CN205791682U - A kind of switching mode lithium battery charging circuit without current sampling resistor and chip - Google Patents
A kind of switching mode lithium battery charging circuit without current sampling resistor and chip Download PDFInfo
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- CN205791682U CN205791682U CN201620543140.8U CN201620543140U CN205791682U CN 205791682 U CN205791682 U CN 205791682U CN 201620543140 U CN201620543140 U CN 201620543140U CN 205791682 U CN205791682 U CN 205791682U
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Abstract
This utility model is applicable to lithium battery charging circuit field, it is provided that a kind of switching mode lithium battery charging circuit without current sampling resistor and chip.This utility model is by additionally arranging an anticipation circuit and a sampling hold circuit in traditional switching mode lithium battery charging circuit, the logic control circuit 0.5 times of time trigger anticipation circuit in the conducting period of on-off circuit is made to send a rising edge signal to sampling hold circuit, the sampled voltage signal that current sampling circuit is exported by triggering sampling hold circuit is sampled and keeps and export a current signal, and compare generation error voltage with reference voltage after described current signal being converted to voltage signal by reference current sampled signal amplifying circuit, enable logic control circuit according to the dutycycle of the ON time of described error voltage adjustment on-off circuit, in the case of need not sampling resistor, control on-off circuit with realization and lithium battery is carried out constant-current charge.
Description
Technical field
This utility model belongs to lithium battery charging circuit field, particularly relates to a kind of switching mode without current sampling resistor
Lithium battery charging circuit and chip.
Background technology
Along with constantly popularizing of the mobile communication equipment such as smart mobile phone, panel computer, the public sets for these mobile communication
Standby flying power requires more and more higher.The advantages such as lithium battery is little with its volume, energy density is high, without memory become mobile
The first-selected supplying cell of communication apparatus.
At present, generally use constant current switch charging circuit that lithium battery is charged, but, existing constant current switch charges
Circuit needs the sampling resistor by resistance accuracy is the highest to be monitored the charging current of lithium battery, this sampling resistor
Relatively costly, add the hardware cost of the electronic equipment entirety relying on lithium battery power supply and reduce charge efficiency.
Utility model content
The purpose of this utility model is to provide a kind of switching mode lithium battery charging circuit without current sampling resistor, purport
Need the sampling resistor by resistance accuracy is the highest that lithium battery is filled solving existing constant current switch charging circuit
Electricity electric current is monitored, and this sampling resistor is relatively costly, and the hardware adding the electronic equipment entirety relying on lithium battery power supply becomes
Basis and the problem reducing charge efficiency.
This utility model is achieved in that a kind of switching mode lithium battery charging circuit without current sampling resistor, institute
State switching mode lithium battery charging circuit and include that on-off circuit, current sampling circuit, inductance L, electric current turn potential circuit, anticipation electricity
Road, sampling hold circuit, reference current sampled signal amplifying circuit, constant current constant voltage switching circuit, PWM comparator, logic control
Circuit, reference voltage sampled signal amplifying circuit and compensation circuit；
The input of described on-off circuit and the first input end of described current sampling circuit are connected to external power source altogether, described
Second input of the outfan of on-off circuit and described current sampling circuit is connected to one end of inductance L, the other end of inductance L altogether
Connect the positive pole of lithium battery；
The output of described current sampling circuit terminates the input of described current-to-voltage converting circuit；
The output of described current-to-voltage converting circuit terminates the input of described sampling hold circuit；
The output of described sampling hold circuit terminates the first input end of described reference current sampled signal amplifying circuit, institute
The first logic signal input end stating sampling hold circuit connects the logical signal outfan of described anticipation circuit, and described sampling keeps
Second logic signal input end of circuit is connected to described logic control circuit altogether with the logic signal input end of described anticipation circuit
Logical signal outfan, the enable input enabling input and described anticipation circuit of described sampling hold circuit is connected to altogether
The enable outfan of described logic control circuit；
The input termination external power source of described anticipation circuit, the positive pole of the output termination lithium battery of described anticipation circuit, institute
State the reference voltage input input reference voltage of anticipation circuit；
Second input termination external power source of described reference current sampled signal amplifying circuit is to produce reference voltage, described
The output of reference current sampled signal amplifying circuit terminates the first input end of described constant current constant voltage switching circuit；
The first input end of described reference voltage sampled signal amplifying circuit connects external power source to produce reference voltage, described
Second input of reference voltage sampled signal amplifying circuit terminates the positive pole of described lithium battery, and described reference voltage sampled signal is put
The output of big circuit terminates the second input of described constant pressure and flow switching circuit；
The output of described constant current constant voltage switching circuit terminates the positive input terminal of described PWM comparator, described PWM comparator
Negative input terminates described compensation circuit；
The output of described PWM comparator singly connects the input of described logic control circuit, described logic control circuit defeated
Go out the controlled end terminating described on-off circuit；
When described on-off circuit turns on, the sampling of described current sampling circuit flows into the sampled current signals of described inductance L,
Described electric current turns potential circuit and described sampled current signals is converted into sampled voltage signal is sent to described sampling hold circuit；
In 0.5 times of moment of the conducting period of described on-off circuit, described logic control circuit triggers described anticipation circuit
Send a rising edge signal to described sampling hold circuit, make described sampling hold circuit that described sampled voltage signal to be carried out
Sample and keep and export a current signal to described reference current sampled signal amplifying circuit；
Described current signal is converted to voltage signal and described benchmark electricity by described reference current sampled signal amplifying circuit
Pressure produces error voltage after comparing, and described error voltage is transferred to through described constant current constant voltage switching circuit and PWM comparator
Described logic control circuit, described logic control circuit adjusts the ON time of described on-off circuit according to described error voltage
Dutycycle, to control the constant charging current of described on-off circuit output to the charging of described lithium battery.
Preferably, described anticipation circuit includes the first logic device, not gate NOT1, not gate NOT2, nor gate NOR1, first puts
Big device, the second amplifier, the 3rd amplifier, PMOS Q1～Q5, NMOS tube Q6～Q11, resistance R1～R6 and electric capacity C1；
The signal input part of described first logic device connects external power source, and the clock signal terminal of described first logic device is described
The logic signal input end of anticipation circuit, the signal output part of described first logic device connects the input of not gate NOT1, and described
The outfan enabling termination nor gate NOR1 of one logic device；
The grid of the outfan of not gate NOT1, the grid of PMOS Q1 and NMOS tube Q6 connects altogether；
The drain electrode of the source electrode of PMOS Q1, the drain electrode of PMOS Q2 and NMOS tube Q7 connects altogether, the drain electrode of PMOS Q1 with
The drain electrode of NMOS tube Q6 is connected with the positive pole of electric capacity C1 and the positive input of the first amplifier after connecing altogether respectively, and electric capacity C1's is negative
Pole connects simulation ground；
The source electrode of NMOS tube Q6 connects the drain electrode of NMOS tube Q8；
The drain electrode of the grid of PMOS Q2, the grid of PMOS Q3, the drain electrode of PMOS Q3 and NMOS tube Q9 connects altogether, PMOS
The source electrode of pipe Q2 and the source electrode of PMOS Q3 are connected to external power source altogether；
The drain electrode of the grid of NMOS tube Q7, the grid of NMOS tube Q8, the grid of NMOS tube Q10 and PMOS Q4 connects altogether,
The source electrode of the source electrode of NMOS tube Q7, the source electrode of NMOS tube Q8 and NMOS tube Q10 all connects simulation ground；
The grid of NMOS tube Q9 connects the outfan of the second amplifier, the source electrode of NMOS tube Q9 and the second amplifier the most defeated
The one end entering end and resistance R1 connects altogether, another termination simulation ground of resistance R1；
The drain electrode of the grid of PMOS Q4, the grid of PMOS Q5, the drain electrode of PMOS Q5 and NMOS tube Q11 connects altogether,
The source electrode of PMOS Q4 and the source electrode of PMOS Q5 are connected to external power source altogether；
The grid of NMOS tube Q11 connects the outfan of the 3rd amplifier, the source electrode of NMOS tube Q11, the 3rd amplifier anti-phase
One end of input and resistance R2 connects altogether, another termination simulation ground of resistance R2；
The first input end of nor gate NOR1 connects the outfan of not gate NOT2, second input of nor gate NOR1 and first
The outfan of amplifier connects the logical signal outfan constituting described anticipation circuit altogether, and the input of not gate NOT2 is described anticipation
The enable input of circuit；
The reverse input end of the first amplifier is the reference voltage input of described anticipation circuit；
The positive input of the second amplifier connects altogether with one end of resistance R3 and one end of resistance R4, the other end of resistance R3
For the input of described anticipation circuit, the other end ground connection of resistance R4, wherein, the resistance of resistance R3 and resistance R4 is equal；
The positive input of the 3rd amplifier connects altogether with one end of one end of resistance R5 and resistance R6, the other end of resistance R5
For the outfan of described anticipation circuit, the other end ground connection of resistance R6, wherein, the resistance of resistance R6 is the three of the resistance of resistance R5
Times；
Before turning on to described on-off circuit after 0.5 times of moment of the conducting period of described on-off circuit, described pre-
The outfan output electric current sentencing circuit makes electric capacity C1 discharge, and the initial voltage of electric capacity C1 is equal to described reference voltage；
Before conducting start time to 0.5 times of moment of the conducting period of described on-off circuit of described on-off circuit,
The input input current of described anticipation circuit charges to electric capacity C1；
After electric capacity C1 charges, when its capacitance voltage is again equal to described reference voltage, described anticipation circuit judges now
For described on-off circuit conducting the period 0.5 times of moment, its logical signal outfan to described sampling hold circuit send one
Individual rising edge signal.
Preferably, described sampling hold circuit includes the second logic device, not gate NOT3～NOT8 and door AND1, anti-phase executes
Schmitt trigger ST1, anti-phase Schmidt trigger ST2, nor gate NOR2, NAND gate NAND1, resistance R7, resistance R8, electric capacity C2
～C5, PMOS Q12, PMOS Q13, NMOS tube Q14～Q16, switch S1 and switch S2；
The signal input part of the second logic device connects external power source, the signal output part of the second logic device, not gate NOT3 defeated
Enter end, the grid of PMOS Q12, the grid of NMOS tube Q14 and the first input end with door AND1 to connect altogether, the second logic device time
Clock signal end is the first logic signal input end of described sampling hold circuit, the enable termination nor gate NOR2 of the second logic device
Outfan, the outfan of not gate NOT3 constitutes the controlling of sampling end of described sampling hold circuit；
The source electrode of PMOS Q12 connects external power source, the drain electrode of PMOS Q12, the input of anti-phase Schmidt trigger ST1
The positive pole of end, one end of resistance R7 and electric capacity C2 connects altogether；
The other end of the drain electrode connecting resistance R7 of NMOS tube 14, the source electrode of NMOS tube 14 is connected to simulation altogether with the negative pole of electric capacity C2
Ground；
With the outfan of the second input termination not gate NOT4 of door AND1, the output with door AND1 terminates the defeated of not gate NOT5
Entering end, the outfan of not gate NOT5 constitutes the holding of described sampling hold circuit and controls end, and the input termination of not gate NOT4 is anti-phase
The outfan of Schmidt trigger ST1；
The first input end of nor gate NOR2 connects the outfan of not gate NOT6, the second input termination not gate of nor gate NOR2
The outfan of NOT7, the input of not gate NOT7 is the enable input of described sampling hold circuit；
The outfan of input termination NAND gate NAND1 of not gate NOT6, the first input end of NAND gate NAND1 connects not gate
The outfan of NOT8, the grid of the second input of NAND gate NAND`, the grid of PMOS Q13 and NMOS tube Q15 connects composition altogether
Second logic signal input end of described sampling hold circuit；
The outfan of the input termination Schmidt trigger ST2 of not gate NOT8, the input of Schmidt trigger ST2, electricity
The drain electrode holding the positive pole of C3, one end of resistance R8 and PMOS Q13 connects altogether, and the source electrode of PMOS Q13 connects external power source；
The other end of the drain electrode connecting resistance R8 of NMOS tube Q15, the source electrode of NMOS tube Q15 is connected to mould altogether with the negative pole of electric capacity C3
Intend ground；
Switch S1 the input that one end is described sampling hold circuit, switch the other end of S1, the positive pole of electric capacity C4 and
One end of switch S2 connects altogether；
The grid of the switch other end of S2, the positive pole of electric capacity C5 and NMOS tube Q16 connects altogether, and the drain electrode of NMOS tube Q16 is institute
Stating the outfan of sampling hold circuit, the source electrode of the negative pole of electric capacity C4, the negative pole of electric capacity C5 and NMOS tube Q16 is connected to simulation altogether
Ground；
In the conducting start time of described on-off circuit, described sampling hold circuit receive the upper of described anticipation circuit
Rising along signal, described controlling of sampling end triggers switch S1 Guan Bi, and now switch S2 disconnects, the input input of sampling hold circuit
Described electric current turns the sampled voltage signal of potential circuit output and charges to electric capacity C4；
In 0.5 times of moment of the conducting period of described on-off circuit, described controlling of sampling end triggers switch S1 and disconnects, now
Electric capacity C4 storage has the sampled current signals corresponding to described 0.5 times of moment；
Before turning on to described on-off circuit after 0.5 times of moment of the conducting period of described on-off circuit, described guarantor
Hold control end and trigger switch S2 Guan Bi, make electric capacity C4 charge to electric capacity C5, when the voltage of electric capacity C4 is equal with the voltage of electric capacity C5
Time, described holding controls end and triggers switch S2 disconnection, makes electric capacity C5 storage sample rate current letter corresponding to described 0.5 times of moment
Number, described sampled current signals is through NMOS tube Q16 output extremely described reference current sampled signal amplifying circuit.
Preferably, described reference current sampled signal amplifying circuit include by the first equivalent current source, NMOS tube Q17,
NMOS tube Q18, PMOS Q19 and the reference current generation unit of PMOS Q20 composition；
The described input of the first equivalent current source connects composition altogether with the source electrode of the source electrode of PMOS Q19 and PMOS Q20
The input of described reference current sampled signal amplifying circuit, the outfan of described first equivalent current source and NMOS tube Q17
The grid of drain electrode, the grid of NMOS tube Q17 and NMOS tube Q18 connects altogether, and the source electrode of NMOS tube Q17 and the source electrode of NMOS tube Q18 are altogether
It is connected to simulation ground；
The grid of PMOS Q19, the grid of PMOS Q20, the drain electrode of PMOS Q19 and the drain electrode of NMOS tube Q18 connect altogether,
The first input end that drain electrode is described reference current sampled signal amplifying circuit of PMOS Q20 and outfan；
Described first equivalent current source produces a reference current and flows through PMOS Q20, this reference current and described sampling
The sampled current signals of holding circuit output forms error voltage by the equivalent resistance between PMOS Q20 and NMOS tube Q16
And export to described constant current constant voltage switching circuit.
Preferably, described reference current sampled signal amplifying circuit includes error amplifier and reference voltage generation unit；
Described reference voltage generation unit includes the second equivalent current source, NMOS tube Q21, NMOS tube Q22, resistance R9 and resistance R10；
The positive input of described error amplifier connects the described reference current sampled signal of composition altogether with one end of resistance R9
One end of the first input end of amplifying circuit, the reverse input end of described error amplifier and resistance R10 and the leakage of NMOS tube Q21
Connecing the most altogether, the outfan of described error amplifier is the outfan of described reference current sampled signal amplifying circuit；
The input of described second equivalent current source meets composition institute altogether with the other end of the other end of resistance R9 and resistance R10
State the second input of reference current sampled signal amplifying circuit, the outfan of described second equivalent current source and NMOS tube Q21
The grid of drain electrode, the grid of NMOS tube Q21 and NMOS tube Q22 connect altogether, the source electrode of NMOS tube Q21 and the source electrode of NMOS tube Q22
It is connected to simulation ground altogether；
Described second equivalent current source produces a reference current and flows through resistance R10, makes to produce reference voltage on resistance R10
The reverse input end of output extremely described error amplifier, the sampled current signals of described sampling hold circuit output is through resistance R9
Being converted into voltage signal, the difference between described voltage signal and described reference voltage is amplified by described error amplifier,
Thus produce error voltage and export to described constant current constant voltage switching circuit.
Preferably, described electric current turns potential circuit and includes NMOS tube Q23, the drain electrode of NMOS tube Q23 be connected with grid after structure
Becoming described electric current to turn input and the outfan of potential circuit, the source electrode of NMOS tube Q23 connects simulation ground；
The drain electrode of NMOS tube Q23 is inputted described sampled current signals and is converted to sampled voltage signal and is exported by its grid
To described sampling hold circuit.
Preferably, described on-off circuit includes PMOS Q24 and diode D1；
The grid of PMOS Q24 is the controlled end of described on-off circuit, and the drain electrode of PMOS Q24 is described on-off circuit
Input, the source electrode of PMOS Q24 connects, with the negative pole of diode D1, the outfan constituting described on-off circuit altogether, diode D1's
Plus earth.
Preferably, described on-off circuit also includes NMOS tube Q25；
The grid of NMOS tube Q25 is another controlled end of described on-off circuit, and the drain electrode of NMOS tube Q25 meets described PMOS
The source electrode of pipe Q24, the source ground of NMOS tube Q25.
Preferably, described switching mode lithium battery charging circuit also includes resistance R11, resistance R12 and electric capacity C6；
One end of resistance R11, the positive pole of electric capacity C6, the other end of inductance L are connected to the positive pole of lithium battery altogether, resistance R11's
The other end, one end of resistance R12 connect altogether with the second input of described reference voltage sampled signal amplifying circuit, resistance R12's
The negative pole of the other end, the negative pole of electric capacity C6 and lithium battery is connected to ground altogether.
This utility model also provides for a kind of switching mode lithium cell charging chip without current sampling resistor, described switching mode
Lithium cell charging chip includes the switching mode lithium battery charging circuit as described in front any one.
Compared with prior art, it has the beneficial effects that this utility model:
By arranging an anticipation circuit and a sampling hold circuit, make logic control circuit in the conducting of on-off circuit
0.5 times of time trigger anticipation circuit of period sends a rising edge signal to sampling hold circuit, triggers sampling hold circuit
The sampled voltage signal of current sampling circuit output is sampled and keeps and export a current signal, and by benchmark electricity
Stream sampled signal amplifying circuit compares generation error electricity with reference voltage after described current signal is converted to voltage signal
Pressure, enables logic control circuit according to the dutycycle of the ON time of described error voltage adjustment on-off circuit, exists with realization
Control on-off circuit in the case of need not sampling resistor and lithium battery is carried out constant-current charge.
Accompanying drawing explanation
Fig. 1 is the base of the switching mode lithium battery charging circuit without current sampling resistor that this utility model embodiment provides
This structured flowchart；
Fig. 2 is the tool of the switching mode lithium battery charging circuit without current sampling resistor that this utility model embodiment provides
Body structured flowchart；
Fig. 3 is the circuit theory diagrams of the anticipation circuit that this utility model embodiment provides；
Fig. 4 is that the electric current that this utility model embodiment provides turns voltage cell, sampling hold circuit and reference current sampling
The circuit theory diagrams of signal amplification circuit；
Fig. 5 is the circuit theory diagrams of the reference current sampled signal amplifying circuit that this utility model embodiment provides.
Detailed description of the invention
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing and enforcement
Example, is further elaborated to this utility model.Should be appreciated that specific embodiment described herein is only in order to explain this
Utility model, is not used to limit this utility model.
As it is shown in figure 1, the switching mode lithium battery charging circuit without current sampling resistor that the present embodiment provides includes out
Pass circuit 10, current sampling circuit 20, inductance L, electric current turn potential circuit 30, anticipation circuit 40, sampling hold circuit 50, benchmark
Current sampling signal amplifying circuit 60, constant current constant voltage switching circuit 70, PWM comparator 80, logic control circuit 90, reference voltage
Sampled signal amplifying circuit 00 and compensation circuit 01.
The input of on-off circuit 10 and the first input end of current sampling circuit 20 are connected to external power source VIN altogether, switch
Second input of the outfan of circuit 10 and current sampling circuit 20 is connected to one end of inductance L altogether, another termination lithium of inductance L
The positive pole of battery BAT；
The input of the output termination current-to-voltage converting circuit 30 of current sampling circuit 20；
The input of the output termination sampling hold circuit 50 of current-to-voltage converting circuit 30；
The first input end of the output termination reference current sampled signal amplifying circuit 60 of sampling hold circuit 50, sampling is protected
The first logic signal input end holding circuit 50 connects the logical signal outfan of anticipation circuit 40, the second of sampling hold circuit 50
The logic signal input end 40 of logic signal input end and anticipation circuit is connected to the logical signal output of logic control circuit 90 altogether
End, the enable input of sampling hold circuit 50 is connected to making of logic control circuit 90 altogether with the input that enables of anticipation circuit 40
Can outfan；
The input termination external power source VIN of anticipation circuit 40, the positive pole of the output termination lithium battery of anticipation circuit 40, anticipation
The reference voltage input input reference voltage of circuit 40；
Second input termination external power source of reference current sampled signal amplifying circuit 60 is to produce reference voltage, and benchmark is electric
The first input end of the output termination constant current constant voltage switching circuit 70 of stream sampled signal amplifying circuit 60；
The first input end of reference voltage sampled signal amplifying circuit 00 connects external power source to produce reference voltage, benchmark electricity
The positive pole of the second input termination lithium battery BAT of pressure sampled signal amplifying circuit 00, reference voltage sampled signal amplifying circuit 00
Output termination constant pressure and flow switching circuit 70 the second input；
The positive input terminal of the output termination PWM comparator 80 of constant current constant voltage switching circuit 70, the negative input of PWM comparator 80
Termination compensates circuit 01；
The output of PWM comparator 80 singly connects the input of logic control circuit 90, the output termination of logic control circuit 90
The controlled end of on-off circuit 10；
In the present embodiment, on-off circuit 10 includes PMOS Q24 and diode D1；The grid of PMOS Q24 is switch
The controlled end of circuit 10, the input that drain electrode is on-off circuit 10 of PMOS Q24, the source electrode of PMOS Q24 and diode D1
Negative pole altogether connect constitute on-off circuit 10 outfan, the plus earth of diode D1.
When on-off circuit 10 turns on, current sampling circuit 20 sampling flows into the sampled current signals of inductance L, and electric current turns electricity
Sampled current signals is converted into sampled voltage signal and is sent to sampling hold circuit 50 by volt circuit 30；
In 0.5 times of moment of the conducting period of on-off circuit, logic control circuit 90 triggers anticipation circuit 40 and protects to sampling
Hold circuit 50 and send a rising edge signal, make sampling hold circuit 50 sampled voltage signal be sampled and keep and export
One current signal is to reference current sampled signal amplifying circuit 60；
Current signal is converted to voltage signal and compares with reference voltage by reference current sampled signal amplifying circuit 60
Rear generation error voltage, described error voltage is transferred to logic control electricity through constant current constant voltage switching circuit 70 and PWM comparator 80
Road 90, logic control circuit 90 adjusts the dutycycle of the ON time of on-off circuit 10 according to described error voltage, to control to open
Close circuit 10 and export the charging to lithium battery BAT of the constant charging current.
As in figure 2 it is shown, the switching mode lithium battery charging circuit without current sampling resistor in the present embodiment offer also wraps
Include resistance R11, resistance R12 and electric capacity C6；One end of resistance R11, the positive pole of electric capacity C6, the other end of inductance L are connected to lithium electricity altogether
The positive pole in pond, the other end of resistance R11, one end of resistance R12 input with the second of reference voltage sampled signal amplifying circuit 00
End connects altogether, and the negative pole of the other end of resistance R12, the negative pole of electric capacity C6 and lithium battery BAT is connected to ground altogether.
On-off circuit 10 also includes NMOS tube Q25, and the grid of NMOS tube Q25 is another controlled end of on-off circuit 10,
The drain electrode of NMOS tube Q25 connects the source electrode of described PMOS Q24, the source ground of NMOS tube Q25.
Reference current sampled signal amplifying circuit 60 includes error amplifier 61 and reference voltage generation unit 62, wherein,
The positive input of error amplifier 61 is as the input of reference current sampled signal amplifying circuit 60 and sampling hold circuit
The outfan of 50 connects, the outfan of error amplifier 61 as the outfan of reference current sampled signal amplifying circuit 60 with horizontal
The input of stream constant voltage switch unit connects；The outfan of reference voltage generation unit 62 inputs with the reverse of error amplifier 61
End connects, and is used for inputting external power source to produce reference voltage.
Logic control circuit 90 includes the power tube driver element that logical block 91 is connected with the outfan of logical block 91
92 and the agitator 93 that is connected with logical block 91, wherein, the first input end of logical block 91 is logic control circuit 90
Input, the Enable Pin of logical block 91 is the enable outfan of logic control circuit 90, patrolling of power tube driver element 92
Collecting the logical signal outfan that signal end is logic control circuit 90, the second of the output termination logical block 91 of agitator 93 is defeated
Enter end, provide clock signal for logical block 91.
Reference voltage sampled signal amplifying circuit 00 includes error amplifier 001 and reference voltage generation unit 002, its
In, the reverse input end of error amplifier 001 is as the second input of reference voltage sampled signal amplifying circuit 00, and error is put
The input of the outfan of big device 001 outfan as reference voltage sampled signal amplifying circuit 00 and crossing current constant voltage switch unit
End connects；The outfan of reference voltage generation unit 002 is connected with the positive input of error amplifier 001, outside being used for inputting
Portion's power supply is to produce reference voltage.
Compensate circuit 01 and gather current sample, slope compensation and bias current overlaying function.
As it is shown on figure 3, in the present embodiment, anticipation circuit 40 include the first logic device 41, not gate NOT1, not gate NOT2,
Nor gate NOR1, first amplifier the 42, second amplifier the 43, the 3rd amplifier 44, PMOS Q1～Q5, NMOS tube Q6～Q11,
Resistance R1～R6 and electric capacity C1.
The signal input part D of the first logic device 41 meets external power source VDD, the clock signal terminal CLK of the first logic device 41
Logic signal input end Power_PMOS_Turn_ON_Logic of anticipation circuit 40, the signal output part Q of the first logic device 41
Connect the input of not gate NOT1, the Enable Pin of the first logic device 41Connect the outfan of nor gate NOR1；
The grid of the outfan of not gate NOT1, the grid of PMOS Q1 and NMOS tube Q6 connects altogether；
The drain electrode of the source electrode of PMOS Q1, the drain electrode of PMOS Q2 and NMOS tube Q7 connects altogether, the drain electrode of PMOS Q1 with
The drain electrode of NMOS tube Q6 is connected with the positive pole of electric capacity C1 and the positive input of the first amplifier 42 after connecing altogether respectively, electric capacity C1's
Negative pole connects simulation ground；
The source electrode of NMOS tube Q6 connects the drain electrode of NMOS tube Q8；
The drain electrode of the grid of PMOS Q2, the grid of PMOS Q3, the drain electrode of PMOS Q3 and NMOS tube Q9 connects altogether, PMOS
The source electrode of pipe Q2 and the source electrode of PMOS Q3 are connected to external power source VDD altogether；
The drain electrode of the grid of NMOS tube Q7, the grid of NMOS tube Q8, the grid of NMOS tube Q10 and PMOS Q4 connects altogether,
The source electrode of the source electrode of NMOS tube Q7, the source electrode of NMOS tube Q8 and NMOS tube Q10 all connects simulation ground；
The grid of NMOS tube Q9 connects the outfan of the second amplifier 43, the source electrode of NMOS tube Q9 and the second amplifier 43 anti-
Connect altogether to one end of input and resistance R1, another termination simulation ground of resistance R1；
The drain electrode of the grid of PMOS Q4, the grid of PMOS Q5, the drain electrode of PMOS Q5 and NMOS tube Q11 connects altogether,
The source electrode of PMOS Q4 and the source electrode of PMOS Q5 are connected to external power source VDD altogether；
The grid of NMOS tube Q11 connects the outfan of the 3rd amplifier 44, the source electrode of NMOS tube Q11, the 3rd amplifier 44
One end of inverting input and resistance R2 connects altogether, another termination simulation ground of resistance R2；
The first input end of nor gate NOR1 connects the outfan of not gate NOT2, second input of nor gate NOR1 and first
The outfan of amplifier 42 meets the logical signal outfan OUT constituting anticipation circuit 40 altogether, and the input of not gate NOT2 is anticipation
The enable input Enable of circuit 40；
Reference voltage input V that reverse input end is anticipation circuit 40 of the first amplifier 42Initial；
The positive input of the second amplifier 43 connects altogether with one end of one end of resistance R3 and resistance R4, another of resistance R3
End is the other end ground connection of the input VIN, resistance R4 of anticipation circuit 40, and wherein, the resistance of resistance R3 and resistance R4 is equal；
The positive input of the 3rd amplifier 44 connects altogether with one end of one end of resistance R5 and resistance R6, another of resistance R5
End is the other end ground connection of the outfan VOUT, resistance R6 of anticipation circuit 40, and wherein, the resistance of resistance R6 is the resistance of resistance R5
Three times；
Before turning on to on-off circuit 10 after 0.5 times of moment of the conducting period of on-off circuit 10, anticipation circuit 40
Outfan output electric current make electric capacity C1 discharge, the initial voltage of electric capacity C1 is equal to reference voltage；
Before conducting start time to 0.5 times of moment of the conducting period of on-off circuit 10 of on-off circuit 10, anticipation
The input input current of circuit 40 charges to electric capacity C1；
After electric capacity C1 charges, when its capacitance voltage is again equal to reference voltage, anticipation circuit 40 judges now as switch
In 0.5 times of moment of the conducting period of circuit 10, its logical signal outfan sends a rising edge letter to sampling hold circuit 50
Number.
As shown in Fig. 4 or Fig. 5, current sampling circuit 20 with an equivalent current source-representation, described equivalent current source defeated
Entering end and outfan is respectively input and the outfan of described current sampling circuit 20, current sampling circuit 20 is to external power source
Current signal sample, output sampled current signals Isense turns the input of potential circuit 30 to electric current.
As shown in Fig. 4 or Fig. 5, electric current turns potential circuit 30 and includes NMOS tube Q23, and the drain electrode of NMOS tube Q23 is with grid even
Constituting electric current after connecing and turn input and the outfan of potential circuit 30, the source electrode of NMOS tube Q23 connects simulation ground；
The drain electrode of NMOS tube Q23 inputs described sampled current signals Isense and is converted to sampled voltage signal by its grid
Pole exports to sampling hold circuit 50.
As shown in Figure 4, sampling hold circuit 50 includes the second logic device 51, not gate NOT3～NOT8 and door AND1, anti-phase
Schmidt trigger ST1, anti-phase Schmidt trigger ST2, nor gate NOR2, NAND gate NAND1, resistance R7, resistance R8, electric capacity
C2～C5, PMOS Q12, PMOS Q13, NMOS tube Q14～Q16, switch S1 and switch S2；
The signal input part D of the second logic device 51 connects external power source VDD, the signal output part Q of the second logic device 51, not gate
The input of NOT3, the grid of PMOS Q12, the grid of NMOS tube Q14 and the first input end with door AND1 connect altogether, and second patrols
Collect first logic signal input end that clock signal terminal CLK is described sampling hold circuit 50 of device 51, the second logic device 51
Enable PinConnecing the outfan of nor gate NOR2, the outfan of not gate NOT3 constitutes the controlling of sampling of described sampling hold circuit 50
End Sample；
The source electrode of PMOS Q12 meets external power source VDD, the drain electrode of PMOS Q12, anti-phase Schmidt trigger ST1 defeated
The positive pole entering end, one end of resistance R7 and electric capacity C2 connects altogether；
The other end of the drain electrode connecting resistance R7 of NMOS tube Q14, the source electrode of NMOS tube 14 is connected to mould altogether with the negative pole of electric capacity C2
Intend ground；
With the outfan of the second input termination not gate NOT4 of door AND1, the output with door AND1 terminates the defeated of not gate NOT5
Entering end, the outfan of not gate NOT5 constitutes the holding of described sampling hold circuit 50 and controls end Charge, the input of not gate NOT4
Terminate the outfan of anti-phase Schmidt trigger ST1；
The first input end of nor gate NOR2 connects the outfan of not gate NOT6, the second input termination not gate of nor gate NOR2
The outfan of NOT7, the input of not gate NOT7 is the enable input Enable of described sampling hold circuit 50；
The outfan of input termination NAND gate NAND1 of not gate NOT6, the first input end of NAND gate NAND1 connects not gate
The outfan of NOT8, the grid of the second input of NAND gate NAND`, the grid of PMOS Q13 and NMOS tube Q15 connects composition altogether
Second logic signal input end Power_PMOS_Turn_ON_Logic of described sampling hold circuit 50；
The outfan of the input termination Schmidt trigger ST2 of not gate NOT8, the input of Schmidt trigger ST2, electricity
The drain electrode holding the positive pole of C3, one end of resistance R8 and PMOS Q13 connects altogether, and the source electrode of PMOS Q13 connects external power source；
The other end of the drain electrode connecting resistance R8 of NMOS tube Q15, the source electrode of NMOS tube Q15 is connected to mould altogether with the negative pole of electric capacity C3
Intend ground；
The input that one end is described sampling hold circuit 50 of switch S1, switchs the other end of S1, the positive pole of electric capacity C4
Connect altogether with one end of switch S2；
The grid of the switch other end of S2, the positive pole of electric capacity C5 and NMOS tube Q16 connects altogether, and the drain electrode of NMOS tube Q16 is institute
Stating the outfan of sampling hold circuit 50, the source electrode of the negative pole of electric capacity C4, the negative pole of electric capacity C5 and NMOS tube Q16 is connected to simulation altogether
Ground；
In the conducting start time of on-off circuit 10, the rising edge letter receiving anticipation circuit 40 of sampling hold circuit 50
Number, described controlling of sampling end Sample triggers switch S1 Guan Bi, and now switch S2 disconnects, and the input of sampling hold circuit 50 is defeated
Enter electric current and turn the sampled voltage signal of potential circuit 30 output to electric capacity C4 charging；
In 0.5 times of moment of the conducting period of on-off circuit 10, described controlling of sampling end Sample triggers switch S1 and disconnects,
Now electric capacity C4 storage has the sampled current signals corresponding to described 0.5 times of moment；
Before turning on to on-off circuit 10 after 0.5 times of moment of the conducting period of on-off circuit 10, described holding, is controlled
End Charge processed triggers switch S2 Guan Bi, makes electric capacity C4 charge to electric capacity C5, when the voltage phase of voltage and the electric capacity C5 of electric capacity C4
Deng time, described holding controls end Charge and triggers switch S2 and disconnect, and makes electric capacity C5 storage sampling corresponding to described 0.5 times of moment
Current signal, described sampled current signals exports to reference current sampled signal amplifying circuit 60 through NMOS tube Q16.
As shown in Figure 4, reference current sampled signal amplifying circuit 60 includes that error amplifier 61 and reference voltage produce list
Unit 62；Reference voltage generation unit 62 includes the second equivalent current source 621, NMOS tube Q21, NMOS tube Q22, resistance R9 and resistance
R10；
The positive input of error amplifier 61 and one end of resistance R9 connect composition reference current sampled signal altogether and amplify electric
The first input end on road 60, the reverse input end of error amplifier 61 is total to one end of resistance R10 and the drain electrode of NMOS tube Q21
Connect, the outfan of current sampling signal amplifying circuit 60 on the basis of the outfan of error amplifier 61；
The input of the second equivalent current source 621 connects composition base altogether with the other end of the other end of resistance R9 and resistance R10
Second input of quasi-current sampling signal amplifying circuit 60, the outfan of the second equivalent current source 621 and the leakage of NMOS tube Q21
The grid of pole, the grid of NMOS tube Q21 and NMOS tube Q22 connects altogether, and the source electrode of NMOS tube Q21 and the source electrode of NMOS tube Q22 connect altogether
In simulation ground；
Second equivalent current source 621 produces a reference current and flows through resistance R10, makes to produce reference voltage on resistance R10
Exporting the reverse input end to error amplifier, the sampled current signals of sampling hold circuit output is converted into electricity through resistance R9
Pressure signal, the difference between described voltage signal and described reference voltage is amplified, thus produces error by error amplifier
Voltage also exports to constant current constant voltage switching circuit.
As it is shown in figure 5, in the present embodiment, reference current sampled signal amplifying circuit 60 includes by the first equivalent current source
63, NMOS tube Q17, NMOS tube Q18, PMOS Q19 and the reference current generation unit of PMOS Q20 composition；
The input of the first equivalent current source 63 connects composition base altogether with the source electrode of the source electrode of PMOS Q19 and PMOS Q20
The input of quasi-current sampling signal amplifying circuit 60, the outfan of the first equivalent current source 63 and the drain electrode of NMOS tube Q17,
The grid of NMOS tube Q17 and the grid of NMOS tube Q18 connect altogether, and the source electrode of NMOS tube Q17 and the source electrode of NMOS tube Q18 are connected to mould altogether
Intend ground；
The grid of PMOS Q19, the grid of PMOS Q20, the drain electrode of PMOS Q19 and the drain electrode of NMOS tube Q18 connect altogether,
The first input end of current sampling signal amplifying circuit 60 and outfan on the basis of the drain electrode of PMOS Q20；
First equivalent current source 63 produces a reference current and flows through PMOS Q20, and this reference current and sampling keep electricity
The sampled current signals of road 50 output forms error voltage defeated by equivalent resistance between PMOS Q20 and NMOS tube Q16
Go out to constant current constant voltage switching circuit 70.
This utility model embodiment also provides for a kind of switching mode lithium cell charging chip without current sampling resistor, including
Foregoing switching mode lithium battery charging circuit.In a particular application, on-off circuit can be arranged on described switching mode lithium electricity
Outside the charging chip of pond, it is also possible to be integrated in described switching mode lithium cell charging chip internal.
The foregoing is only preferred embodiment of the present utility model, not in order to limit this utility model, all at this
Any amendment, equivalent and the improvement etc. made within the spirit of utility model and principle, should be included in this utility model
Protection domain within.
Claims (10)
1. the switching mode lithium battery charging circuit without current sampling resistor, it is characterised in that described switching mode lithium battery
Charging circuit include on-off circuit, current sampling circuit, inductance L, electric current turn potential circuit, anticipation circuit, sampling hold circuit,
Reference current sampled signal amplifying circuit, constant current constant voltage switching circuit, PWM comparator, logic control circuit, reference voltage are sampled
Signal amplification circuit and compensation circuit；
The input of described on-off circuit and the first input end of described current sampling circuit are connected to external power source, described switch altogether
Second input of the outfan of circuit and described current sampling circuit is connected to one end of inductance L altogether, another termination lithium of inductance L
The positive pole of battery；
The output of described current sampling circuit terminates the input of described current-to-voltage converting circuit；
The output of described current-to-voltage converting circuit terminates the input of described sampling hold circuit；
Described sampling hold circuit output terminate described reference current sampled signal amplifying circuit first input end, described in adopt
First logic signal input end of sample holding circuit connects the logical signal outfan of described anticipation circuit, described sampling hold circuit
The logic signal input end of the second logic signal input end and described anticipation circuit be connected to patrolling of described logic control circuit altogether
Collecting signal output part, the input that enables of described sampling hold circuit is connected to described with the enable input of described anticipation circuit altogether
The enable outfan of logic control circuit；
The input termination external power source of described anticipation circuit, the positive pole of the output termination lithium battery of described anticipation circuit, described pre-
Sentence the reference voltage input input reference voltage of circuit；
Described reference current sampled signal amplifying circuit second input termination external power source to produce reference voltage, described benchmark
The output of current sampling signal amplifying circuit terminates the first input end of described constant current constant voltage switching circuit；
The first input end of described reference voltage sampled signal amplifying circuit connects external power source to produce reference voltage, described benchmark
Second input of voltage sampling signal amplifying circuit terminates the positive pole of described lithium battery, and described reference voltage sampled signal amplifies electricity
The output on road terminates the second input of described constant pressure and flow switching circuit；
The output of described constant current constant voltage switching circuit terminates the positive input terminal of described PWM comparator, described PWM comparator negative defeated
Enter to terminate described compensation circuit；
The output of described PWM comparator singly connects the input of described logic control circuit, the outfan of described logic control circuit
Connect the controlled end of described on-off circuit；
When described on-off circuit turns on, the sampling of described current sampling circuit flows into the sampled current signals of described inductance L, described
Electric current turns potential circuit and described sampled current signals is converted into sampled voltage signal is sent to described sampling hold circuit；
In 0.5 times of moment of the conducting period of described on-off circuit, described logic control circuit triggers described anticipation circuit to institute
State sampling hold circuit and send a rising edge signal, make described sampling hold circuit that described sampled voltage signal to be sampled
With keep and export a current signal give described reference current sampled signal amplifying circuit；
Described current signal is converted to voltage signal and enters with described reference voltage by described reference current sampled signal amplifying circuit
Producing error voltage after Hang, described error voltage is transferred to described through described constant current constant voltage switching circuit and PWM comparator
Logic control circuit, described logic control circuit adjusts the duty of the ON time of described on-off circuit according to described error voltage
Ratio, to control the constant charging current of described on-off circuit output to the charging of described lithium battery.
2. as claimed in claim 1 without the switching mode lithium battery charging circuit of current sampling resistor, it is characterised in that described
Anticipation circuit include the first logic device, not gate NOT1, not gate NOT2, nor gate NOR1, the first amplifier, the second amplifier,
Three amplifiers, PMOS Q1～Q5, NMOS tube Q6～Q11, resistance R1～R6 and electric capacity C1；
The signal input part of described first logic device connects external power source, and the clock signal terminal of described first logic device is described anticipation
The logic signal input end of circuit, the signal output part of described first logic device connects the input of not gate NOT1, and described first patrols
Collect the outfan enabling termination nor gate NOR1 of device；
The grid of the outfan of not gate NOT1, the grid of PMOS Q1 and NMOS tube Q6 connects altogether；
The drain electrode of the source electrode of PMOS Q1, the drain electrode of PMOS Q2 and NMOS tube Q7 connects altogether, the drain electrode of PMOS Q1 and NMOS tube
The drain electrode of Q6 is connected with the positive pole of electric capacity C1 and the positive input of the first amplifier after connecing altogether respectively, and the negative pole of electric capacity C1 connects mould
Intend ground；
The source electrode of NMOS tube Q6 connects the drain electrode of NMOS tube Q8；
The drain electrode of the grid of PMOS Q2, the grid of PMOS Q3, the drain electrode of PMOS Q3 and NMOS tube Q9 connects altogether, PMOS Q2
Source electrode and the source electrode of PMOS Q3 be connected to external power source altogether；
The drain electrode of the grid of NMOS tube Q7, the grid of NMOS tube Q8, the grid of NMOS tube Q10 and PMOS Q4 connects altogether, NMOS tube
The source electrode of the source electrode of Q7, the source electrode of NMOS tube Q8 and NMOS tube Q10 all connects simulation ground；
The grid of NMOS tube Q9 connects the outfan of the second amplifier, the source electrode of NMOS tube Q9 and the reverse input end of the second amplifier
Connect altogether with one end of resistance R1, another termination simulation ground of resistance R1；
The drain electrode of the grid of PMOS Q4, the grid of PMOS Q5, the drain electrode of PMOS Q5 and NMOS tube Q11 connects altogether, PMOS
The source electrode of Q4 and the source electrode of PMOS Q5 are connected to external power source altogether；
The grid of NMOS tube Q11 connects the outfan of the 3rd amplifier, the source electrode of NMOS tube Q11, the anti-phase input of the 3rd amplifier
One end of end and resistance R2 connects altogether, another termination simulation ground of resistance R2；
The first input end of nor gate NOR1 connects the outfan of not gate NOT2, and second input of nor gate NOR1 and first amplifies
The outfan of device connects the logical signal outfan constituting described anticipation circuit altogether, and the input of not gate NOT2 is described anticipation circuit
Enable input；
The reverse input end of the first amplifier is the reference voltage input of described anticipation circuit；
The positive input of the second amplifier connects altogether with one end of resistance R3 and one end of resistance R4, and the other end of resistance R3 is institute
Stating the input of anticipation circuit, the other end ground connection of resistance R4, wherein, the resistance of resistance R3 and resistance R4 is equal；
The positive input of the 3rd amplifier connects altogether with one end of one end of resistance R5 and resistance R6, and the other end of resistance R5 is institute
Stating the outfan of anticipation circuit, the other end ground connection of resistance R6, wherein, the resistance of resistance R6 is three times of the resistance of resistance R5；
Before turning on to described on-off circuit after 0.5 times of moment of the conducting period of described on-off circuit, described anticipation electricity
The outfan output electric current on road makes electric capacity C1 discharge, and the initial voltage of electric capacity C1 is equal to described reference voltage；
Before conducting start time to 0.5 times of moment of the conducting period of described on-off circuit of described on-off circuit, described
The input input current of anticipation circuit charges to electric capacity C1；
After electric capacity C1 charges, when its capacitance voltage is again equal to described reference voltage, described anticipation circuit judges now for institute
Stating 0.5 times of moment of the conducting period of on-off circuit, its logical signal outfan is on described sampling hold circuit sends one
Rise along signal.
3. as claimed in claim 1 without the switching mode lithium battery charging circuit of current sampling resistor, it is characterised in that described
Sampling hold circuit includes the second logic device, not gate NOT3～NOT8 and door AND1, anti-phase Schmidt trigger ST1, anti-phase executes
Schmitt trigger ST2, nor gate NOR2, NAND gate NAND1, resistance R7, resistance R8, electric capacity C2～C5, PMOS Q12, PMOS
Pipe Q13, NMOS tube Q14～Q16, switch S1 and switch S2；
The signal input part of the second logic device connects external power source, the signal output part of the second logic device, the input of not gate NOT3,
The grid of PMOS Q12, the grid of NMOS tube Q14 and the first input end with door AND1 connect altogether, the clock letter of the second logic device
Number end is the first logic signal input end of described sampling hold circuit, the second logic device enable the defeated of termination nor gate NOR2
Going out end, the outfan of not gate NOT3 constitutes the controlling of sampling end of described sampling hold circuit；
The source electrode of PMOS Q12 connects external power source, the drain electrode of PMOS Q12, the input of anti-phase Schmidt trigger ST1, electricity
One end of resistance R7 and the positive pole of electric capacity C2 connect altogether；
The other end of the drain electrode connecting resistance R7 of NMOS tube 14, the source electrode of NMOS tube 14 is connected to simulation ground altogether with the negative pole of electric capacity C2；
With the outfan of the second input termination not gate NOT4 of door AND1, the output with door AND1 terminates the input of not gate NOT5
End, the outfan of not gate NOT5 constitutes the holding of described sampling hold circuit and controls end, and the input termination of not gate NOT4 is anti-phase to be executed
The outfan of schmitt trigger ST1；
The first input end of nor gate NOR2 connects the outfan of not gate NOT6, the second input termination not gate NOT7 of nor gate NOR2
Outfan, the input of not gate NOT7 is the enable input of described sampling hold circuit；
The outfan of input termination NAND gate NAND1 of not gate NOT6, the first input end of NAND gate NAND1 connects not gate NOT8's
Outfan, the grid of the second input of NAND gate NAND`, the grid of PMOS Q13 and NMOS tube Q15 connects described in composition altogether to be adopted
Second logic signal input end of sample holding circuit；
The outfan of the input termination Schmidt trigger ST2 of not gate NOT8, the input of Schmidt trigger ST2, electric capacity C3
The drain electrode of positive pole, one end of resistance R8 and PMOS Q13 connect altogether, the source electrode of PMOS Q13 connects external power source；
The other end of the drain electrode connecting resistance R8 of NMOS tube Q15, the source electrode of NMOS tube Q15 is connected to simulation altogether with the negative pole of electric capacity C3
Ground；
The input that one end is described sampling hold circuit of switch S1, the switch other end of S1, the positive pole of electric capacity C4 and switch
One end of S2 connects altogether；
The switch other end of S2, the grid of the positive pole of electric capacity C5 and NMOS tube Q16 connect altogether, the drain electrode of NMOS tube Q16 be described in adopt
The outfan of sample holding circuit, the source electrode of the negative pole of electric capacity C4, the negative pole of electric capacity C5 and NMOS tube Q16 is connected to simulation ground altogether；
In the conducting start time of described on-off circuit, the rising edge receiving described anticipation circuit of described sampling hold circuit
Signal, described controlling of sampling end triggers switch S1 Guan Bi, and now switch S2 disconnects, and the input input of sampling hold circuit is described
Electric current turns the sampled voltage signal of potential circuit output and charges to electric capacity C4；
In 0.5 times of moment of the conducting period of described on-off circuit, described controlling of sampling end triggers switch S1 and disconnects, now electric capacity
C4 storage has the sampled current signals corresponding to described 0.5 times of moment；
Before turning on to described on-off circuit after 0.5 times of moment of the conducting period of described on-off circuit, described holding, is controlled
End processed triggers switch S2 Guan Bi, makes electric capacity C4 charge to electric capacity C5, when the voltage of electric capacity C4 is equal with the voltage of electric capacity C5, and institute
State holding and control end triggering switch S2 disconnection, make electric capacity C5 storage sampled current signals corresponding to described 0.5 times of moment, described
Sampled current signals is through NMOS tube Q16 output extremely described reference current sampled signal amplifying circuit.
4. as claimed in claim 3 without the switching mode lithium battery charging circuit of current sampling resistor, it is characterised in that described
Reference current sampled signal amplifying circuit include by the first equivalent current source, NMOS tube Q17, NMOS tube Q18, PMOS Q19 and
The reference current generation unit of PMOS Q20 composition；
It is described that the described input of the first equivalent current source and the source electrode of the source electrode of PMOS Q19 and PMOS Q20 connect composition altogether
The input of reference current sampled signal amplifying circuit, the outfan of described first equivalent current source and the drain electrode of NMOS tube Q17,
The grid of NMOS tube Q17 and the grid of NMOS tube Q18 connect altogether, and the source electrode of NMOS tube Q17 and the source electrode of NMOS tube Q18 are connected to mould altogether
Intend ground；
The grid of PMOS Q19, the grid of PMOS Q20, the drain electrode of PMOS Q19 and the drain electrode of NMOS tube Q18 connect altogether, PMOS
The first input end that drain electrode is described reference current sampled signal amplifying circuit of pipe Q20 and outfan；
Described first equivalent current source produces a reference current and flows through PMOS Q20, and this reference current and described sampling keep
The sampled current signals of circuit output forms error voltage defeated by equivalent resistance between PMOS Q20 and NMOS tube Q16
Go out to described constant current constant voltage switching circuit.
5. as claimed in claim 1 without the switching mode lithium battery charging circuit of current sampling resistor, it is characterised in that described
Reference current sampled signal amplifying circuit includes error amplifier and reference voltage generation unit；Described reference voltage generation unit
Including the second equivalent current source, NMOS tube Q21, NMOS tube Q22, resistance R9 and resistance R10；
The positive input of described error amplifier connects composition described reference current sampled signal amplification altogether with one end of resistance R9
The first input end of circuit, the reverse input end of described error amplifier is total to one end of resistance R10 and the drain electrode of NMOS tube Q21
Connecing, the outfan of described error amplifier is the outfan of described reference current sampled signal amplifying circuit；
The input of described second equivalent current source connects the described base of composition altogether with the other end of the other end of resistance R9 and resistance R10
Second input of quasi-current sampling signal amplifying circuit, the outfan of described second equivalent current source and the leakage of NMOS tube Q21
The grid of pole, the grid of NMOS tube Q21 and NMOS tube Q22 connects altogether, and the source electrode of NMOS tube Q21 and the source electrode of NMOS tube Q22 connect altogether
In simulation ground；
Described second equivalent current source produces a reference current and flows through resistance R10, makes to produce reference voltage output on resistance R10
To the reverse input end of described error amplifier, the sampled current signals of described sampling hold circuit output is changed through resistance R9
Becoming voltage signal, the difference between described voltage signal and described reference voltage is amplified by described error amplifier, thus
Produce error voltage and export to described constant current constant voltage switching circuit.
6. the switching mode lithium battery charging circuit without current sampling resistor as described in any one of claim 1 or 4 or 5, its
Being characterised by, described electric current turns potential circuit and includes NMOS tube Q23, and the drain electrode of NMOS tube Q23 constitutes described after being connected with grid
Electric current turns input and the outfan of potential circuit, and the source electrode of NMOS tube Q23 connects simulation ground；
The drain electrode of NMOS tube Q23 inputs described sampled current signals and is converted to sampled voltage signal by the output of its grid to institute
State sampling hold circuit.
7. as claimed in claim 1 without the switching mode lithium battery charging circuit of current sampling resistor, it is characterised in that described
On-off circuit includes PMOS Q24 and diode D1；
The grid of PMOS Q24 is the controlled end of described on-off circuit, the input that drain electrode is described on-off circuit of PMOS Q24
End, the source electrode of PMOS Q24 connects the outfan constituting described on-off circuit, the positive pole of diode D1 altogether with the negative pole of diode D1
Ground connection.
8. as claimed in claim 7 without the switching mode lithium battery charging circuit of current sampling resistor, it is characterised in that described
On-off circuit also includes NMOS tube Q25；
The grid of NMOS tube Q25 is another controlled end of described on-off circuit, and the drain electrode of NMOS tube Q25 connects described PMOS
The source electrode of Q24, the source ground of NMOS tube Q25.
9. as claimed in claim 1 without the switching mode lithium battery charging circuit of current sampling resistor, it is characterised in that described
Switching mode lithium battery charging circuit also includes resistance R11, resistance R12 and electric capacity C6；
One end of resistance R11, the positive pole of electric capacity C6, the other end of inductance L are connected to the positive pole of lithium battery altogether, another of resistance R11
End, one end of resistance R12 connect altogether with the second input of described reference voltage sampled signal amplifying circuit, another of resistance R12
The negative pole of end, the negative pole of electric capacity C6 and lithium battery is connected to ground altogether.
10. the switching mode lithium cell charging chip without current sampling resistor, it is characterised in that described switching mode lithium battery
Charging chip includes the switching mode lithium battery charging circuit as described in any one of claim 1～9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620543140.8U CN205791682U (en) | 2016-06-03 | 2016-06-03 | A kind of switching mode lithium battery charging circuit without current sampling resistor and chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620543140.8U CN205791682U (en) | 2016-06-03 | 2016-06-03 | A kind of switching mode lithium battery charging circuit without current sampling resistor and chip |
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| CN205791682U true CN205791682U (en) | 2016-12-07 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108808777A (en) * | 2018-06-15 | 2018-11-13 | 西安微电子技术研究所 | The charging circuit that one mode independently switches |
| CN112865251A (en) * | 2021-02-26 | 2021-05-28 | 钰泰半导体南通有限公司 | High-voltage charging management chip based on power consumption |
-
2016
- 2016-06-03 CN CN201620543140.8U patent/CN205791682U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108808777A (en) * | 2018-06-15 | 2018-11-13 | 西安微电子技术研究所 | The charging circuit that one mode independently switches |
| CN112865251A (en) * | 2021-02-26 | 2021-05-28 | 钰泰半导体南通有限公司 | High-voltage charging management chip based on power consumption |
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Address after: 518000 1701, building 1, Shenzhen new generation industrial park, 136 Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen City, Guangdong Province Patentee after: Fuman microelectronics Group Co.,Ltd. Address before: Unit b7-b8, 9 / F, Yanxiang science and technology building, 31 Gaoxin Zhongsi Road, Nanshan District, Shenzhen, Guangdong 518000 Patentee before: SHENZHEN FUMAN ELECTRONIC GROUP Co.,Ltd. |