CN205647561U - PBUS does not have transformer etherCAT communication circuit - Google Patents

Abstract

The utility model discloses a PBUS does not have transformer etherCAT communication circuit, including first ethernet PHY driver chip, second ethernet PHY driver chip, an impedance matching network, the 2nd impedance matching network, the 3rd impedance matching network, fourth impedance matching network, insert parallel connection's an impedance matching network and the 2nd impedance matching network and parallel connection's the 3rd impedance matching network and fourth impedance matching network between first ethernet PHY driver chip and the second ethernet PHY driver chip, the utility model discloses the structure principle is simple, can avoid the waste of unnecessary network transformer, network connector and ethernet cable, can further reduce the required face that accounts for of implementation that uses the etherCAT technique and amass.

Description

PBUS transless EtherCAT telecommunication circuit

Technical field

This utility model relates to industry real-time ethernet technical field of automatic control, specially PBUS without becoming Depressor EtherCAT telecommunication circuit.

Background technology

In typical EtherCAT, Ethernet interface transformator is an important devices, is favorably improved system Barrier propterty, EMI performance signal quality, transmission range are had the biggest contribution.But network transformation Body is long-pending relatively big, and the PCB surface that can increase each slave station module of EtherCAT is amassed, and the most also increases veneer and becomes This.

EtherCAT industrial Ethernet technology is particularly suitable for modularity, Distributed Design.System is needed The function wanted is split as the module that each is independent, it is simple to the system integration and flexible configuration.Between modules Communicated by EtherCAT bus.This also implies that at EtherCAT EPA composition Control system can need network transformer, RJ45 adapter and netting twine in a large number.This most singly makes PCB surface Long-pending excessive, also make regulator cubicle space waste, cable cost increases.

The short haul connection of of this sort intermodule, general distance no more than 500mm.It is not required to the longest Transmission range and outstanding long range propagation protective capacities.It is desirable that one to account for plate area little, compact The communication connection mode of type.For this Germany's times good fortune utility model communication technology of EBUS, by 100M with Too net uses LVDS technology to be transmitted, and carries out impedance matching with the middle resistance break of 100 Ω, without unnecessary Peripheral circuit and device.But EBUS is only at ASIC:ET1100 and ET1200 of Germany times good fortune oneself In supported.The most increasing chip manufacturer starts to release the EtherCAT slave station of oneself and controls core Sheet, singly all relies on PHY, Ethernet transformator and the traditional mode of RJ45 adapter.Geng You manufacturer opens Begin to be integrated in inside ASIC by PHY chip, amass size reducing the PCB surface of user.Although also carrying Go out the back-to-back communication mode between PHY and PHY, however it is necessary that the holding wire of up to more than 10.Lead The size causing adapter is the most excessive.

In view of the foregoing, this utility model is transformed in this level of PHY chip, it is to avoid EBUS's is special Attribute, and the problem that the holding wire that transmits back-to-back of PHY chip is too much.

Utility model content

The purpose of this utility model is to provide PBUS transless EtherCAT telecommunication circuit, to solve The problem proposed in above-mentioned background technology.

For achieving the above object, the following technical scheme of this utility model offer: PBUS transless EtherCAT Telecommunication circuit, including the first ethernet PHY driving chip, the second ethernet PHY driving chip, first Impedance matching network, the second impedance matching network, the 3rd impedance matching network and the 4th impedance matching network, Parallel connection is accessed between described first ethernet PHY driving chip and described second ethernet PHY driving chip The first impedance matching network connected and the second impedance matching network and the 3rd impedance matching that is connected in parallel Network and the 4th impedance matching network, described first impedance matching network includes resistance A, the electricity being connected in series Resistance B, the intermediate node at resistance A and resistance B passes through electric capacity A ground connection, the intermediate node of resistance A and resistance B And indirect 2.5V power supply between electric capacity A；Described second impedance matching network includes the resistance being connected in series C, resistance D, in the intermediate node of resistance C and resistance D by electric capacity B ground connection, resistance C and resistance D it Indirect 2.5V power supply between intermediate node and electric capacity B；Described 3rd impedance matching network includes being connected in series Resistance E, resistance F, in the intermediate node of resistance E and resistance F by electric capacity C ground connection, resistance E and electricity Indirect 2.5V power supply between intermediate node and the electric capacity C of resistance F；Described 4th impedance matching network includes string Resistance G, the resistance H that connection connects, the intermediate node at resistance G and resistance H passes through electric capacity D ground connection, resistance Indirect 2.5V power supply between G and the intermediate node of resistance H and electric capacity D.

Preferably, described first ethernet PHY driving chip TX+ end connects resistance L one end, resistance respectively A one end, electric capacity E one end, the electric capacity E other end connects resistance C one end, resistance M one end and respectively Two ethernet PHY driving chip TX+ ends；Described first ethernet PHY driving chip TX-end connects respectively Resistance K one end, resistance B one end, electric capacity F one end, the electric capacity F other end connect respectively resistance D one end, Resistance O one end and the second ethernet PHY driving chip TX-end；Described first ethernet PHY drives core Sheet RX+ end connects resistance J one end, resistance E one end, electric capacity G one end respectively, and the electric capacity G other end is respectively Connect resistance G one end, resistance N one end and the second ethernet PHY driving chip RX+ end；Described second Ethernet PHY driving chip RX-end connects resistance I one end, resistance F one end, electric capacity H one end respectively, The electric capacity H other end connects resistance F one end, resistance P one end and the second ethernet PHY respectively and drives core Sheet RX-end.

Preferably, the resistance A in described first impedance matching network, resistance B resistance value are 49.9 Europe Nurse, electric capacity A capacitance is 0.1 microfarad；Resistance C, resistance D electricity in described second impedance matching network Resistance is 49.9 ohm, and electric capacity B capacitance is 0.1 microfarad；In described 3rd impedance matching network Resistance E, resistance F resistance value are 49.9 ohm, and electric capacity C capacitance is 0.1 microfarad；Described 4th Resistance G, resistance H resistance value in impedance matching network are 49.9 ohm, and electric capacity D capacitance is 0.1 Microfarad.

Compared with prior art, the beneficial effects of the utility model are: this utility model structural principle is simple, It can be avoided that unnecessary network transformer, network connector and the waste of Ethernet cable, it is possible to further Account for plate area required for reducing the enforcement using EtherCAT technology, be practical new to Germany times good fortune simultaneously The EBUS of type carries out a kind of brand-new replacement, reduces its monopoly；Can also realize: without transformation simultaneously Device transmission, support 100BASE-TX, support full-duplex data transmission, support reticule self adaptation, support 1 meter of inner panel level cabling transmission.

Accompanying drawing explanation

Fig. 1 is overall structure schematic diagram of the present utility model.

Detailed description of the invention

Below in conjunction with the accompanying drawing in this utility model embodiment, to the technology in this utility model embodiment Scheme is clearly and completely described, it is clear that described embodiment is only this utility model one Divide embodiment rather than whole embodiments.Based on the embodiment in this utility model, this area is common The every other embodiment that technical staff is obtained under not making creative work premise, broadly falls into this The scope of utility model protection.

Referring to Fig. 1, this utility model provides a kind of technical scheme: PBUS transless EtherCAT leads to Letter circuit, including first ethernet PHY driving chip the 1, second ethernet PHY driving chip 2, first Impedance matching network the 3, second impedance matching network the 4, the 3rd impedance matching network 5 and the 4th impedance matching Network 6, described first ethernet PHY driving chip 1 and described second ethernet PHY driving chip 2 it Between access the first impedance matching network 3 and the second impedance matching network 4 being connected in parallel and be connected in parallel The 3rd impedance matching network 5 and the 4th impedance matching network 6, described first impedance matching network 3 includes Resistance A 1a, the resistance B 2a being connected in series, the intermediate node at resistance A 1a and resistance B 2a passes through electricity Hold A 1b ground connection, between resistance A 1a and the intermediate node of resistance B 2a and electric capacity A 1b in indirect 2.5V Power supply；Described second impedance matching network 4 includes resistance C 3a, the resistance D 4a being connected in series, at electricity The intermediate node of resistance C 3a and resistance D 4a by electric capacity B 2b ground connection, resistance C 3a and resistance D 4a it Indirect 2.5V power supply between intermediate node and electric capacity B 2b；Described 3rd impedance matching network 5 includes string Resistance E 5a, the resistance F 6a that connection connects, the intermediate node at resistance E 5a Yu resistance F 6a passes through electric capacity C 3b ground connection, between resistance E 5a and the intermediate node of resistance F 6a and electric capacity C 3b in indirect 2.5V electricity Source；Described 4th impedance matching network 6 includes resistance G 7a, the resistance H 8a being connected in series, at resistance The intermediate node of G 7a and resistance H 8a is by electric capacity D 4b ground connection, between resistance G 7a and resistance H 8a Indirect 2.5V power supply between node and electric capacity D 4b.Ethernet is a kind of LAN networking skill Art, is the most general communication protocol standard of current existing LAN employing.The standards define at local The type of cable used in net and signal processing method.Ethernet between InterWorking Equipment with 10～100Mbps Speed transmit information bag, twisted-pair cable 10Base T Ethernet is due to its low cost, high reliability And the ethernet technology that the speed of 10Mbps and becoming is most widely used；Physical layer defines data and passes Send and receive required electricity and optical signal, line status, clock reference, data encoding and circuit etc., And provide standard interface to data link layer device.The chip of physical layer is referred to as PHY, and data link layer is then Addressing mechanism, the structure of Frame, data error inspection are provided, transmit control, to Internet offer mark The functions such as accurate data-interface.

First ethernet PHY driving chip 1TX+ end connects resistance L 12a one end, resistance A 1a respectively One end, electric capacity E 5b one end, the electric capacity E 5b other end connects resistance C 3a one end, resistance M 13a respectively One end and the second ethernet PHY driving chip 2TX+ end；Described first ethernet PHY driving chip 1 TX-end connects resistance K 11a one end, resistance B 2a one end, electric capacity F 6b one end, electric capacity F 6b respectively The other end connects resistance D 4a one end, resistance O 15a one end and the second ethernet PHY respectively and drives core Sheet 2TX-end；Described first ethernet PHY driving chip 1RX+ end connect respectively resistance J 10a one end, Resistance E 5a one end, electric capacity G 7b one end, the electric capacity G 7b other end connect respectively resistance G 7a one end, Resistance N 14a one end and the second ethernet PHY driving chip 2RX+ end；Described second ethernet PHY Driving chip 2RX-end connects resistance I 9a one end, resistance F 6a one end, electric capacity H 8b one end respectively, The electric capacity H 8b other end connects resistance F 6a one end, resistance P 16a one end and the second Ethernet respectively PHY driving chip 2RX-end.

It addition, in the present embodiment, the resistance A 1a in the first impedance matching network 3, resistance B 2a resistance Value is 49.9 ohm, and electric capacity A 1b capacitance is 0.1 microfarad；Described second impedance matching network 4 In resistance C 3a, resistance D 4a resistance value be 49.9 ohm, electric capacity B 2b capacitance is 0.1 micro- Method；Resistance E 5a, resistance F 6a resistance value in described 3rd impedance matching network 5 are 49.9 Europe Nurse, electric capacity C 3b capacitance is 0.1 microfarad；Resistance G 7a in described 4th impedance matching network 6, Resistance H 8a resistance value is 49.9 ohm, and electric capacity D 4b capacitance is 0.1 microfarad, utilize electric capacity " every Straight-through hand over " characteristic substitute transformator, it is achieved the transmission of electric capacity both sides AC signal.

Embodiment:

Application process of the present utility model is mainly:

A, PBUS communication PBUS special connector connected between two boards card, and intermodule distance 20mm, PBUS track lengths is less than 80mm, and testing result is: EtherCAT slave station can be with main website proper communication； Can proper communication between EtherCAT slave station；Do not find to communicate different by the detection of EtherCAT diagnostic software Often through 48 hours follow-on tests, no abnormal.

B, PBUS communication cat5e netting twine connected between two boards card, and intermodule distance 1500mm, inspection Survey result is: can proper communication between EtherCAT slave station；Detected not by EtherCAT diagnostic software Discovery communication abnormality was through 48 hours follow-on tests, no abnormal.

This utility model structural principle is simple, it is possible to avoid unnecessary network transformer, network connector with The waste of Ethernet cable, it is possible to account for plate required for reducing further the enforcement using EtherCAT technology Area, is that the EBUS to Germany times good fortune utility model carries out a kind of brand-new replacement simultaneously, reduces it special Sexual；Can also realize: transless transmission, support 100BASE-TX, support full-duplex data simultaneously Transmission, support reticule self adaptation, 1 meter of inner panel level cabling transmission of support.

Embodiment the most of the present utility model, for the ordinary skill people of this area For Yuan, it is possible to understand that can be real to these in the case of without departing from principle of the present utility model and spirit Executing example to carry out multiple change, revise, replace and modification, scope of the present utility model is by claims And equivalent limits.

Claims (3)

1.PBUS transless EtherCAT telecommunication circuit, including the first ethernet PHY driving chip, Second ethernet PHY driving chip, the first impedance matching network, the second impedance matching network, the 3rd resistance Anti-matching network and the 4th impedance matching network, it is characterised in that: described first ethernet PHY drives core Access between sheet and described second ethernet PHY driving chip the first impedance matching network of being connected in parallel and Second impedance matching network and the 3rd impedance matching network being connected in parallel and the 4th impedance matching network, Described first impedance matching network includes resistance A, the resistance B being connected in series, resistance A and resistance B it Intermediate node passes through electric capacity A ground connection, between resistance A and the intermediate node of resistance B and electric capacity A in indirect 2.5V Power supply；Described second impedance matching network includes resistance C, the resistance D being connected in series, at resistance C and electricity The intermediate node of resistance D is by electric capacity B ground connection, middle between resistance C and the intermediate node of resistance D and electric capacity B Connect 2.5V power supply；Described 3rd impedance matching network includes resistance E, the resistance F being connected in series, at electricity The intermediate node of resistance E and resistance F is by electric capacity C ground connection, the intermediate node of resistance E and resistance F and electric capacity C Indirect 2.5V power supply between；Described 4th impedance matching network includes resistance G, the resistance being connected in series H, in the intermediate node of resistance G and resistance H by electric capacity D ground connection, the intermediate node of resistance G and resistance H with Indirect 2.5V power supply between electric capacity D.

PBUS transless EtherCAT telecommunication circuit the most according to claim 1, its feature exists In: described first ethernet PHY driving chip TX+ end connect respectively resistance L one end, resistance A one end, Electric capacity E one end, the electric capacity E other end connects resistance C one end, resistance M one end and the second ether respectively Net PHY driving chip TX+ end；Described first ethernet PHY driving chip TX-end connects resistance K respectively One end, resistance B one end, electric capacity F one end, the electric capacity F other end connects resistance D one end, resistance O respectively One end and the second ethernet PHY driving chip TX-end；Described first ethernet PHY driving chip RX+ End connects resistance J one end, resistance E one end, electric capacity G one end respectively, and the electric capacity G other end connects respectively Resistance G one end, resistance N one end and the second ethernet PHY driving chip RX+ end；Described second ether Net PHY driving chip RX-end connects resistance I one end, resistance F one end, electric capacity H one end, electric capacity respectively The H other end connects resistance F one end, resistance P one end and the second ethernet PHY driving chip RX-respectively End.

PBUS transless EtherCAT telecommunication circuit the most according to claim 1, its feature exists In: resistance A, resistance B resistance value in described first impedance matching network are 49.9 ohm, electric capacity A capacitance is 0.1 microfarad；Resistance C, resistance D resistance value in described second impedance matching network are 49.9 ohm, electric capacity B capacitance is 0.1 microfarad；Resistance E in described 3rd impedance matching network, Resistance F resistance value is 49.9 ohm, and electric capacity C capacitance is 0.1 microfarad；Described 4th impedance matching Resistance G, resistance H resistance value in network are 49.9 ohm, and electric capacity D capacitance is 0.1 microfarad.