CN205644863U - Antitheft detection appearance - Google Patents
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- CN205644863U CN205644863U CN201620225220.9U CN201620225220U CN205644863U CN 205644863 U CN205644863 U CN 205644863U CN 201620225220 U CN201620225220 U CN 201620225220U CN 205644863 U CN205644863 U CN 205644863U
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Abstract
The utility model discloses an antitheft detection appearance, antitheft detection appearance includes power, sensing unit, amplifying unit, comparing element, opposition unit, memory cell, control gate unit, oscillating unit, counting unit, the settlement of pulse quantity unit, the control unit and output unit. Antitheft detection appearance can be promptly and accurately detection invasion and location invasion position, have sensitivity height, characteristics that job stabilization is reliable, simultaneously, be applied to theftproof detection system with it, can realize through a public signal line in with the system alarm signal of all detectors send the host computer to, simplified circuit structure greatly, reduced the work load of installation, maintenance.
Description
Technical field
This utility model relates to electronic circuit technology field, particularly relates to a kind of antitheft detector.
Background technology
Along with the improving constantly of living standard since China's reform, the requirement of the person and property safety is improved by people the most day by day, and antitheft detection system is increasingly widely applied as the critical facility of the thunder boltes such as pre-rob-proof, theft.The antitheft detection system currently commonly used is deployed troops on garrison duty some antitheft detectors in monitored area, it is possible to detection occurs the intrusion behavior in monitored area, sends alarm when there is invasion to main frame, and is locked into invasion and puts.But it is required to a holding wire between the traditional each detector of antitheft detection system and main frame, it is used for transmitting the alarm signal of each detector position, the holding wire being connected with main frame when detector quantity is more the most just accordingly increases, it is probably tens the most hundreds of, not only installation inconvenience, and too increase cost, and bring difficulty to regular maintenance.
Utility model content
For above-mentioned technical problem, the purpose of this utility model is to provide a kind of antitheft detector, described antitheft detector is applied to antitheft detection system, it is capable of sending the alarm signal of detectors all in system to main frame by a public holding wire, enormously simplify circuit structure, reducing installation, the workload safeguarded, this antitheft detector has feature highly sensitive, stable and reliable in work simultaneously.
For reaching this purpose, this utility model by the following technical solutions:
A kind of antitheft detector, including: power supply, sensing unit, amplifying unit, comparing unit, rp unit, memory element, control gate cell, oscillating unit, counting unit, number of pulses setup unit, control unit and output unit；
Described power supply is for powering to whole antitheft detector；
Described sensing unit electrically connects with amplifying unit, for detecting whether there is human body process, and sensor signal is exported amplifying unit；
Described amplifying unit electrically connects with comparing unit, and after being amplified sensor signal, output is to comparing unit；
Described comparing unit electrically connects with rp unit, is used for comparing sensor signal voltage numerical value and reference voltage numerical value, sends alarm signal according to comparative result, and comparative result is exported rp unit；
Described rp unit electrically connects with memory element, is used for making memory element anti-phase；
Described memory element electrically connects with controlling gate cell, for the alarm signal keeping sensor to export, and triggers control gate cell conducting when sensor output alarm signal；
Described control gate cell electrically connects with oscillating unit, counting unit, output unit, for the oscillator signal that oscillating unit produces being sent to counting unit and output unit when sensor output alarm signal；
Described oscillating unit electrically connects with control unit, is used for producing oscillator signal；
Described counting unit electrically connects with number of pulses setup unit, for counting the number of pulses of oscillator signal；
Described number of pulses setup unit electrically connects with control unit, the number of pulses in setting oscillator signal each cycle that oscillating unit produces, thus arranges respective markers for antitheft detector；
Described control unit electrically connects with oscillating unit, for when the number of pulses that oscillating unit produces reaches the numerical value that number of pulses setup unit sets, controls oscillating unit and stops oscillation, and counting unit resetted；
The external main frame of described output unit, identifies, according to the different of the number of pulses received, the sensor occurring to report to the police to external main frame, main frame for the pulsing produced by oscillating unit when sensor output alarm signal.
Especially, described amplifying unit includes that the second audion and the second operational amplifier, described second transistor base connect sensing unit, grounded emitter, and colelctor electrode connects positive source；The power pins of described second operational amplifier connects power supply, and in-phase input end connects the colelctor electrode of the second audion, reverse inter-input-ing ending grounding, and outfan connects comparing unit.
Especially, described comparing unit includes the 3rd operational amplifier and potentiometer, and described 3rd operational amplifier power pins connects power supply, in-phase input end connects amplifying unit, the movable leg of inverting input connection potentiometer, and outfan connects rp unit；Two fixing feet of described potentiometer connect power supply.
Especially, described memory element includes that the 9th NAND gate, the tenth NAND gate, the 9th electric capacity, the 14th resistance and intervalometer, two inputs of described 9th NAND gate connect rp unit and the outfan of the tenth NAND gate respectively, and outfan connects control gate cell；The first input end of described tenth NAND gate connects the outfan of the 9th NAND gate, and the second input connects DC power anode through the 14th resistance；Described 9th electric capacity and intervalometer are arranged in parallel between the second input and the ground of the tenth NAND gate.
Especially, described control gate cell includes that the first not gate and the second NAND gate, described first not gate input connect the second NAND gate outfan, outfan connection count unit and output unit；Two inputs of described second NAND gate connect memory element and oscillating unit respectively.
Especially, described oscillating unit includes that the 3rd not gate, the 4th NAND gate and the first electric capacity and the first resistance, described 3rd not gate input connect the 4th NAND gate outfan, and outfan connects control gate cell；The first input end of described 4th NAND gate connects control unit, the second input connects the 3rd not gate input through the first resistance, and described first electric capacity is parallel between the 3rd non-gate output terminal and the 4th NAND gate the second input.
Especially, described counting unit includes binary system serial counter, and described binary system serial counter pulse input end connects control gate cell, and clear terminal connects control unit, and pulse output end connects number of pulses setup unit.
Especially, described number of pulses setup unit includes phase inverter, single-pole double-throw switch (SPDT), diode and the second resistance, described phase inverter pulse input end connection count unit, phase inverter every road pulse output end is connected respectively and is connected in parallel to one end of the second resistance after a single-pole double-throw switch (SPDT) and a diode, and the other end of described second resistance connects output unit and control unit；Wherein, in the output of phase inverter every road, the moved end of described single-pole double-throw switch (SPDT) connects the negative electrode of diode, two not moved end connect pulse input end and the pulse output end of phase inverter respectively.
Especially, described control unit includes the first trigger, the second trigger, the second electric capacity, the 3rd electric capacity, the 3rd resistance, the 4th resistance, the 5th not gate, the 6th NAND gate, the 7th not gate, the 8th NAND gate, described first flip-flop data input connects output unit, input end of clock connects number of pulses setup unit, reset terminal is through the second capacity earth, set end ground connection, outfan connects reset terminal through the 3rd resistance, and output end of oppisite phase connects the input end of clock of the second trigger；Described second flip-flop data input connects output unit, input end of clock connects the output end of oppisite phase of the first trigger, and reset terminal is through the 3rd capacity earth, set end ground connection, outfan connects reset terminal through the 4th resistance, and output end of oppisite phase connects a road input of the 8th NAND gate；Described 5th not gate input connects the 6th NAND gate outfan and counting unit respectively, and outfan connects oscillating unit；Two inputs of described 6th NAND gate connect the 7th non-gate output terminal and memory element respectively；The input of described 7th not gate connects the 8th NAND gate outfan；Two inputs of described 8th NAND gate connect the output end of oppisite phase of the first trigger and the second trigger respectively.
Especially, described output unit includes the first audion and the 5th resistance, and the base stage of described first audion connects control gate cell sum counter unit, the external main frame of emitter stage through the 5th resistance, and colelctor electrode connects number of pulses setup unit and control unit.
The antitheft detector that the utility model proposes, when sensing unit has detected that human body is through out-of-date, the amplified unit of sensor signal, comparing unit, rp unit, memory element is amplified, compare with reference value, anti-phase and signal exports after keeping, control gate cell conducting, the pulse that oscillating unit produces is sent to output unit and counting unit by controlling gate cell, counting unit number of pulses amount counts, when count value reaches the quantity of the generation vibration of each cycle that number of pulses setup unit sets, control unit controls oscillating unit and stops oscillation, and counting unit is resetted, the external main frame of output unit, the pulsing produced in each for oscillating unit cycle is to main frame, main frame distinguishes the position of sensor human body process being detected according to the number of pulses received, send alarm, and be locked into invasion and put.Described antitheft detector can be invaded in detection promptly and accurately, and position invasion position, there is feature highly sensitive, stable and reliable in work, simultaneously, it is applied to antitheft detection system, it is capable of sending the alarm signal of detectors all in system to main frame by a public holding wire, enormously simplify circuit structure, reduce installation, the workload safeguarded.
Accompanying drawing explanation
Fig. 1 is the antitheft detector electrical block diagram that this utility model embodiment provides.
Fig. 2 is the antitheft detector circuit theory diagrams that this utility model embodiment provides.
Detailed description of the invention
The utility model is described in further detail with embodiment below in conjunction with the accompanying drawings.It is understood that specific embodiment described herein is used only for explaining this utility model, rather than to restriction of the present utility model.It also should be noted that, for the ease of describing, accompanying drawing illustrate only the part relevant to this utility model rather than full content, unless otherwise defined, all of technology used herein and scientific terminology are identical with belonging to the implication that those skilled in the art of the present utility model are generally understood that.It is intended merely to describe the purpose of specific embodiment at term used in the description of the present utility model herein, it is not intended that in limiting this utility model.Term as used herein " and/or " include the arbitrary and all of combination of one or more relevant Listed Items.
Embodiment one
Refer to shown in Fig. 1, the electrical block diagram of the antitheft detector that Fig. 1 provides for this utility model embodiment.
In the present embodiment, antitheft detector includes power supply 101, sensing unit 102, amplifying unit 103, comparing unit 104, rp unit 105, memory element 106, controls gate cell 107, oscillating unit 108, counting unit 109, number of pulses setup unit 110, control unit 111 and output unit 112.
Described power supply 101, for powering to whole antitheft detector, specifically includes；Transformator T1, rectifier bridge VC1, manostat V1, the tenth electric capacity C10, the 11st electric capacity C11, the 12nd electric capacity C12, the 13rd electric capacity C13.Wherein, transformator T1 input connects external power source, outfan connects the AC of rectifier bridge VC1, the DC side anode of rectifier bridge VC1 connects the input of manostat V1, positive DC side end ground connection, the outfan of manostat V1 connects other circuit of antitheft detector, common end grounding, tenth electric capacity C10 and the 11st electric capacity C11 is connected in parallel between input and the ground of manostat V1, and the 12nd electric capacity C12 and the 13rd electric capacity C13 is connected in parallel between outfan and the ground of manostat V1.
Described sensing unit 102 electrically connects with amplifying unit 103, for detecting whether there is human body process, and sensor signal exports amplifying unit 103, specifically includes: sensor IC 1 and the 6th resistance R6.Wherein, the power end of sensor IC 1 connects DC source, and signal end connects amplifying unit 103 and the 6th resistance R6, the other end ground connection of the 6th resistance R6.Sensor IC 1 described in the present embodiment uses pyroelectric infrared sensor, concrete model to be P2288, is a kind of only infrared ray responsive semiconductor device to human body radiation, when there being human body through out-of-date output low frequency signal before sensor.
Described amplifying unit 103 electrically connects with comparing unit 104, after being amplified sensor signal, output is to comparing unit 104, specifically include the second audion Q2 and the second operational amplifier IC2, the base stage of described second audion Q2 connects the signal end of sensor IC 1, grounded emitter, colelctor electrode connects positive source；The power pins of described second operational amplifier IC2 connects power supply, and in-phase input end connects the colelctor electrode of the second audion Q2, reverse inter-input-ing ending grounding, and outfan connects comparing unit 104.
Described comparing unit 104 electrically connects with rp unit 105, for comparing sensor signal voltage numerical value and reference voltage numerical value, alarm signal is sent according to comparative result, and comparative result is exported rp unit 105, specifically include: the 3rd operational amplifier IC3 and potentiometer W1, described 3rd operational amplifier IC3 power pins connects power supply, in-phase input end connects the outfan of the second operational amplifier IC2, the movable leg of inverting input connection potentiometer W1, and outfan connects rp unit 105；Two fixing feet of described potentiometer W1 connect power supply.
Described rp unit 105 electrically connects with memory element 106, for making memory element 106 anti-phase, the concrete base stage using the 3rd audion Q3, described 3rd audion Q3 connects the outfan of the 3rd operational amplifier IC3, grounded emitter, colelctor electrode connects memory element 106.
Described memory element 106 electrically connects with controlling gate cell 107, for the alarm signal keeping sensor to export, and triggering control gate cell 107 turns on when sensor output alarm signal, specifically include the 9th NAND gate G9 and the tenth NAND gate G10, two inputs of described 9th NAND gate G9 connect base stage and the outfan of the tenth NAND gate G10 of the 3rd audion Q3 respectively, and outfan connects control gate cell 107；Two inputs of described tenth NAND gate G10 connect emitter stage and the outfan of the 9th NAND gate G9 of the 3rd audion Q3 respectively.
Described memory element 106 electrically connects with controlling gate cell 107, for the alarm signal keeping sensor to export, and triggering control gate cell 107 turns on when sensor output alarm signal, specifically include the 9th NAND gate G9, the tenth NAND gate G10, the 9th electric capacity C9, the 14th resistance R14 and intervalometer AN, two inputs of described 9th NAND gate G9 connect base stage and the outfan of the tenth NAND gate G10 of the 3rd audion Q3 respectively, and outfan connects control gate cell 107；The first input end of described tenth NAND gate G10 connects the outfan of the 9th NAND gate G9, and the second input connects DC power anode through the 14th resistance R14；Described 9th electric capacity C9 and intervalometer AN is arranged in parallel between the second input and the ground of the tenth NAND gate G10.
Described control gate cell 107 electrically connects with oscillating unit 108, counting unit 109, output unit 112, for the oscillator signal that oscillating unit 108 produces being sent to when sensor output alarm signal counting unit 109 and output unit 112, specifically include the first not gate G1 and the second NAND gate G2, described first not gate G1 input connects the second NAND gate G2 outfan, outfan connection count unit 109 and output unit 112；Two inputs of described second NAND gate connect outfan and the oscillating unit 108 of the 9th NAND gate G9 respectively.
Described oscillating unit 108 electrically connects with control unit 111, for producing oscillator signal, specifically include: the 3rd not gate G3, the 4th NAND gate G4 and the first electric capacity C1 and the first resistance R1, described 3rd not gate G3 input connects the 4th NAND gate G4 outfan, and outfan connects the input of the second NAND gate G2；The first input end of described 4th NAND gate G4 connects control unit 111, and the second input connects the 3rd not gate G3 input through the first resistance R1, and described first electric capacity C1 is parallel between the 3rd not gate G3 outfan and the 4th NAND gate G4 the second input.
Described counting unit 109 electrically connects with number of pulses setup unit 110, for the number of pulses of oscillator signal is counted, concrete employing binary system serial counter C1, the pulse input end of described binary system serial counter C1 connects the outfan of the first not gate G1, clear terminal connects control unit 111, and pulse output end connects number of pulses setup unit 110.
nullDescribed number of pulses setup unit 110 electrically connects with control unit 111，Number of pulses in setting each cycle that oscillating unit 108 produces，Thus respective markers is set for antitheft detector，Specifically include: phase inverter P1，First to the 6th single-pole double-throw switch (SPDT) K1、K2、K3、K4、K5、K6，First to the 6th diode D1、D2、D3、D4、D5、D6 and the second resistance R2，The pulse input end of described phase inverter P1 connects the pulse output end of binary system serial counter C1，First pulse output end of phase inverter P1 is connected and is connected in parallel to one end of the second resistance R2 after the first single-pole double-throw switch (SPDT) K1 and the first diode，By that analogy，Until being connected in parallel to one end of the second resistance R2 after the 6th pulse output end series connection the 6th single-pole double-throw switch (SPDT) K6 and the 6th diode D6 of phase inverter P1，The other end of described second resistance R2 connects output unit 112 and control unit 111；Wherein, in the output of phase inverter P1 every road, the moved end of described single-pole double-throw switch (SPDT) connects the negative electrode of diode, two not moved end connect pulse input end and the pulse output end of phase inverter P1 respectively.
nullThe described list 111 yuan that controls electrically connects with oscillating unit 108，For when the number of pulses that oscillating unit 108 produces reaches the numerical value that number of pulses setup unit sets，Control oscillating unit 108 to stop oscillation，And counting unit 109 is resetted，Specifically include the first trigger F1、Second trigger F2、Second electric capacity C2、3rd electric capacity C3、3rd resistance R3、4th resistance R4、5th not gate G5、6th NAND gate G6、7th not gate G7、8th NAND gate G8，Described first trigger F1 data input pin connects output unit 112，Input end of clock connects six diode D1、D2、D3、D4、D5、The common port of the positive pole of D6，Reset terminal is through the second electric capacity C2 ground connection，Set end ground connection，Outfan connects reset terminal through the 3rd resistance R3，Output end of oppisite phase connects the input end of clock of the second trigger F2；The data input pin of described second trigger F2 connects output unit 112, input end of clock connects the output end of oppisite phase of the first trigger F1, reset terminal is through the 3rd electric capacity C3 ground connection, set end ground connection, outfan connects reset terminal through the 4th resistance R4, and output end of oppisite phase connects a road input of the 8th NAND gate G8；The input of described 5th not gate G5 connects outfan and the clear terminal of binary system serial counter C1 of the 6th NAND gate G6 respectively, and outfan connects the second input of the 4th NAND gate G4；Two inputs of described 6th NAND gate G6 connect outfan and second input of the tenth NAND gate G10 of the 7th not gate G7 respectively；The input of described 7th not gate G7 connects the 8th NAND gate G8 outfan；Two inputs of described 8th NAND gate G connect the first trigger F1 and the output end of oppisite phase of the second trigger F2 respectively.
The described external main frame of output unit 112, for the pulsing that oscillating unit 108 produced when sensor output alarm signal to external main frame, main frame identifies, according to the different of the number of pulses received, the sensor occurring to report to the police, and specifically includes the first audion Q1 and the 5th resistance R5.Wherein, the base stage of the first audion Q1 connects outfan and the pulse input end of binary system serial counter C1 of the first not gate G1 through the 5th resistance R5, the external main frame of emitter stage, colelctor electrode connects the data input pin of the first trigger F1, the data input pin of the second trigger F2 and the common port of the positive pole through second resistance R2 connection six diodes D1, D2, D3, D4, D5, D6 respectively.
In the present embodiment, antitheft detector operation principle is: transformator T1, rectifier bridge VC1, manostat V1, the tenth electric capacity C10, the 11st electric capacity C11, the 12nd electric capacity C12, the 13rd electric capacity C13 form power subsystem, external AC power supply is converted into DC source and powers to whole antitheft detector circuit.Power on circuitry is started working, sensor IC 1 exports faint low frequency signal, the in-phase input end of the 3rd operational amplifier IC3 is added to, compared with the voltage of the inverting input of the 3rd operational amplifier IC3 after the direct current amplifier amplification that the second audion Q2, the second operational amplifier IC2 are constituted.The voltage of the inverting input of described IC3 is determined by potentiometer W1, the suitably resistance of regulator potentiometer W1, when sensor IC 1 has been not detected by human body through out-of-date, when making the in-phase input end voltage of IC3 less than anti-phase input terminal voltage, the 3rd operational amplifier IC3 output low level；When sensor IC 1 has detected that human body, through out-of-date, makes the in-phase input end voltage of IC3 export high level higher than anti-phase input terminal voltage, the 3rd operational amplifier IC3.When sensor IC 1 has detected that human body is through out-of-date, 3rd operational amplifier IC3 exports high level, output low level after the 3rd audion Q3 is anti-phase, the input of the basic RS filpflop that this low level acts on the 9th NAND gate G9, the tenth NAND gate G10 composition makes it overturn, then the 9th NAND gate G9 output high level.Hereafter, when sensor IC 1 detects that the alarm signal of human body process disappears, and the state of trigger also will not change, thus alarm signal storage is kept.9th electric capacity C9, the 14th resistance R14 and intervalometer AN form the clearing delay circuit that powers on, after powering on, 9th electric capacity C9 is in low level, ensure that rest-set flip-flop will not be triggered upset within the setting time, thus in system electrification following period of time, although operator are without departing from scene, but alarm signal will not be sent.Meanwhile, after powering on, the 9th electric capacity C9 is in low level, and the clear terminal adding to enumerator C1 through the 6th NAND gate G6 makes it reset, and adds to the input of the 4th NAND gate G4 through the 5th NAND gate G5, the 6th NAND gate G6, makes agitator be in failure of oscillation state.During nine NAND gate G9 output high level, the control door that the first not gate G1 and the second NAND gate G2 are constituted is opened, and the rectangular pulse that the agitator of the composition such as the 3rd not gate G3 and the 4th NAND gate G4 produces is sent to enumerator C1 and the first audion Q1 by controlling door.The diode AND gate of first to the 6th diode D1, D2, D3, D4, D5, D6 and the second resistance R2 composition and phase inverter P1, first to the 6th single-pole double-throw switch (SPDT) K1, K2, K3, K4, K5, K6 form number of pulses initialization circuit, phase inverter P1 realizes the complementary operation to enumerator C1 output signal, first to the 6th single-pole double-throw switch (SPDT) K1, K2, K3, K4, K5, K6 determines the reversed-phase output after giving the input hour counter outfan of diode AND gate or the enumerator inverted device P1 of output, when switch is placed in ON position, for counter output；When switch is placed in OFF, for enumerator reversed-phase output.Therefore arranged by first to the 6th single-pole double-throw switch (SPDT) K1, K2, K3, K4, K5, K6 different open, pipe combines, number of pulses can set between 1-63, and the numerical value of setting is as the labelling of this sensor.The pulse that agitator is produced by enumerator C1 counts, different output different for quantity correspondence enumerator C1 and phase inverter P1, when count value reaches the numerical value that number of pulses setup unit sets, the opening of first to the 6th single-pole double-throw switch (SPDT) K1, K2, K3, K4, K5, K6 that the output of enumerator C1 and phase inverter P1 and number of pulses setup unit are preset, pipe combination are corresponding, making diode AND gate input for high level, corresponding output is also high level.This high level signal is sent to control unit 111, makes agitator stop oscillation and is resetted by enumerator C1.nullFirst trigger F1、Second trigger F2、Second electric capacity C2、3rd electric capacity C3、3rd resistance R3、4th resistance R4、5th not gate G5、6th NAND gate G6、7th not gate G7、8th NAND gate G8 composition oscillating circuit，First trigger F1 and the second trigger F2 connects into monostable flipflop，During stable state，Their outfan is low level，When diode AND gate output height allocates，Its rising edge signal makes the first trigger F1 enter temporary stable state，Jump on its outfan as high level，It is adjusted to low level under output end of oppisite phase，The low level signal of this output end of oppisite phase is through the 8th NAND gate G8、7th not gate G7、Adding to enumerator C1 clear terminal after 6th NAND gate G6 is anti-phase makes it reset，Add to the 4th NAND gate G4 after the 5th not gate G5 is anti-phase again makes agitator quit work simultaneously.After the temporary stable state of the first trigger F1 terminates, it is adjusted to low level under its outfan, jump on output end of oppisite phase as high level, trigger the second trigger F2 upset, enter temporary stable state, second trigger F2 outfan output low level makes enumerator C1 still in cleared condition, and agitator is still in the state of quitting work.First trigger F1 and the second trigger F2 is used in combination, and reduces timing element the second electric capacity C2 and the capacity of the 3rd electric capacity C3, it is to avoid use the electrolysis condenser that capacity is easily varied, it is ensured that stablizing of delay time.After the temporary stable state of the second trigger F2 terminates, agitator is resumed work, and above-mentioned work process will repeat, the pulse setting quantity can be produced again, so moving in circles, time delay at set intervals is issued by setting the pulse of quantity, until main frame re-powers after pressing reset or down circuitry.First audion Q1 and the 5th resistance R5 forms output unit, and after being amplified by the pulse signal of the setting quantity that control door output, agitator produces, the emitter stage through the first audion Q1 is sent to main frame.When multiple antitheft detectors form antitheft detection system, the emitter stage of the first audion of each antitheft detector output unit is all connected on public signal transmssion line, during alarm free signal, each first audion is turned off, and antitheft detector is separate for each, do not interfere with each other；When certain antitheft detector has detected that human body, through out-of-date, is sent to main frame after pulse signal amplification that control door is exported by its first audion, agitator generation setting quantity.If there being multiple antitheft detector human body process to be detected, main frame, by the difference according to the duration impulse quantity received, is distinguished the position of the antitheft detector sending alarm, thus is positioned invasion.
It should be noted that in above-described embodiment, the described preferred model of manostat V1 is 7809, the described preferred model of enumerator C1 is CD4040, and the described preferred model of phase inverter P1 is CD4069, and described first trigger F1 and the second preferred model of trigger F2 are CD4013.
It should be noted that, in above-described embodiment, the circuit of described power supply 101, sensing unit 102, amplifying unit 103, comparing unit 104, rp unit 105, memory element 106, control gate cell 107, oscillating unit 108, counting unit 109, number of pulses setup unit 110, control unit 111 and output unit 112 is preferred circuit structure, and other circuit structures being capable of identical function can do equivalent.
By sensing unit, the technical solution of the utility model has detected that human body is through out-of-date, the amplified unit of sensor signal, comparing unit, rp unit, memory element is amplified, compare with reference value, anti-phase and signal exports after keeping, control gate cell conducting, the pulse that oscillating unit produces is sent to output unit and counting unit by controlling gate cell, counting unit number of pulses amount counts, when count value reaches the quantity of the generation vibration of each cycle that number of pulses setup unit sets, control unit controls oscillating unit and stops oscillation, and counting unit is resetted, the external main frame of output unit, the pulsing produced in each for oscillating unit cycle is to main frame, main frame distinguishes the position of sensor human body process being detected according to the number of pulses received, send alarm, and be locked into invasion and put.Invasion position can be invaded and be positioned to described antitheft detector detection promptly and accurately, there is feature highly sensitive, stable and reliable in work, simultaneously, it is applied to antitheft detection system, it is capable of sending the alarm signal of detectors all in system to main frame by a public holding wire, enormously simplify circuit structure, reduce installation, the workload safeguarded.
Note, above are only preferred embodiment of the present utility model and institute's application technology principle.It will be appreciated by those skilled in the art that this utility model is not limited to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute without departing from protection domain of the present utility model.Therefore, although this utility model being described in further detail by above example, but this utility model is not limited only to above example, in the case of conceiving without departing from this utility model, other Equivalent embodiments more can also be included, and scope of the present utility model is determined by scope of the appended claims.
Claims (8)
1. an antitheft detector, it is characterised in that including: power supply, sensing unit, amplifying unit, comparing unit, rp unit, memory element, control gate cell, oscillating unit, counting unit, number of pulses setup unit, control unit and output unit；
Described power supply is for powering to whole antitheft detector；
Described sensing unit electrically connects with amplifying unit, for detecting whether there is human body process, and sensor signal is exported amplifying unit；
Described amplifying unit electrically connects with comparing unit, and after being amplified sensor signal, output is to comparing unit；
Described comparing unit electrically connects with rp unit, is used for comparing sensor signal voltage numerical value and reference voltage numerical value, sends alarm signal according to comparative result, and comparative result is exported rp unit；
Described rp unit electrically connects with memory element, is used for making memory element anti-phase；
Described memory element electrically connects with controlling gate cell, for the alarm signal keeping sensor to export, and control gate cell conducting is triggered when sensor output alarm signal, specifically include the 9th NAND gate, the tenth NAND gate, the 9th electric capacity, the 14th resistance and intervalometer, two inputs of described 9th NAND gate connect rp unit and the outfan of the tenth NAND gate respectively, and outfan connects control gate cell；The first input end of described tenth NAND gate connects the outfan of the 9th NAND gate, and the second input connects DC power anode through the 14th resistance；Described 9th electric capacity and intervalometer are arranged in parallel between the second input and the ground of the tenth NAND gate；
Described control gate cell electrically connects with oscillating unit, counting unit, output unit, for the oscillator signal that oscillating unit produces being sent to counting unit and output unit when sensor output alarm signal；
Described oscillating unit electrically connects with control unit, is used for producing oscillator signal；
Described counting unit electrically connects with number of pulses setup unit, for counting the number of pulses of oscillator signal；
Described number of pulses setup unit electrically connects with control unit, the number of pulses in setting oscillator signal each cycle that oscillating unit produces, thus arranges respective markers for antitheft detector；
Described control unit electrically connects with oscillating unit, for when the number of pulses that oscillating unit produces reaches the numerical value that number of pulses setup unit sets, controls oscillating unit and stops oscillation, and counting unit resetted；
The external main frame of described output unit, identifies, according to the different of the number of pulses received, the sensor occurring to report to the police to external main frame, main frame for the pulsing produced by oscillating unit when sensor output alarm signal.
Antitheft detector the most according to claim 1, it is characterised in that described amplifying unit includes that the second audion and the second operational amplifier, described second transistor base connect sensing unit, grounded emitter, and colelctor electrode connects positive source；The power pins of described second operational amplifier connects power supply, and in-phase input end connects the colelctor electrode of the second audion, reverse inter-input-ing ending grounding, and outfan connects comparing unit.
Antitheft detector the most according to claim 1, it is characterized in that, described comparing unit includes the 3rd operational amplifier and potentiometer, described 3rd operational amplifier power pins connects power supply, in-phase input end connects amplifying unit, the movable leg of inverting input connection potentiometer, and outfan connects rp unit；Two fixing feet of described potentiometer connect power supply.
Antitheft detector the most according to claim 1, it is characterised in that described control gate cell includes that the first not gate and the second NAND gate, described first not gate input connect the second NAND gate outfan, outfan connection count unit and output unit；Two inputs of described second NAND gate connect memory element and oscillating unit respectively.
Antitheft detector the most according to claim 1, it is characterised in that described oscillating unit includes that the 3rd not gate, the 4th NAND gate and the first electric capacity and the first resistance, described 3rd not gate input connect the 4th NAND gate outfan, and outfan connects control gate cell；The first input end of described 4th NAND gate connects control unit, the second input connects the 3rd not gate input through the first resistance, and described first electric capacity is parallel between the 3rd non-gate output terminal and the 4th NAND gate the second input.
Antitheft detector the most according to claim 1, it is characterized in that, described counting unit includes binary system serial counter, and described binary system serial counter pulse input end connects control gate cell, clear terminal connects control unit, and pulse output end connects number of pulses setup unit.
Antitheft detector the most according to claim 1, it is characterized in that, described number of pulses setup unit includes phase inverter, single-pole double-throw switch (SPDT), diode and the second resistance, described phase inverter pulse input end connection count unit, phase inverter every road pulse output end is connected respectively and is connected in parallel to one end of the second resistance after a single-pole double-throw switch (SPDT) and a diode, and the other end of described second resistance connects output unit and control unit；Wherein, in the output of phase inverter every road, the moved end of described single-pole double-throw switch (SPDT) connects the negative electrode of diode, two not moved end connect pulse input end and the pulse output end of phase inverter respectively.
Antitheft detector the most according to claim 1, it is characterized in that, described output unit includes the first audion and the 5th resistance, the base stage of described first audion connects control gate cell sum counter unit through the 5th resistance, the external main frame of emitter stage, colelctor electrode connects number of pulses setup unit and control unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620225220.9U CN205644863U (en) | 2016-03-23 | 2016-03-23 | Antitheft detection appearance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620225220.9U CN205644863U (en) | 2016-03-23 | 2016-03-23 | Antitheft detection appearance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205644863U true CN205644863U (en) | 2016-10-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620225220.9U Expired - Fee Related CN205644863U (en) | 2016-03-23 | 2016-03-23 | Antitheft detection appearance |
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|---|---|
| CN (1) | CN205644863U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105809859A (en) * | 2016-03-23 | 2016-07-27 | 成都锐奕信息技术有限公司 | Circuit applied to anti-theft detector |
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2016
- 2016-03-23 CN CN201620225220.9U patent/CN205644863U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105809859A (en) * | 2016-03-23 | 2016-07-27 | 成都锐奕信息技术有限公司 | Circuit applied to anti-theft detector |
| CN105809859B (en) * | 2016-03-23 | 2018-05-18 | 成都锐奕信息技术有限公司 | A kind of circuit applied to antitheft detector |
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