CN205542781U - Three dimensional integrated circuits chip - Google Patents
Three dimensional integrated circuits chip Download PDFInfo
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- CN205542781U CN205542781U CN201620072706.3U CN201620072706U CN205542781U CN 205542781 U CN205542781 U CN 205542781U CN 201620072706 U CN201620072706 U CN 201620072706U CN 205542781 U CN205542781 U CN 205542781U
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- 239000003990 capacitor Substances 0.000 claims description 39
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 1
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Abstract
The utility model provides a three dimensional integrated circuits chip. Three dimensional integrated circuits chip includes: system NULL, system NULL includes the power network, the dynamic RAM) chip, the dynamic RAM) chip includes the electric capacity unit, system NULL the middle zone of power network with the dynamic RAM) chip electric capacity unit intercommunication, the electric capacity unit is used for the filtering as the unit of decoupling power supply noise on the power network. The utility model discloses a three dimensional integrated circuits chip through the intercommunication of the electric capacity unit on the power network middle zone with the NULL of system and the dynamic RAM) chip, utilizes electric capacity unit on the dynamic RAM) chip as decoupling the unit, and power supply noise on the NULL of the filtering system power network improves the NULL middle zone's of system power supply effect, improves the power supply stability and the antinoise performance of power network.
Description
Technical field
This utility model relates to integrated circuit fields, particularly relates to a kind of three dimensional integrated circuits chip.
Background technology
Along with SOC(system integrated chip) scale increasing, its electric power network design be increasingly becoming difficult point and bottleneck.How to ensure each module in SOC, the module for power supply being especially positioned at chip zone line is stable, reduces Power(power supply) and Gnd(Ground, ground) on noise, often become the key technology determining that can SOC performance even correctly work.
As it is shown in figure 1, in conventional one-piece SOC 110, external power source enters chip by being positioned at the pad 112 of marginal area, and the electric power network 111 by chip internal is delivered to chip everywhere.Under obvious this power supply mode, chip edge region is obtained in that relatively stable reliable power supply near the circuit of pad 112, and noise is less, and the circuit of chip zone line can be poor for electrical stability, and noise is relatively big, thus affects the performance of circuit.In tradition SOC design, decoupling unit (decouple cell, a kind of provide the standard block of decoupling capacitance between power supply and ground, not shown in Fig. 1) can be inserted everywhere at circuit, reduce power-supply fluctuation and noise.Yet with the restriction of standard CMOS process, the capacitance that usual this decoupling unit can be provided by is very limited, and the power supply therefore brought improves the least.
As shown in Figure 2, novel 3DIC(three dimensional integrated circuits) chip includes at least one of which SOC and at least one of which DRAM(dynamic RAM) chip, it is shown in which to be one layer of SOC 210 and one layer of dram chip 220, wherein, power supply on dram chip 220 can be provided in middle optional position by the silicon through hole or dimpling block (not shown) that are located therein a region, but the power supply of SOC 210 provides yet by the pad 212 being positioned at its marginal area, identical with conventional one-piece SOC, therefore the circuit of the zone line of SOC 210 yet suffers from less stable of powering, the problem that noise is bigger, thus affect the performance of circuit.
Utility model content
The purpose of this utility model is to provide a kind of three dimensional integrated circuits chip, improves the power supply effect of system integrated chip zone line, and that improves electric power network supplies electrical stability and noise robustness.
Based on considerations above, this utility model provides a kind of three dimensional integrated circuits chip, including: system integrated chip, described system integrated chip includes electric power network；Dynamic random access memory chip, described dynamic random access memory chip includes capacitor cell；The zone line of the described electric power network of described system integrated chip connects with the described capacitor cell of described dynamic random access memory chip, and described capacitor cell is used for filtering the power supply noise on described electric power network as decoupling unit.
Preferably, the capacitance of the described capacitor cell of described dynamic random access memory chip is on described system integrated chip 100-1000 times of the capacitance of equal area capacitor cell.
Preferably, the described electric power network of described system integrated chip is connected by silicon through hole or dimpling block with the described capacitor cell of described dynamic random access memory chip.
Preferably, including the integrated chip of multilayer system and/or multilamellar dynamic random access memory chip, wherein the described electric power network of an integrated chip of layer system connects with the described capacitor cell of wherein one layer of dynamic random access memory chip.
Preferably, the described electric power network of described system integrated chip connects with external power source by being positioned at the pad of marginal area.
Three dimensional integrated circuits chip of the present utility model, by the electric power network zone line of system integrated chip is connected with the capacitor cell on dynamic random access memory chip, utilize the capacitor cell on dynamic random access memory chip as decoupling unit, power supply noise on filtering appts integrated chip power network, improving the power supply effect of system integrated chip zone line, that improves electric power network supplies electrical stability and noise robustness.
Accompanying drawing explanation
Reading the following detailed description to non-limiting example by referring to accompanying drawing, other features, objects and advantages of the present utility model will become more apparent upon.
Fig. 1 is the structural representation of the integrated chip of existing monolithic system；
Fig. 2 is the structural representation of existing three dimensional integrated circuits chip；
Fig. 3 is the structural representation of three dimensional integrated circuits chip of the present utility model.
In the drawings, running through different diagrams, same or similar reference represents same or analogous device (module) or step.
Detailed description of the invention
For solving above-mentioned the problems of the prior art, this utility model provides a kind of three dimensional integrated circuits chip, by the electric power network zone line of system integrated chip is connected with the capacitor cell on dynamic random access memory chip, utilize the capacitor cell on dynamic random access memory chip as decoupling unit, power supply noise on filtering appts integrated chip power network, improving the power supply effect of system integrated chip zone line, that improves electric power network supplies electrical stability and noise robustness.
In the specific descriptions of following preferred embodiment, by with reference to constituting the accompanying drawing appended by this utility model part.Appended accompanying drawing has been illustrated by way of example and has been capable of specific embodiment of the present utility model.The embodiment of example is not intended as limit according to all embodiments of the present utility model.It is appreciated that on the premise of without departing from scope of the present utility model, it is possible to use other embodiments, it is also possible to carry out the structural or amendment of logicality.Therefore, following specific descriptions are the most nonrestrictive, and scope of the present utility model is defined by the claims appended hereto.
The power supply noise filtering method of three dimensional integrated circuits chip of the present utility model includes: providing system integrated chip 310, described system integrated chip 310 includes electric power network 311；Thering is provided dynamic random access memory chip 320, described dynamic random access memory chip 320 includes capacitor cell 321；Being connected with the described capacitor cell 321 of described dynamic random access memory chip 320 by the zone line of the described electric power network 311 of described system integrated chip 310, described capacitor cell 321 filters the power supply noise on described electric power network 311 as decoupling unit.
Specifically, as shown in Figure 3, it is provided that system integrated chip 310, described system integrated chip 310 includes electric power network 311, this electric power network 311 connects with external power source (not shown) by being positioned at the pad 312 of marginal area, thus is introduced by external power source in system integrated chip 310；Dynamic random access memory chip 320 is provided, described dynamic random access memory chip 320 includes capacitor cell 321, special process due to dynamic random access memory chip 320, the electric capacity of big hundred times than on system integrated chip 310 can be manufactured in equal area, in general, the capacitance of the capacitor cell 321 on dynamic random access memory chip 320 can be on system integrated chip 310 100-1000 times of the capacitance of equal area capacitor cell, so only needing to utilize area the least on dynamic random access memory chip 320, provide for bigger decoupling capacitor；The zone line of the described electric power network 311 of described system integrated chip 310 is connected with the described capacitor cell 321 of described dynamic random access memory chip 320, preferably connected by silicon through hole or dimpling block 330, utilize the capacitor cell 321 on dynamic random access memory chip 320 as decoupling unit, power supply noise on the electric power network 311 of the integrated chip of filtering appts 310, improving the power supply effect of system integrated chip 310 zone line, that improves electric power network 311 supplies electrical stability and noise robustness.
This method only needs the good silicon through hole of advance planning or the position of dimpling block 330 on system integrated chip 310, the area expending system integrated chip 310 is almost negligible, and can be connected with the capacitor cell 321 of dynamic random access memory chip 320 by silicon through hole or dimpling block 330 in any position of electric power network 311 zone line of system integrated chip 310 in theory, it is only necessary to ensure that this region is not the memory element position on dynamic random access memory chip 320.
It will be appreciated by those skilled in the art that, according to actual needs, described three dimensional integrated circuits chip can include the integrated chip of multilayer system 310 and/or multilamellar dynamic random access memory chip 320, the wherein described electric power network of an integrated chip of layer system is connected with the described capacitor cell of wherein one layer of dynamic random access memory chip, utilizes the capacitor cell on this dynamic random access memory chip as decoupling unit power supply noise on filtering appts integrated chip power network.
As it is shown on figure 3, three dimensional integrated circuits chip of the present utility model includes: system integrated chip 310, described system integrated chip 310 includes electric power network 311；Dynamic random access memory chip 320, described dynamic random access memory chip 320 includes capacitor cell 321；The zone line of the described electric power network 311 of described system integrated chip 310 connects with the described capacitor cell 321 of described dynamic random access memory chip 320, and described capacitor cell 321 is used for filtering the power supply noise on described electric power network 311 as decoupling unit.
Preferably, the capacitance of the described capacitor cell 321 of described dynamic random access memory chip 320 is on described system integrated chip 310 100-1000 times of the capacitance of equal area capacitor cell.
Preferably, the described electric power network 311 of described system integrated chip 310 is connected by silicon through hole or dimpling block 330 with the described capacitor cell 321 of described dynamic random access memory chip 320.
Preferably, described three dimensional integrated circuits chip includes the integrated chip of multilayer system 310 and/or multilamellar dynamic random access memory chip 320, and wherein the described electric power network of an integrated chip of layer system connects with the described capacitor cell of wherein one layer of dynamic random access memory chip.
Preferably, the described electric power network 311 of described system integrated chip 310 connects with external power source by being positioned at the pad 312 of marginal area.
Three dimensional integrated circuits chip of the present utility model, by the electric power network zone line of system integrated chip is connected with the capacitor cell on dynamic random access memory chip, utilize the capacitor cell on dynamic random access memory chip as decoupling unit, power supply noise on filtering appts integrated chip power network, improving the power supply effect of system integrated chip zone line, that improves electric power network supplies electrical stability and noise robustness.
It is obvious to a person skilled in the art that this utility model is not limited to the details of above-mentioned one exemplary embodiment, and in the case of without departing substantially from spirit or essential attributes of the present utility model, it is possible to realize this utility model in other specific forms.Therefore, in any case from the point of view of, embodiment all should be regarded as exemplary, and be nonrestrictive.Additionally, it will be evident that " an including " word is not excluded for other elements and step, and wording " one " is not excluded for plural number.In device claim, multiple elements of statement can also be realized by an element.The first, the second word such as grade is used for representing title, and is not offered as any specific order.
Claims (5)
1. a three dimensional integrated circuits chip, it is characterised in that including:
System integrated chip, described system integrated chip includes electric power network；
Dynamic random access memory chip, described dynamic random access memory chip includes capacitor cell；
The zone line of the described electric power network of described system integrated chip connects with the described capacitor cell of described dynamic random access memory chip, and described capacitor cell is used for filtering the power supply noise on described electric power network as decoupling unit.
2. three dimensional integrated circuits chip as claimed in claim 1, it is characterised in that the capacitance of the described capacitor cell of described dynamic random access memory chip is on described system integrated chip 100-1000 times of the capacitance of equal area capacitor cell.
3. three dimensional integrated circuits chip as claimed in claim 1, it is characterised in that the described electric power network of described system integrated chip is connected by silicon through hole or dimpling block with the described capacitor cell of described dynamic random access memory chip.
4. three dimensional integrated circuits chip as claimed in claim 1, it is characterized in that, including the integrated chip of multilayer system and/or multilamellar dynamic random access memory chip, wherein the described electric power network of an integrated chip of layer system connects with the described capacitor cell of wherein one layer of dynamic random access memory chip.
5. three dimensional integrated circuits chip as claimed in claim 1, it is characterised in that the described electric power network of described system integrated chip connects with external power source by being positioned at the pad of marginal area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620072706.3U CN205542781U (en) | 2016-01-26 | 2016-01-26 | Three dimensional integrated circuits chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620072706.3U CN205542781U (en) | 2016-01-26 | 2016-01-26 | Three dimensional integrated circuits chip |
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| Publication Number | Publication Date |
|---|---|
| CN205542781U true CN205542781U (en) | 2016-08-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620072706.3U Withdrawn - After Issue CN205542781U (en) | 2016-01-26 | 2016-01-26 | Three dimensional integrated circuits chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105575967A (en) * | 2016-01-26 | 2016-05-11 | 格科微电子（上海）有限公司 | Three-dimensional integrated circuit chip and power supply noise filtering method therefor |
-
2016
- 2016-01-26 CN CN201620072706.3U patent/CN205542781U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105575967A (en) * | 2016-01-26 | 2016-05-11 | 格科微电子（上海）有限公司 | Three-dimensional integrated circuit chip and power supply noise filtering method therefor |
| CN105575967B (en) * | 2016-01-26 | 2024-01-12 | 格科微电子（上海）有限公司 | Three-dimensional integrated circuit chip and power supply noise filtering method thereof |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20160831 Effective date of abandoning: 20240112 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20160831 Effective date of abandoning: 20240112 |
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| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |