CN205540217U - Analog input device - Google Patents
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Abstract
Description
技术领域technical field
本实用新型涉及DCS控制系统领域,特别是涉及一种模拟量输入装置。The utility model relates to the field of DCS control systems, in particular to an analog quantity input device.
背景技术Background technique
在DCS控制系统中,AI模拟量输入模块使用是很普及的。在现场中经常遇到由于现场环境不太好,传输信号线上耦合了共模信号,当共模信号比较大时对信号的影响很大,导致信号检测不准。现在一般采用的方法是输入端加一个电压跟随放大器进行信号采集,但是该电压跟随放大器是不能对共模信号进行抑制,同时因其输入电阻很低并且对电路中的电阻比值匹配度要求很高,所以共模抑制能力不是很强。In the DCS control system, the use of AI analog input modules is very popular. In the field, it is often encountered that the common mode signal is coupled on the transmission signal line due to the poor site environment. When the common mode signal is relatively large, it will have a great impact on the signal, resulting in inaccurate signal detection. The current general method is to add a voltage follower amplifier to the input for signal acquisition, but the voltage follower amplifier cannot suppress the common mode signal, and because of its low input resistance and high requirements on the matching degree of the resistance ratio in the circuit , so the common mode rejection ability is not very strong.
发明内容Contents of the invention
本实用新型的目的在于针对现有技术的不足,提供一种模拟量输入装置,通过本实用新型的共模抑制电路可以只对差模进行放大,而对共模进行抑制,解决DCS系统中AI模块中抗共模干扰能力不太强的问题。The purpose of this utility model is to provide an analog input device for the deficiencies of the prior art. Through the common mode suppression circuit of the present utility model, only the differential mode can be amplified, and the common mode can be suppressed, so as to solve the problem of AI in the DCS system. The problem that the anti-common mode interference ability in the module is not very strong.
本实用新型的目的是这样实现的:一种模拟量输入装置,包括供电电路、CPU模块、通信电路和通道采集电路,所述供电电路用于给整个AI模块供电,所述通道采集电路用于采集现场设备的信号,并传递给CPU模块,所述CPU模块用于通过通信电路与DCS系统的控制站正确进行通讯,所述通道采集电路设有带高输入阻抗的共模抑制电路,所述共模抑制电路用于对现场信号进行差模放大,同时实现共模抑制。共模抑制电路的输入端为本模拟量输入模块的信号输入端。The purpose of this utility model is achieved as follows: an analog input device, including a power supply circuit, a CPU module, a communication circuit and a channel acquisition circuit, the power supply circuit is used to supply power to the entire AI module, and the channel acquisition circuit is used for Collect the signal of the field equipment and transmit it to the CPU module. The CPU module is used to communicate correctly with the control station of the DCS system through the communication circuit. The channel collection circuit is provided with a common mode suppression circuit with high input impedance. The common-mode suppression circuit is used for differential-mode amplification of field signals while realizing common-mode suppression. The input end of the common mode suppression circuit is the signal input end of the analog input module.
所述共模抑制电路包括第一运放VC1A、第二运放VC1C、第三运放VC1D以及若干电阻,所述第二运放VC1C的同相输入端用于与现场设备的第一信号输出端连接,所述第二运放VC1C的反相输入端分别与第五电阻R5的一端、第七电阻RG的一端连接,所述第五电阻R5的另一端与第二运放VC1C的输出端连接,所述第七电阻RG的另一端分别与第六电阻R6的一端、第三运放VC1D的反相输入端连接,所述第六电阻R6的另一端与第三运放VC1D的输出端连接,所述第二运放VC1C的输出端与第一电阻R1的一端连接,第一电阻R1的另一端分别与第二电阻R2的一端、第一运放VC1A的同相输入端连接,第二电阻R2的另一端与第一运放VC1A的输出端连接,所述第一运放VC1A的输出端与通道采集电路连接,所述第三运放VC1D的同相输入端用于与现场设备的第二信号输出端连接,第三运放VC1D的输出端与第三电阻R3的一端连接,第三电阻R3的另一端分别与第四电阻R4的一端、第一运放VC1A的反相输入端连接,第四电阻R4的另一端接地。本实用新型的共模抑制电路共模抑制能力很强,比如1-5V输入信号,使用传统差模电路,只能保证<20mV的共模电压不会对精度产生影响,而使用本实用新型设计的共模抑制电路,可以在<1V共模信号下对精度无影响。且本实用新型的共模抑制电路有增大输入阻抗的作用,正负两端输入阻抗都特别大,大于108欧姆,输入阻抗高对信号影响小。The common-mode suppression circuit includes a first operational amplifier VC1A, a second operational amplifier VC1C, a third operational amplifier VC1D and several resistors, and the non-inverting input terminal of the second operational amplifier VC1C is used to communicate with the first signal output terminal of the field device connected, the inverting input end of the second operational amplifier VC1C is connected to one end of the fifth resistor R5 and one end of the seventh resistor RG respectively, and the other end of the fifth resistor R5 is connected to the output end of the second operational amplifier VC1C , the other end of the seventh resistor RG is respectively connected to one end of the sixth resistor R6 and the inverting input end of the third op-amp VC1D, and the other end of the sixth resistor R6 is connected to the output end of the third op-amp VC1D , the output end of the second operational amplifier VC1C is connected to one end of the first resistor R1, the other end of the first resistor R1 is respectively connected to one end of the second resistor R2 and the non-inverting input end of the first operational amplifier VC1A, and the second resistor The other end of R2 is connected to the output terminal of the first operational amplifier VC1A, the output terminal of the first operational amplifier VC1A is connected to the channel acquisition circuit, and the non-inverting input terminal of the third operational amplifier VC1D is used to communicate with the second The signal output terminal is connected, the output terminal of the third operational amplifier VC1D is connected with one end of the third resistor R3, and the other end of the third resistor R3 is respectively connected with one end of the fourth resistor R4 and the inverting input terminal of the first operational amplifier VC1A, The other end of the fourth resistor R4 is grounded. The common-mode suppression circuit of the utility model has strong common-mode suppression ability, such as 1-5V input signal, using the traditional differential mode circuit, can only ensure that the common-mode voltage <20mV will not affect the accuracy, but the utility model design The common mode rejection circuit has no effect on the accuracy under the <1V common mode signal. Moreover, the common-mode suppression circuit of the utility model has the function of increasing the input impedance, and the input impedance at both positive and negative ends is particularly large, greater than 10 8 ohms, and the high input impedance has little influence on the signal.
所述第一运放VC1A、第二运放VC1C、第三运放VC1D采用型号为LM324A的集成运放。The first operational amplifier VC1A, the second operational amplifier VC1C, and the third operational amplifier VC1D adopt an integrated operational amplifier model LM324A.
所述通道采集电路还包括滤波电路和采样电路,所述滤波电路和采样电路设置在共模抑制电路与CPU模块之间,所述共模抑制电路的输入端用于接收现场信号,所述共模抑制电路的输出端与滤波电路的输入端连接,所述滤波电路的输出端与采样电路的输入端连接,所述采样电路的输出端与CPU模块连接。采样电路一般情况是AD转换电路。若CPU模块自带AD转换功能,则本实用新型的通道采集电路无需设置AD转换电路。滤波电路是滤掉信号中的噪声等干扰。The channel acquisition circuit also includes a filter circuit and a sampling circuit, the filter circuit and the sampling circuit are arranged between the common-mode suppression circuit and the CPU module, the input end of the common-mode suppression circuit is used to receive field signals, and the common-mode suppression circuit The output end of the mode suppression circuit is connected with the input end of the filter circuit, the output end of the filter circuit is connected with the input end of the sampling circuit, and the output end of the sampling circuit is connected with the CPU module. The sampling circuit is generally an AD conversion circuit. If the CPU module has its own AD conversion function, then the channel acquisition circuit of the present utility model does not need to be provided with an AD conversion circuit. The filter circuit is to filter out interference such as noise in the signal.
所述CPU模块与通道采集电路之间设有第一隔离电路。A first isolation circuit is provided between the CPU module and the channel acquisition circuit.
所述CPU模块与通信电路之间设有第二隔离电路。A second isolation circuit is provided between the CPU module and the communication circuit.
由于采用了上述方案,由于本实用新型的通道采集电路设有带高输入阻抗的共模抑制电路,所述共模抑制电路用于对现场信号进行差模放大,对共模进行抑制。通过本实用新型的共模抑制电路可以只对差模进行放大对共模进行抑制,采用了本电路的AI输入模块共模抑制比很高,且输入阻抗很大。Due to the adoption of the above scheme, the channel acquisition circuit of the present invention is provided with a common-mode suppression circuit with high input impedance, and the common-mode suppression circuit is used for differential-mode amplification of field signals and suppression of common-mode. The common mode suppression circuit of the utility model can only amplify the differential mode and suppress the common mode, and the AI input module adopting the circuit has a high common mode suppression ratio and a large input impedance.
下面结合附图和具体实施方式对本实用新型作进一步说明。Below in conjunction with accompanying drawing and specific embodiment, the utility model is further described.
附图说明Description of drawings
图1为本实用新型的模拟量输入装置的原理框图;Fig. 1 is the functional block diagram of the analog quantity input device of the present utility model;
图2为本实用新型的共模抑制电路的电路图。Fig. 2 is a circuit diagram of the common mode suppression circuit of the present invention.
具体实施方式detailed description
参见图1,一种模拟量输入装置,包括供电电路、CPU模块、通信电路和通道采集电路,所述供电电路用于给整个AI模块供电,所述通道采集电路用于采集现场信号,并将现场信号传递给CPU模块。所述通道采集电路设有带高输入阻抗的共模抑制电路,所述共模抑制电路用于对现场信号进行差模放大,同时实现共模抑制。共模抑制电路的输入端为本模拟量输入模块的信号输入端。所述通道采集电路还包括滤波电路和采样电路,所述滤波电路和采样电路设置在共模抑制电路与CPU模块之间,所述共模抑制电路的输入端用于接收现场信号,所述共模抑制电路的输出端与滤波电路的输入端连接,所述滤波电路的输出端与采样电路的输入端连接,所述采样电路的输出端与CPU模块连接。采样电路一般情况是AD转换电路。若CPU模块自带AD转换功能,则本实用新型的通道采集电路无需设置AD转换电路。滤波电路是滤掉信号中的噪声等干扰。所述CPU模块连接EEPROM存取电路,可以保存一些设置参数。所述CPU模块与通道采集电路之间设有第一隔离电路。所述CPU模块用于通过通信电路与DCS系统的控制站进行通讯。所述CPU模块与通信电路之间设有第二隔离电路。通信电路是进行通信的电路。通过通信电路,CPU可以和控制站进行通信。通信电路的核心是采用的通信芯片,比如SP485等。它一边接外边的485总线,一边接上边的隔离电路。Referring to Fig. 1, an analog quantity input device includes a power supply circuit, a CPU module, a communication circuit and a channel acquisition circuit, the power supply circuit is used to supply power to the entire AI module, the channel acquisition circuit is used to collect field signals, and The field signal is passed to the CPU module. The channel acquisition circuit is provided with a common-mode suppression circuit with high input impedance, and the common-mode suppression circuit is used for differential-mode amplification of field signals while realizing common-mode suppression. The input end of the common mode suppression circuit is the signal input end of the analog input module. The channel acquisition circuit also includes a filter circuit and a sampling circuit, the filter circuit and the sampling circuit are arranged between the common-mode suppression circuit and the CPU module, the input end of the common-mode suppression circuit is used to receive field signals, and the common-mode suppression circuit The output end of the mode suppression circuit is connected with the input end of the filter circuit, the output end of the filter circuit is connected with the input end of the sampling circuit, and the output end of the sampling circuit is connected with the CPU module. The sampling circuit is generally an AD conversion circuit. If the CPU module has its own AD conversion function, then the channel acquisition circuit of the present utility model does not need to be provided with an AD conversion circuit. The filter circuit is to filter out interference such as noise in the signal. The CPU module is connected with an EEPROM access circuit, and can save some setting parameters. A first isolation circuit is provided between the CPU module and the channel acquisition circuit. The CPU module is used for communicating with the control station of the DCS system through the communication circuit. A second isolation circuit is provided between the CPU module and the communication circuit. A communication circuit is a circuit that communicates. Through the communication circuit, the CPU can communicate with the control station. The core of the communication circuit is the communication chip used, such as SP485 and so on. It is connected to the 485 bus outside and the isolation circuit on the other side.
参见图2,所述共模抑制电路包括第一运放VC1A、第二运放VC1C、第三运放VC1D以及若干电阻,所述第二运放VC1C的同相输入端用于与现场设备的第一信号输出端连接,所述第二运放VC1C的反相输入端分别与第五电阻R5的一端、第七电阻RG的一端连接,所述第五电阻R5的另一端与第二运放VC1C的输出端连接,所述第七电阻RG的另一端分别与第六电阻R6的一端、第三运放VC1D的反相输入端连接,所述第六电阻R6的另一端与第三运放VC1D的输出端连接,所述第二运放VC1C的输出端与第一电阻R1的一端连接,第一电阻R1的另一端分别与第二电阻R2的一端、第一运放VC1A的同相输入端连接,第二电阻R2的另一端与第一运放VC1A的输出端连接,所述第一运放VC1A的输出端与通道采集电路连接,所述第三运放VC1D的同相输入端用于与现场设备的第二信号输出端连接,第三运放VC1D的输出端与第三电阻R3的一端连接,第三电阻R3的另一端分别与第四电阻R4的一端、第一运放VC1A的反相输入端连接,第四电阻R4的另一端接地。所述第一运放VC1A、第二运放VC1C、第三运放VC1D采用型号为LM324A的集成运放。本实用新型的共模抑制电路共模抑制能力很强,比如1-5V输入信号,使用传统差模电路,只能保证<20mV的共模电压不会对精度产生影响,而使用本实用新型设计的共模抑制电路,可以在<1V共模信号下对精度无影响。且本实用新型的共模抑制电路有增大输入阻抗的作用,正负两端输入阻抗都特别大,大于108.。Referring to Fig. 2, the common mode suppression circuit includes a first operational amplifier VC1A, a second operational amplifier VC1C, a third operational amplifier VC1D and several resistors, and the non-inverting input terminal of the second operational amplifier VC1C is used to communicate with the first operational amplifier of the field device A signal output terminal is connected, the inverting input terminal of the second operational amplifier VC1C is connected with one end of the fifth resistor R5 and one end of the seventh resistor RG respectively, and the other end of the fifth resistor R5 is connected with the second operational amplifier VC1C The other end of the seventh resistor RG is connected to one end of the sixth resistor R6 and the inverting input end of the third operational amplifier VC1D respectively, and the other end of the sixth resistor R6 is connected to the third operational amplifier VC1D The output end of the second operational amplifier VC1C is connected to one end of the first resistor R1, and the other end of the first resistor R1 is respectively connected to one end of the second resistor R2 and the non-inverting input end of the first operational amplifier VC1A , the other end of the second resistance R2 is connected with the output terminal of the first operational amplifier VC1A, the output terminal of the first operational amplifier VC1A is connected with the channel acquisition circuit, and the non-inverting input terminal of the third operational amplifier VC1D is used to communicate with the field The second signal output terminal of the device is connected, the output terminal of the third operational amplifier VC1D is connected to one end of the third resistor R3, and the other end of the third resistor R3 is respectively connected to one end of the fourth resistor R4 and the reverse phase of the first operational amplifier VC1A The input end is connected, and the other end of the fourth resistor R4 is grounded. The first operational amplifier VC1A, the second operational amplifier VC1C, and the third operational amplifier VC1D adopt an integrated operational amplifier model LM324A. The common-mode suppression circuit of the utility model has strong common-mode suppression ability, such as 1-5V input signal, using the traditional differential mode circuit, can only ensure that the common-mode voltage <20mV will not affect the accuracy, but the utility model design The common mode rejection circuit has no effect on the accuracy under the <1V common mode signal. Moreover, the common mode suppression circuit of the present invention has the effect of increasing the input impedance, and the input impedance at both positive and negative ends is particularly large, greater than 10 8 .
参见图2,设R1=R3, R2=R4, R5=R6. 那么根据电路知识可以得到:Uout=-(Uin+-Uin-)(1+2R5/RG)R2/R1 。根据这个推倒公式,可以看到输出电压只和输入电压的差有关系。想把输入的差放大多少倍就相应的取值。其中的电阻R5, . RG R2,R1都是精密电阻可根据具体需要自己匹配,这样的话,共模信号在本电路就被极大的抑制了。采用了本电路的AI输入模块共模抑制比很高。根据我们的AI模块实测共模交流抑制电压可以达到250V.Ac,共模直流可达1V,而改进前分别为40V.ac. 20mV.dc。Referring to Figure 2, set R1=R3, R2=R4, R5=R6. Then according to circuit knowledge, it can be obtained: Uout=-(U in+ -U in- )(1+2R 5 /R G )R 2 /R 1 . According to this deduction formula, it can be seen that the output voltage is only related to the difference of the input voltage. How many times you want to amplify the input difference is the corresponding value. The resistors R 5, R G R 2, and R 1 are precision resistors that can be matched according to specific needs. In this case, the common mode signal is greatly suppressed in this circuit. The common mode rejection ratio of the AI input module using this circuit is very high. According to our AI module, the common-mode AC suppression voltage can reach 250V.Ac, and the common-mode DC can reach 1V, compared to 40V.ac. 20mV.dc before improvement.
本实用新型不仅仅局限于上述实施例,在不背离本实用新型技术方案原则精神的情况下进行些许改动的技术方案,应落入本实用新型的保护范围。The utility model is not limited to the above-mentioned embodiments, and technical solutions with slight changes without departing from the spirit of the technical solutions of the utility model shall fall into the protection scope of the utility model.
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