CN205540213U - Numerical control IO bus control system - Google Patents
Numerical control IO bus control system Download PDFInfo
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- CN205540213U CN205540213U CN201520762894.8U CN201520762894U CN205540213U CN 205540213 U CN205540213 U CN 205540213U CN 201520762894 U CN201520762894 U CN 201520762894U CN 205540213 U CN205540213 U CN 205540213U
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Abstract
The utility model relates to a numerical control IO bus control system directly passes through the communication of PCI interface through numerical control module and IO bus controller, has improved communication efficiency greatly, the real time transport of a large amount of data of being convenient for. PCI interface module and bus control module realize through the hardware description language programming in FPGA. The FPGA structure is nimble, fast, can effectively improve data processing and transmission efficiency to convenient subsequent function development. Since not need like general bus controller consider with multiple hardware compatibility, consequently, bus order is very retrencied, has promoted communication efficiency greatly.
Description
Technical field
This utility model relates to automation control area, particularly relates to a kind of simple in construction, numerical control IO bus control system that efficiency is high.
Background technology
Field bus technique, since promoting, has the most worldwide been applied to the every field of Industry Control.The technology of fieldbus or has been applied to the industry-by-industries such as metallurgy, automobile making, tobacco machine, environmental conservation, petrochemical industry, electric power energy, textile machine.The bus protocol of application mainly includes PROFIBUS, DeviceNet, Foundation, Fieldbus, Interbus_S etc..The field bus control system of design abroad has been applied very extensive, from stand-alone device to the induction system of whole production line, all uses the control method of fieldbus.And domestic application still mostly centralized production line induction system, will necessarily progressively extend its application along with the development of technology and the renewal of idea.General bus unit is owing to consider and the compatibility of multiple industrial equipment, and general structure is complicated, communication speed is limited, cost is high, it is impossible to meet user to cost and the demand of efficiency.
Utility model content
Based on this, it is necessary to provide the numerical control IO bus control system that a kind of simple in construction, efficiency are high.
A kind of numerical control IO bus control system, including numerical control module, IO bus control unit and I/O module；
Described IO bus control unit connects described numerical control module by pci interface, and described IO bus control unit connects described I/O module by IO bus；
Described IO bus control unit includes pci interface module, bus control module and the bus interface module being sequentially connected with；
Described pci interface module is for realizing the communication of described IO bus control unit and described pci interface；
Described bus control module is for processing the order of described IO bus and address distribution；
Described bus interface module is for realizing data transmission between described IO bus control unit and described I/O module；
Described numerical control module carries out data interaction by described pci interface and described IO bus control unit, data and instruction that described pci interface is transmitted by described IO bus control unit are sent in IO bus, and the data returned in described IO bus are transferred to described pci interface module；
Described I/O module is the slave station of described IO bus, for carrying out communication with described IO bus control unit.
Wherein in an embodiment, described pci interface module uses the hardware description language programming realization of FPGA with described bus control module.
Wherein in an embodiment, described pci interface module includes data input/output module, configuration module, state machine module and data processing module；Described data input/output module is simultaneously connected with described configuration module, described state machine module and described data processing module；
Described data input/output module is for extracting the input data on described pci interface, and the data that simultaneously will send export on described pci interface, and carries out sequential scheduling and supervisor's time-sharing multiplex process；
Described configuration module is used for distributing PCI address space；
Described state machine module is used for processing PCI communication process；
Described data processing module inputs the effective information in data for extracting on pci interface, and described effective information is sent to described bus control module；The data that described bus control module returns are transferred on pci interface simultaneously.
Wherein in an embodiment, described state machine module is used for monitoring user and detects voltage, temperature and WDT.
Wherein in an embodiment, described bus control module includes bus line command processing module, described address assignment module and described data transmission module；
Described bus line command processing module is for reading and writing the bus line command in memory module；Described address assignment module is for being divided into different sections to define memory module by PCI address space；
Described data transmission module is for exporting the instruction of described bus control module transmission and being read in described bus control module by the pci data in IO bus.
Wherein in an embodiment, described memory module includes depositor and RAM memory.
Wherein in an embodiment, the corresponding different depositor of described every sector address.
Wherein in an embodiment, described address assignment module is that each slave station distributes address, and is defined the address space within slave station.
Wherein in an embodiment, the address of described IO bus and data use the data bits of 8bit.
Wherein in an embodiment, the address of described slave station from 00 to FF be incremented by successively every 8 addresses, and in the internal address space of described slave station introduce index.
Above-mentioned numerical control IO bus control system directly passes through pci interface communication by numerical control module with IO bus control unit, substantially increases communication efficiency, it is simple to the real-time Transmission of mass data.Pci interface module and bus control module pass through hardware description language programming realization in FPGA.FPGA structure is flexible, speed is fast, it is possible to is effectively improved data and processes and efficiency of transmission, and facilitates follow-up functions expanding.Owing to need not consider as versabus controller and plurality of devices compatibility, therefore, bus line command is extremely simplified, and is greatly improved communication efficiency.
Accompanying drawing explanation
Fig. 1 is the module map of numerical control IO bus control system；
Fig. 2 is the module map of IO bus control unit；
Fig. 3 is the module map of pci interface module；
Fig. 4 is the module map of bus control module；
Fig. 5 is that PCI address space divides schematic diagram；
Fig. 6 is tributary address schematic diagram；
Fig. 7 is that tributary address indexes schematic diagram；
Fig. 8 is the byte definition schematic diagram of depositor.
Detailed description of the invention
For the ease of understanding this utility model, below with reference to relevant drawings, this utility model is described more fully.Accompanying drawing gives preferred embodiment of the present utility model.But, this utility model can realize in many different forms, however it is not limited to embodiment described herein.On the contrary, providing the purpose of these embodiments is to make the understanding to disclosure of the present utility model more thorough comprehensively.
It should be noted that be referred to as " being fixed on " another element when element, it can be directly on another element or can also there is element placed in the middle.When an element is considered as " connection " another element, and it can be directly to another element or may be simultaneously present centering elements.Term as used herein " vertical ", " level ", "left", "right" and similar statement are for illustrative purposes only.
Unless otherwise defined, all of technology used herein and scientific terminology are identical with belonging to the implication that those skilled in the art of the present utility model are generally understood that.It is intended merely to describe the purpose of specific embodiment at term used in the description of the present utility model herein, it is not intended that in limiting this utility model.Term as used herein " and/or " include the arbitrary and all of combination of one or more relevant Listed Items.
As it is shown in figure 1, be the module map of numerical control IO bus control system.
Incorporated by reference to Fig. 2.
A kind of numerical control IO bus control system, including numerical control module 101, IO bus control unit 102 and I/O module 103.
Described IO bus control unit 102 connects described numerical control module 101 by pci interface (Peripheral Component Interconnect, Peripheral Component Interconnect standard), and described IO bus control unit 102 connects described I/O module 103 by IO bus.
Described IO bus control unit 102 includes pci interface module 201, bus control module 202 and the bus interface module 203 being sequentially connected with.
Described pci interface module 201 is for realizing the communication of described IO bus control unit 102 and described pci interface.
Described bus control module 202 is for processing the order of described IO bus and address distribution.
Described bus interface module 203 is for realizing data transmission between described IO bus control unit 102 and described I/O module 103.
Described numerical control module 101 carries out data interaction by described pci interface and described IO bus control unit 102, data and instruction that described pci interface is transmitted by described IO bus control unit 102 are sent in IO bus, and the data returned in described IO bus are transferred to described pci interface module 201.
Described I/O module 103 is the slave station of described IO bus, for carrying out communication with described IO bus control unit 102.
In the present embodiment, numerical control module 101 carries out data interaction by the pci interface of PCI machine and IO bus control unit.The data that PCI machine is transmitted by IO bus control unit 102 instruct well and are sent in IO bus, and the data returned in IO bus are transferred to pci interface module 201.Owing to I/O module 103 carries out communication as slave station and the IO bus control unit 102 of IO bus.Numerical control module 101 and IO bus control unit 102 directly by pci interface communication, greatly increase communication efficiency, it is simple to the real-time Transmission of mass data.
In the present embodiment, pci interface module 201 and described bus control module 202 use the hardware description language programming realization of FPGA.
Incorporated by reference to Fig. 3.
Pci interface module includes data input/output module 301, configuration module 302, state machine module 303 and data processing module 304；Described data input/output module 301 is simultaneously connected with described configuration module 302, described state machine module 303 and described data processing module 304.
Described data input/output module 301 is for extracting the input data on described pci interface, and the data that simultaneously will send export on described pci interface, and carries out sequential scheduling and supervisor's time-sharing multiplex process.
Described configuration module 302 is used for distributing PCI address space.
Described state machine module 303 is used for processing PCI communication process.
Described data processing module 303 inputs the effective information in data for extracting on pci interface, and described effective information is sent to described bus control module 202；The data that described bus control module returns are transferred on pci interface simultaneously.
State machine module 303 is additionally operable to monitor user and detects voltage, temperature and WDT.
Pci interface module 201 realizes the communication of IO bus control unit 102 and the pci interface of PC, and bus control module 202 realizes bus line command process, address distribution.Bus interface module 203 realizes the data transmission of IO bus control unit 102 and I/O module 103.
Incorporated by reference to Fig. 4.
In the present embodiment, bus control module 202 includes bus line command processing module 401, described address assignment module 402 and described data transmission module 403.
Described bus line command processing module 401 is for reading and writing the bus line command in memory module；Described address assignment module 402 is for being divided into different sections to define memory module by PCI address space.
Described data transmission module 403 is for exporting the instruction of described bus control module 202 transmission and being read in described bus control module 202 by the pci data in IO bus.
In the present embodiment, bus line command module 401 realizes bus line command control by read-write register.PCI address space is divided into different sections and carrys out definition register.As shown in Figure 5.The corresponding different depositor of every sector address, by the process of the implementing reading and writing bus line command of depositor.Hardware configuration is for realizing the definition of the hardware informations such as the size of the selection of communication speed, memory space；IO bus control unit 102 is for bus address and the read-write of data；Condition monitoring user detects the signals such as voltage, temperature, house dog；RAM (Random-Access Memory, random access memory) is used for storage and the read-write of data.Owing to need not consider as versabus controller and plurality of devices compatibility, the bus line command that therefore IO bus control unit 102 sends extremely is simplified, and is greatly improved communication efficiency.
Pci interface module 201 and bus control module 202 pass through hardware description language programming realization in FPGA (Field-Programmable Gate Array, field programmable gate array).FPGA structure is flexible, speed is fast, it is possible to is effectively improved data and processes and efficiency of transmission, and facilitates follow-up functions expanding.
In the present embodiment, memory module includes depositor and RAM memory.
In the present embodiment, the corresponding different depositor of every sector address.
Address assignment module is that each slave station distributes address, and is defined the address space within slave station.
The address of slave station from 00 to FF be incremented by successively every 8 addresses, and in the internal address space of described slave station introduce index.
Concrete, on the one hand address assignment module is that each slave station distributes address, is on the other hand defined slave station internal address space.IO bus address and data all use the data bits of 8bit, so can ensure that address, input data, output data are transmitted on the pci interface of 32 simultaneously, can improve efficiency of transmission and the real-time of data.The address of slave station from 00 to FF be incremented by successively, as shown in Figure 6 every 8 addresses.8 addresses at interval use as the internal address space of slave station, and 8 addresses are very limited, it is impossible to carry out the logic control of complexity, introduce index, greatly increase the utilization rate of address space, as shown in Figure 7 in the internal address space of slave station.
The transmission means of bus interface module 203 major control IO bus data and sequential, first byte (bit0-7) of IO bus control register in PCI address space is defined as IO bus address (C), second byte (bit8-15) is defined as IO bus output data (A), 3rd byte (bit16-23) is defined as IO bus input data (B), as shown in Figure 8.The when of writing data in bus, address C is defaulted as 0, and first-selection writes data on A, writes on C by destination address again after postponing 1us, and slave station needs to read data A during address C is converted to 0；The when that IO bus control unit 102 reading data from bus, address C is defaulted as 0, first writes on C by destination address, behind slave station identification address, response data is write on B, and at this moment bus control unit can read data, and after completing, address C switches to 0 again.
Based on above-mentioned all embodiments, numerical control IO bus control system simple in construction, speed are fast, easy to use, low cost；Numerical control module 101 and IO bus control unit 102 directly by pci interface communication, greatly increase communication efficiency, it is simple to the real-time Transmission of mass data；
Using FPGA as processor, its flexible structure, speed are fast, it is possible to are effectively improved data and process and efficiency of transmission, and facilitate follow-up functions expanding；And bus line command extremely simplifies, it is greatly improved communication efficiency.
In the internal address space of slave station, introduce index, greatly increase the utilization rate of address space；Self-defining numerical control IO bus control system special IO bus, it is not necessary to buy IP kernel and the asic chip of versabus controller, reduce the finished product of product.
Based on above-mentioned all embodiments, in PCI address space, the distribution of register address can change flexibly according to user's request.
The address of IO bus and data bits can be other numerical value, such as 16bit or 32bit；
The address distribution of slave station can be order or backward.
Direct address and the index address method of salary distribution of the address space of slave station can change flexibly according to user's request.
Above-mentioned numerical control IO bus control system directly passes through pci interface communication by numerical control module 101 with IO bus control unit 102, substantially increases communication efficiency, it is simple to the real-time Transmission of mass data.Pci interface module 201 and bus control module 202 pass through hardware description language programming realization in FPGA.FPGA structure is flexible, speed is fast, it is possible to is effectively improved data and processes and efficiency of transmission, and facilitates follow-up functions expanding.Owing to need not consider as versabus controller and plurality of devices compatibility, therefore, bus line command is extremely simplified, and is greatly improved communication efficiency.
Each technical characteristic of embodiment described above can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, all it is considered to be the scope that this specification is recorded.
Embodiment described above only have expressed several embodiments of the present utility model, and it describes more concrete and detailed, but therefore can not be interpreted as the restriction to utility model patent scope.It should be pointed out that, for the person of ordinary skill of the art, without departing from the concept of the premise utility, it is also possible to make some deformation and improvement, these broadly fall into protection domain of the present utility model.Therefore, the protection domain of this utility model patent should be as the criterion with claims.
Claims (10)
1. a numerical control IO bus control system, it is characterised in that include numerical control module, IO bus control unit and I/O module；
Described IO bus control unit connects described numerical control module by pci interface, and described IO bus control unit connects described I/O module by IO bus；
Described IO bus control unit includes pci interface module, bus control module and the bus interface module being sequentially connected with；
Described pci interface module is for realizing the communication of described IO bus control unit and described pci interface；
Described bus control module is for processing the order of described IO bus and address distribution；
Described bus interface module is for realizing data transmission between described IO bus control unit and described I/O module；
Described numerical control module carries out data interaction by described pci interface and described IO bus control unit, data and instruction that described pci interface is transmitted by described IO bus control unit are sent in IO bus, and the data returned in described IO bus are transferred to described pci interface module；
Described I/O module is the slave station of described IO bus, for carrying out communication with described IO bus control unit.
Numerical control IO bus control system the most according to claim 1, it is characterised in that described pci interface module uses the hardware description language programming realization of FPGA with described bus control module.
Numerical control IO bus control system the most according to claim 1, it is characterised in that described pci interface module includes data input/output module, configuration module, state machine module and data processing module；Described data input/output module is simultaneously connected with described configuration module, described state machine module and described data processing module；
Described data input/output module is for extracting the input data on described pci interface, and the data that simultaneously will send export on described pci interface, and carries out sequential scheduling and supervisor's time-sharing multiplex process；
Described configuration module is used for distributing PCI address space；
Described state machine module is used for processing PCI communication process；
Described data processing module inputs the effective information in data for extracting on pci interface, and described effective information is sent to described bus control module；The data that described bus control module returns are transferred on pci interface simultaneously.
Numerical control IO bus control system the most according to claim 3, it is characterised in that described state machine module is used for monitoring user and detects voltage, temperature and WDT.
Numerical control IO bus control system the most according to claim 1, it is characterised in that described bus control module includes bus line command processing module, address assignment module and data transmission module；
Described bus line command processing module is for reading and writing the bus line command in memory module；Described address assignment module is for being divided into different sections to define memory module by PCI address space；
Described data transmission module is for exporting the instruction of described bus control module transmission and being read in described bus control module by the pci data in IO bus.
Numerical control IO bus control system the most according to claim 5, it is characterised in that described memory module includes depositor and RAM memory.
Numerical control IO bus control system the most according to claim 5, it is characterised in that the corresponding different depositor of described every sector address.
Numerical control IO bus control system the most according to claim 5, it is characterised in that described address assignment module is that each slave station distributes address, and is defined the address space within slave station.
Numerical control IO bus control system the most according to claim 5, it is characterised in that the address of described IO bus and data use the data bits of 8bit.
Numerical control IO bus control system the most according to claim 5, it is characterised in that the address of described slave station from 00 to FF be incremented by successively every 8 addresses, and in the internal address space of described slave station introduce index.
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Effective date of registration: 20170620 Address after: Dazu laser Building No. 9 Nanshan District high tech Park North new road Shenzhen city Guangdong province 518000 Co-patentee after: HAN'S PA AUTOMATION TECHNOLOGY Co.,Ltd. Patentee after: HAN'S LASER TECHNOLOGY INDUSTRY GROUP Co.,Ltd. Co-patentee after: SHENZHEN HAN'S SMART CONTROL TECHNOLOGY Co.,Ltd. Address before: Dazu laser Building No. 9 Nanshan District high tech Park North new road Shenzhen city Guangdong province 518000 Co-patentee before: HAN'S PA AUTOMATION TECHNOLOGY Co.,Ltd. Patentee before: HAN'S LASER TECHNOLOGY INDUSTRY GROUP Co.,Ltd. |
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Address after: 518000 Dazu laser building, 9 new West Road, North Nanshan District high tech park, Shenzhen, Guangdong Patentee after: HAN'S LASER TECHNOLOGY INDUSTRY GROUP Co.,Ltd. Patentee after: Shenzhen Han's photon laser technology Co.,Ltd. Patentee after: SHENZHEN HAN'S SMART CONTROL TECHNOLOGY Co.,Ltd. Address before: 518000 Dazu laser building, 9 new West Road, North Nanshan District high tech park, Shenzhen, Guangdong Patentee before: HAN'S LASER TECHNOLOGY INDUSTRY GROUP Co.,Ltd. Patentee before: HAN'S PA AUTOMATION TECHNOLOGY Co.,Ltd. Patentee before: SHENZHEN HAN'S SMART CONTROL TECHNOLOGY Co.,Ltd. |
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