CN205488099U - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN205488099U CN205488099U CN201620256676.1U CN201620256676U CN205488099U CN 205488099 U CN205488099 U CN 205488099U CN 201620256676 U CN201620256676 U CN 201620256676U CN 205488099 U CN205488099 U CN 205488099U
- Authority
- CN
- China
- Prior art keywords
- heat sink
- lead
- heating panel
- semiconductor device
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
Abstract
Semiconductor device. Under the condition of carrying on the great semiconductor chip of a plurality of areas, the heating panel increase, there is following problem in its result: the transverse dimension increase of the peripheral body to lead to the installation space increase on the printed base plate. The utility model discloses a semiconductor device has: a plurality of heating panels of alternate segregation ground configuration, a plurality of outside leads, carry on the semiconductor chip on the heating panel, and the peripheral body, it is to the heating panel, outside lead and semiconductor chip seal, the outside lead disposes in the 1st direction along the tip of the heating panel of party side by side, the heating panel of party and another party's heating panel are in the configuration side by side in the 2nd criss -cross direction with the 1st direction, the 1 connectiong lead that is connected with the heating panel of party and the 2 connectiong lead that is connected with another party's heating panel are disposed in side of the heating panel of another party's heating panel and party respectively and are extended in the 2nd direction.
Description
Technical field
This utility model relates to semiconductor device, particularly to being equipped with multiple heat sinks of semiconductor chip by outer containment body
The semiconductor device sealed.
Background technology
Known have such resin molded semiconductor device: it utilizes and is sealed by the outer containment body constituted such as resin moulded
It is equipped with multiple heat sinks of semiconductor chip.
Such as, Patent Document 1 discloses a kind of resin molded semiconductor device, this semiconductor device possesses:
The power there is multiple heat sink and the lead frame of outside lead (lead terminal), being equipped on each heat sink half
Conductor chip and control use IC chip, by moulding resin to lead frame, power semiconductor chip and control
Seal with IC chip.
This semiconductor device is SIP (single in-line packages: the Single that outside lead is arranged on the side of heat sink
Inline Package) semiconductor device of type, it is equipped with outside the heat sink of semiconductor chip along transverse width direction is
The orientation of portion's lead-in wire configures.
[patent documentation 1]: Japanese Unexamined Patent Publication 2012-19084 publication
In general, SIP type semiconductor device is that its outside lead is inserted on printed base plate the hole (hole) arranged
In and carry out what welding etc. was installed.
But, in the prior art, although less for problem from the point of view of the semiconductor chip that area is less, but carrying
In the case of multiple bigger semiconductor chips, heat sink increases, and its result is to there is following problem: outer containment body (envelope
Dress) lateral dimension increase, thus cause the installing space on printed base plate to increase.
Utility model content
This utility model completes to solve above-mentioned problem, its object is to provide semiconductor device, and it will be taken
The heat sink being loaded with semiconductor chip configures along the vertical direction, thus suppresses to encapsulate the increase of transverse width.
In order to solve above-mentioned problem, this utility model becomes structure shown below.
That is, semiconductor device of the present utility model has: the multiple heat sinks configured separated from each other；Multiple outsides are drawn
Line；The semiconductor chip being equipped on heat sink；And outer containment body, it is to heat sink, outside lead and quasiconductor
Chip seals, and outside lead configures on the 1st direction side by side along the end of the heat sink of a side, and a side dissipates
The heat sink of hot plate and the opposing party configures, side by side with the heat sink phase of a side on the 2nd direction intersected with the 1st direction
The 1st connecting lead wire and the 2nd connecting lead wire being connected with the heat sink of the opposing party that connect are configured in the opposing party respectively
The side of heat sink and the side of heat sink of a side upwardly extending the 2nd side.
This utility model has the effect that
(1) configure side by side on the 2nd direction that the orientation with outside lead intersects due to multiple heat sinks, because of
This can reduce the transverse width (outer containment body width on the 1st direction being configured with outside lead) of outer containment body.
(2) by the 1st connecting lead wire and the 2nd connecting lead wire are used as outside lead, by increasing capacitance it is possible to increase outside is drawn
The number of the arrangement of line is without the lateral dimension increasing outer containment body.
(3) if the 1st connecting lead wire and the 2nd connecting lead wire are used as the connector connect to even muscle, then can
Prevent the bending of heat sink, it is possible to increase the reliability of semiconductor device.
Accompanying drawing explanation
Fig. 1 is the top view of the interior sight structure of the semiconductor device representing embodiment 1 of the present utility model.
Fig. 2 is the top view of the lead frame of the semiconductor device representing embodiment 1 of the present utility model.
Fig. 3 is the close-up sectional view of the connecting lead wire of the semiconductor device representing embodiment 1 of the present utility model.
Label declaration
1: semiconductor chip；2: semiconductor chip；The heat sink of 3: one sides；31: outside lead；32: connect
Body；33: the 1 connecting lead wires；4: the heat sink of the opposing party；41: outside lead；42: connector；43: the
2 connecting lead wires；5: even muscle；6: even muscle；7: outside lead；8: wire rod；9: outer containment body；11: quasiconductor
Device；12: lead frame.
Detailed description of the invention
Below, referring to the drawings to being used for implementing mode of the present utility model being described in detail.But, this practicality is new
Type is not limited to following contents.
Embodiment 1
The semiconductor device 11 of embodiment 1 of the present utility model is illustrated.Fig. 1 is to represent semiconductor device 11
The top view of interior sight structure.Fig. 2 is the top view of the lead frame structure representing semiconductor device 11.
As it is shown in figure 1, semiconductor device 11 be have on lead frame 12 semiconductor chip 1,2, wire rod 8,
And the resin molded semiconductor device of outer containment body 9.
As in figure 2 it is shown, about lead frame 12, the heat sink 3 of a side and the heat sink 4 of the opposing party with phase each other
To mode configure side by side on the 2nd direction intersected with the 1st direction.
Lead frame 12 has the 1st connecting lead wire 33 that the heat sink 3 with a side is connected, the 1st connecting lead wire 33
It is configured in the side of the heat sink 4 of the opposing party and upwardly extends the 2nd side.
Lead frame 12 has the 2nd connecting lead wire 43 that the heat sink 4 with the opposing party is connected, the 2nd connecting lead wire
The side of 43 heat sinks 3 being configured in a side and upwardly extending the 2nd side.
1st direction refers to the configuration direction of outside lead, is left and right directions (laterally) in FIG.
Then, the outside lead of lead frame 2 is illustrated.
It is attached by outside lead 31 towards even muscle 6 from the heat sink 3 of a side.It addition, with the heat sink of a side
3 the 1st connecting lead wires 33 being connected are connected with company's muscle 5 of the periphery frame as lead frame 2 by connector 32
Connect.
The 2nd connecting lead wire 43 being connected with the heat sink 4 of the opposing party is carried out even towards even muscle 6 by outside lead 41
Connect.It addition, company's muscle 5 phase that the heat sink 4 of the opposing party is by connector 42 with the periphery frame as lead frame 2
Connect.
Outside lead 7 configures on the 1st direction side by side along the end of the heat sink 3 of a side.Such as, divide with heat sink
From multiple outside leads 7 be connected with even muscle 6.
Such as, lead frame 2 is to utilize the materials such as copper coin that thermal conductivity is higher to be formed by punch process etc..
The manufacture method of semiconductor device 11 is illustrated.
As it is shown in figure 1, the upper surface at the heat sink 3 of a side of semiconductor device 11 carries semiconductor chip 1.
Upper surface at the heat sink 4 of the opposing party carries semiconductor chip 2.Such as, it is equipped on the heat sink 3 of a side
Semiconductor chip 1 is control IC chip, and the semiconductor chip 2 being equipped on the heat sink 4 of the opposing party is power
Semiconductor chip.At this moment, the grafting materials such as solder are used to carry out engaging (not shown).
Afterwards, use lead wire connecting apparatus, by wire rod 8 from the electrode of each semiconductor chip upper surface dissipating to a side
1st connecting lead wire 33 of hot plate 3, the semiconductor chip electrode of the opposing party and outside lead 7 carry out wiring and enter
Row electrical connection.
Such as, wire rod 8 is the materials such as gold or aluminum fine rule.Alternatively, it is also possible to be the use of the clamp leads of copper coin etc..
The heat sink 3 of a side of lead frame 2, the heat sink 4 of the opposing party, semiconductor chip is covered with outer containment body 9
1, the outside lead 7 of semiconductor chip 2, wire rod 8 and lead frame 2.Such as, molding die is used to pass through
Epoxies insulating resin is shaped.
Outside lead 7,31,41 extends and protrudes from the outside of outer containment body.
Wherein, eliminate in FIG and be positioned at the diagram of each outside lead below even muscle 6.
After the molding of outer containment body 9, by cutting off or the mode such as drawing removes company's muscle 5 and even of frame as lead frame 2
Junctor 32,42.Further, the company's of cut-out muscle 6 so that outside lead 7,31,41 is independent of one another.Thus, outside becoming
Portion's lead-in wire 7,31,41 protrudes from the form of the semiconductor device of the SIP type of outer containment body 9.
When carrying multiple semiconductor chip, if the configuration of semiconductor chip is set to left and right directions, then transverse width
Upper restricted, it is impossible to carry to realize the semiconductor chip that height exports and area is bigger.Accordingly, as lead frame
Shape, heat sink is configured along the 1st direction (above-below direction).
That is, in the case of SIP type encapsulates, it is that outside lead is inserted on printed base plate the hole (hole) arranged
In and carry out direction when welding etc. is installed.
It addition, connecting lead wire upwardly extends and is configured in respectively the side of heat sink the 2nd side respectively and is in relatively
Position.That is, make heat sink become and combined, by L-shaped shape and inverted L-shaped shape, the structure obtained.
Thereby, it is possible to guarantee space in the direction of the width, therefore, it is possible to carry area on the whole width of heat sink
Bigger semiconductor chip.
It addition, in the case of multiple semiconductor chips, it is possible to configure along the vertical direction.
Thereby, it is possible to realize inhibiting the semiconductor device of the high reliability of the increase of encapsulation transverse width.
When carrying power component and controlling element and each electrode controlling element is arranged into the end of element, it is possible to contracting
Short interelement distance, it is also possible to shorten the winding of wire rod, therefore, it is possible to make the bonding length optimization that goes between.
As above describe for implementing mode of the present utility model, it is apparent that those skilled in the art can be according to above-mentioned public affairs
The content opened realizes multiple alternative embodiment and embodiment.
In the configuration of Fig. 1, it is also possible to be the heterochiral knot in position making the 1st connecting lead wire and the 2nd connecting lead wire
Structure.It addition, the number of the arrangement of outside lead can arbitrarily set.Effect now is identical.
The 1st connecting lead wire being connected with the heat sink of a side and the be connected with the heat sink of the opposing party the 2nd is connected and draws
Line is configured in the heat sink of the opposing party and the side of the heat sink of a side respectively, and upwardly extends the 2nd side.Therefore,
If the 1st connecting lead wire and the 2nd connecting lead wire used as outside lead, then can increase the arrangement of outside lead
Quantity is without the lateral dimension increasing outer containment body.
If the 1st connecting lead wire and the 2nd connecting lead wire used as the connector connect to even muscle, then it is prevented from dissipating
The bending of hot plate, it is possible to increase the reliability of semiconductor device.
It is known that semiconductor device is the use of repeated arrangement in the orientation of outside lead multiple heat sink
The lead frame of strip be made.A pair even muscle it is configured with, by outside lead at the two ends of this lead frame
It is connected to this with multiple heat sinks connect on muscle.So, it is therefore prevented that outside lead and the bending of heat sink, it is possible to maintain and draw
The flatness of wire frame, it is possible to stably carry out the production of semiconductor device.
In the present embodiment, it is also possible to the 1st connecting lead wire and the 2nd connecting lead wire as connection heat sink and are connected muscle
Connector use.
When reducing the width of the 1st connecting lead wire 33, as it is shown on figure 3, protuberance can be arranged also in the front end extended
Connector is set.Thereby, it is possible to make the narrower intervals of connector, increase the chip carrying width of heat sink further,
The design freedom of chip area and lead frame can be increased.
The semiconductor chip being equipped on heat sink can be to be equipped with control element and the combination of diode.
Claims (2)
1. a semiconductor device, it is characterised in that
This semiconductor device has:
The multiple heat sinks configured separated from each other；
Multiple outside leads；
It is equipped on the semiconductor chip on described heat sink；And
Outer containment body, described heat sink, described outside lead and described semiconductor chip seal by it,
Described outside lead configures on the 1st direction side by side along the end of the described heat sink of a side, and a side's is described
The described heat sink of heat sink and the opposing party configures, side by side with the institute of a side on the 2nd direction intersected with the 1st direction
The 1st connecting lead wire and the 2nd connecting lead wire being connected with the described heat sink of the opposing party of stating heat sink connection are joined respectively
It is placed in the side of the described heat sink of the opposing party and the side of the described heat sink of a side and upwardly extends the 2nd side.
Semiconductor device the most according to claim 1, it is characterised in that
Described 1st connecting lead wire and described 2nd connecting lead wire are formed as the institute of the described heat sink than a side and the opposing party
The width stating heat sink is little.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016-038334 | 2016-02-29 | ||
| JP2016038334A JP2017157648A (en) | 2016-02-29 | 2016-02-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205488099U true CN205488099U (en) | 2016-08-17 |
Family
ID=56647895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620256676.1U Active CN205488099U (en) | 2016-02-29 | 2016-03-30 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2017157648A (en) |
| CN (1) | CN205488099U (en) |
-
2016
- 2016-02-29 JP JP2016038334A patent/JP2017157648A/en active Pending
- 2016-03-30 CN CN201620256676.1U patent/CN205488099U/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017157648A (en) | 2017-09-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |