CN205385483U - Onu terminal equipment - Google Patents
Onu terminal equipment Download PDFInfo
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- CN205385483U CN205385483U CN201620086611.7U CN201620086611U CN205385483U CN 205385483 U CN205385483 U CN 205385483U CN 201620086611 U CN201620086611 U CN 201620086611U CN 205385483 U CN205385483 U CN 205385483U
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Abstract
The utility model discloses a ONU terminal equipment, this ONU terminal equipment include the host processing ware, are used for the electric interface module of connection client equipment in order to realize the communication of host processing ware and customer end equipment to and be used for connection source end equipment with the smooth interface module of realization host processing ware with the communication of source end equipment, light interface module is the smooth transceiver module based on the BOSA form, the electricity interface module with light interface module all with the host processing ware is connected. The utility model discloses can reduce ONU terminal equipment's cost to improve the uniformity of ONU terminal equipment optical parameter.
Description
Technical field
This utility model relates to transmission equipment technical field, particularly to a kind of ONU terminal unit.
Background technology
PON (PassiveOpticalNetwork, EPON) it is the EPON of a kind of point-to-multipoint structure, GPON (Gigabit-CapablePON, gigabit passive optical network) technology is based on the latest generation broadband passive light Integrated access standard of ITU-TG.984.x standard.The same with all PON system, GPON is also by OLT (OpticalLineTerminal, optical line terminal), ONU (OpticalNetworkUnit, optical network unit) and ODN (OpticalDistributionNetwork, Optical Distribution Network, i.e. light orchestration) composition.Wherein, ONU is terminal (user side) equipment of GPON system, and it can be connected with the OLT of source by ODN, completes the transmission of user data, it is connected by the PON mouth of ODN and OLT with PON mouth (i.e. light mouth), and the information to complete OLT and ONU is transmitted and data exchange；Communicating with client device (such as PC) with the electric mouth of 10/100/1000M, the information completing ONU and client device exchanges.The effect of ONU is to provide the interface between network side and user side or local switch for optical access network, and communicates with the OLT of source through ODN, and the relation of OLT and ONU is master-slave communication relation.
Current ONU is polymorphic ONU and deposits, and provides the user access way flexibly.But ONU in the market uses PON optical module in PON interface, owing to using PON optical module, causing that the cost of ONU is high, the optical parameter concordance of optical module is also poor.
Utility model content
Main purpose of the present utility model is to propose a kind of ONU terminal unit, it is intended to reduces the cost of ONU terminal unit, and improves the concordance of optical parameter.
For achieving the above object, the ONU terminal unit that the utility model proposes includes primary processor, for connecting client device to realize the electrical interface module of primary processor and client device communications, and for connecting source equipment to realize the optical interface module that primary processor communicates with source equipment；Described optical interface module is the optical transceiver module based on BOSA (Bi-DirectionalOpticalSub-Assembly, light emission receiving unit) form, and described electrical interface module and described optical interface module are all connected with described primary processor.
Preferably, described optical interface module includes double-closed-loop control combined chip and light transceiver interface, and described primary processor includes a gateway chip；
The oppisite phase data input pin that receives of described double-closed-loop control combined chip is connected with the data positive pole pin of described smooth transceiver interface, and the reception in-phase data input pin of described double-closed-loop control combined chip is connected with the data negative pin of described smooth transceiver interface；The Laser Modulation in-phase current pin of described double-closed-loop control combined chip and laser bias current compensation pin are all connected with the current detecting positive pole pin/photodiode negative pin of described smooth transceiver interface, the Laser Modulation negative-phase sequence curent pin of described double-closed-loop control combined chip and laser bias current pin are all connected with the current detecting negative pin of described smooth transceiver interface, and the monitor photo-diode input pin of described double-closed-loop control combined chip is connected with the photodiode positive pole pin of described smooth transceiver interface；
The oppisite phase data output pin that receives of described double-closed-loop control combined chip is connected with the reception oppisite phase data input pin of described gateway chip, and the reception in-phase data output pin of described double-closed-loop control combined chip is connected with the reception in-phase data input pin of described gateway chip；The transmission data high-speed reversed input pin of described double-closed-loop control combined chip sends pin with the oppisite phase data of described gateway chip and is connected, and the transmission data high-speed homophase input pin of described double-closed-loop control combined chip sends pin with the in-phase data of described gateway chip and is connected；The signal detection of described double-closed-loop control combined chip/dropout State-output pin, enable receiver sleep pattern pin, transmitter failure State-output pin is corresponding with a general input/output port of described gateway chip respectively to be connected, the transmitter signal detection output pin of described double-closed-loop control combined chip detects input pin with the transmitter signal of described gateway chip and is connected, the signal detection of described double-closed-loop control combined chip/dropout State-output pin is also connected with the dropout state input pin of described gateway chip, the burst of described double-closed-loop control combined chip enables homophase input pin and is connected with the burst enable homophase output pin of described gateway chip；The serial data interface of described double-closed-loop control combined chip connects pin and is connected pin connection with the serial data interface of described gateway chip, and the serial clock interface of described double-closed-loop control combined chip connects pin and is connected pin connection with the serial clock interface of described gateway chip.
Preferably, described electrical interface module is RJ45 interface.
Preferably, ONU terminal unit also includes the DC/DC power supply for providing multiple power sources, and described DC/DC power supply is connected with described primary processor.
Preferably, ONU terminal unit also includes the memory element of the systems soft ware for storing ONU terminal unit, and described memory element is connected with described primary processor.
Preferably, described memory element is FLASH memory.
Preferably, ONU terminal unit also includes the buffer unit of the packet for buffer memory ONU terminal unit, and described buffer unit is connected with described primary processor.
Preferably, described buffer unit is DDR memory.
Preferably, ONU terminal unit also includes for receiving and dispatching the rs 232 serial interface signal serial communication interface with upgrading and the systems soft ware of management ONU terminal unit, and described serial communication interface is connected with described primary processor.
Preferably, ONU terminal unit also includes state indicating device, and described state indicating device is connected with described primary processor.
Technical solutions of the utility model are by adopting ONU terminal unit, connect client device by electrical interface module and realize the communication of ONU terminal unit and client device, connect source equipment by optical interface module and realize the communication of ONU terminal unit and source equipment, and optical interface module is the optical transceiver module based on BOSA form, thus relative to existing PON optical module, reduce the cost of ONU terminal unit, and the optical parameter concordance of optical transceiver module is good.
Accompanying drawing explanation
In order to be illustrated more clearly that this utility model embodiment or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to the structure according to these accompanying drawings obtains other accompanying drawing.
Fig. 1 is the theory structure schematic diagram of this utility model ONU terminal unit one embodiment；
Fig. 2 is the electrical block diagram that in Fig. 1, optical interface module is connected with primary processor.
Drawing reference numeral illustrates:
The realization of this utility model purpose, functional characteristics and advantage will in conjunction with the embodiments, are described further with reference to accompanying drawing.
Detailed description of the invention
Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present utility model, rather than whole embodiments.Based on the embodiment in this utility model, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of this utility model protection.
The utility model proposes a kind of ONU terminal unit.
With reference to the theory structure schematic diagram that Fig. 1, Fig. 1 are this utility model ONU terminal unit one embodiment.
In this utility model embodiment, as it is shown in figure 1, ONU terminal unit of the present utility model includes primary processor 10, electrical interface module 20 and optical interface module 30；Wherein, described electrical interface module 20 and described optical interface module 30 are all connected with described primary processor 10, electrical interface module 20 is used for connecting client device to realize primary processor 10 and client device communications, optical interface module 30 is used for connecting source equipment to realize primary processor 10 and source equipment communication, and described optical interface module 30 is the optical transceiver module based on BOSA form.
In ONU terminal unit of the present utility model, when being connected to client device (such as PC) by electrical interface module 20, primary processor 10 in ONU terminal unit can with client device communications, it is achieved the communication of ONU terminal unit and client device；When being connected to source equipment by optical interface module 30, namely during passive light line terminal, primary processor 10 in ONU terminal unit can communicate with source equipment, it is achieved the communication of ONU terminal unit and client device, thus realizing the communication of client device and source equipment.Owing in ONU terminal unit, optical interface module 30 is the optical transceiver module based on BOSA form, thus the cost of ONU terminal unit of the present utility model is lower than existing PON optical module, and the optical parameter concordance of optical transceiver module is good.
Specifically, the electrical interface module 20 in ONU terminal unit is RJ45 interface, and RJ45 interface is network interface by ONU terminal unit, realizes the communication of ONU terminal unit and client device by being connected to client device.
It is the electrical block diagram that in Fig. 1, optical interface module 30 is connected with primary processor 10 in conjunction with reference Fig. 2, Fig. 2.
Optical interface module 30 in ONU terminal unit includes double-closed-loop control combined chip U1 and light transceiver interface J1, primary processor 10 in ONU terminal unit includes gateway chip U2, this gateway chip U2 supports EPON (EthernetPON, Ethernet passive optical network) and GPON standard, the present embodiment is preferably, gateway chip U2 is ZX279110A1 chip, and double-closed-loop control combined chip U1 is GN25L95 chip.
As shown in Figure 2, the data positive pole pin DATA+ receiving oppisite phase data input pin RXIN-and described smooth transceiver interface J1 of described double-closed-loop control combined chip U1 is connected, and the data negative pin DATA-of the reception in-phase data input pin RXIN+ and described smooth transceiver interface J1 of described double-closed-loop control combined chip U1 is connected；The Laser Modulation in-phase current pin LASER+ and laser bias current compensation pin BIAS-of described double-closed-loop control combined chip U1 is all connected with the current detecting positive pole pin of described smooth transceiver interface J1/photodiode negative pin LD+/MPD-, the Laser Modulation negative-phase sequence curent pin LASER-of described double-closed-loop control combined chip U1 and laser bias current pin BIAS+ is all connected with the current detecting negative pin LD-of described smooth transceiver interface J1, and the photodiode positive pole pin MPD+ of the monitor photo-diode input pin MPD of described double-closed-loop control combined chip U1 and described smooth transceiver interface J1 is connected.
The reception oppisite phase data input pin X_GEPON_RXM_L0 receiving oppisite phase data output pin RXOUT-and described gateway chip U2 of described double-closed-loop control combined chip U1 is connected, and the reception in-phase data input pin X_GEPON_RXP_L0 of the reception in-phase data output pin RXOUT+ and described gateway chip U2 of described double-closed-loop control combined chip U1 is connected；The oppisite phase data of transmission data high-speed reversed input pin TXIN-and the described gateway chip U2 of described double-closed-loop control combined chip U1 sends pin X_GEPON_TXM_L0 and is connected, and the in-phase data of transmission data high-speed homophase input pin TXIN+ and the described gateway chip U2 of described double-closed-loop control combined chip U1 sends pin (X_GEPON_TXP_L0) and is connected；The signal detection of described double-closed-loop control combined chip U1/dropout State-output pin SD/LOS, enable receiver sleep pattern pin RX_SLEEP, transmitter failure State-output pin TX_FAULT is corresponding with a general input/output port of described gateway chip U2 respectively to be connected, such as, in Fig. 2, signal detection/dropout State-output pin SD/LOS is connected with general input/output port GPIO1, enable receiver sleep pattern pin RX_SLEEP to be connected with general input/output port GPIO2, transmitter failure State-output pin TX_FAULT is connected with general input/output port GPIO3；The transmitter signal detection input pin X_TX_SD of transmitter signal detection output pin TX_SD and the described gateway chip U2 of described double-closed-loop control combined chip U1 is connected, the signal detection of described double-closed-loop control combined chip U1/dropout State-output pin SD/LOS is also connected with the dropout state input pin X_RX_LOS of described gateway chip U2, and the burst of described double-closed-loop control combined chip U1 enables the burst enable homophase output pin X_PON_BEN of homophase input pin BEN+ and described gateway chip U2 and is connected；The serial data interface of described double-closed-loop control combined chip U1 connects the serial data interface of pin SDA and described gateway chip U2 and is connected pin X_I2C_SDA connection, and the serial clock interface of described double-closed-loop control combined chip U1 connects the serial clock interface of pin SCL and described gateway chip U2 and is connected pin X_I2C_SCL connection.
In ONU terminal unit of the present utility model, gateway chip U2 supports EPON and GPON standard, internet is connected and is incorporated into passive point-to-multipoint fiber optic network, and have 802.3z gigabit Ethernet MAC (MediaAccessControler, media access controller) as Central Office network interface, it is provided that a 10/100/1000M self adaptation electrical interface is to meet the needs of different users.Meanwhile, using the double-closed-loop control combined chip U1 driving chip as optical interface module 30, the BOSA of optical interface module 30 (i.e. optical transceiver module) is coordinated to realize the PON interface function of ONU terminal unit.
Further, as it is shown in figure 1, ONU terminal unit also includes the DC/DC power supply 40 for providing multiple power sources, described DC/DC power supply 40 is connected with described primary processor 10.The multiple power sources needed for ONU terminal unit can be provided by DC/DC power supply 40, for instance 12V Power convert is 1.1V, 1.8V, 3.3V etc. by DC/DC power supply 40, the power supplys such as 1.1V, 1.8V, 3.3V are provided to the load of ONU terminal unit.This utility model coordinates the BOSA of optical interface module 30 (i.e. optical transceiver module) to realize PON interface transmitting-receiving sensitivity automatic regulation function by DC/DC power supply 40.
Further, as it is shown in figure 1, ONU terminal unit also includes the memory element 50 of the systems soft ware for storing ONU terminal unit, described memory element 50 is connected with described primary processor 10.Specifically, described memory element 50 is FLASH memory.ONU terminal unit stores its systems soft ware by FLASH memory so that can start and normal operation after the energising of ONU terminal unit.
Further, as it is shown in figure 1, ONU terminal unit also includes the buffer unit 60 of the packet for buffer memory ONU terminal unit, described buffer unit 60 is connected with described primary processor 10.Specifically, described buffer unit 60 is DDR memory.ONU terminal unit is when communicating with client device or source equipment, and ONU terminal unit temporarily deposits received data and data to be sent by DDR memory.
Further, as it is shown in figure 1, ONU terminal unit also includes for receiving and dispatching the rs 232 serial interface signal serial communication interface 70 with upgrading and the systems soft ware of management ONU terminal unit, described serial communication interface 70 is connected with described primary processor 10.ONU terminal unit can pass through serial communication interface 70 (such as UART interface) and connect the equipment such as PC, systems soft ware by device downloads ONU terminal units such as PCs, the systems soft ware of ONU terminal unit is updated, upgrades, the systems soft ware of ONU terminal unit is managed, consequently facilitating the systems soft ware of online upgrading and management ONU terminal unit, it is user-friendly to.
Further, as shown in Figure 1, ONU terminal unit also includes state indicating device 80, described state indicating device 80 is connected with described primary processor 10, and this state indicating device 80 includes but not limited to one or more combinations in power supply indicator, alarm indicator, network state display lamp, optical signal status indicator lamp and power down display lamp.
The foregoing is only preferred embodiment of the present utility model; not thereby the scope of the claims of the present utility model is limited; every under inventive concept of the present utility model; utilize the equivalent structure transformation that this utility model description and accompanying drawing content are made, or directly/be indirectly used in other relevant technical fields and be included in scope of patent protection of the present utility model.
Claims (10)
1. an ONU terminal unit, it is characterized in that, including primary processor, for connecting client device to realize the electrical interface module of primary processor and client device communications, and for connecting source equipment to realize the optical interface module that primary processor communicates with source equipment；Described optical interface module is the optical transceiver module based on BOSA form, and described electrical interface module and described optical interface module are all connected with described primary processor.
2. ONU terminal unit as claimed in claim 1, it is characterised in that described optical interface module includes double-closed-loop control combined chip and light transceiver interface, and described primary processor includes a gateway chip；
The oppisite phase data input pin that receives of described double-closed-loop control combined chip is connected with the data positive pole pin of described smooth transceiver interface, and the reception in-phase data input pin of described double-closed-loop control combined chip is connected with the data negative pin of described smooth transceiver interface；The Laser Modulation in-phase current pin of described double-closed-loop control combined chip and laser bias current compensation pin are all connected with the current detecting positive pole pin/photodiode negative pin of described smooth transceiver interface, the Laser Modulation negative-phase sequence curent pin of described double-closed-loop control combined chip and laser bias current pin are all connected with the current detecting negative pin of described smooth transceiver interface, and the monitor photo-diode input pin of described double-closed-loop control combined chip is connected with the photodiode positive pole pin of described smooth transceiver interface；
The oppisite phase data output pin that receives of described double-closed-loop control combined chip is connected with the reception oppisite phase data input pin of described gateway chip, and the reception in-phase data output pin of described double-closed-loop control combined chip is connected with the reception in-phase data input pin of described gateway chip；The transmission data high-speed reversed input pin of described double-closed-loop control combined chip sends pin with the oppisite phase data of described gateway chip and is connected, and the transmission data high-speed homophase input pin of described double-closed-loop control combined chip sends pin with the in-phase data of described gateway chip and is connected；The signal detection of described double-closed-loop control combined chip/dropout State-output pin, enable receiver sleep pattern pin, transmitter failure State-output pin is corresponding with a general input/output port of described gateway chip respectively to be connected, the transmitter signal detection output pin of described double-closed-loop control combined chip detects input pin with the transmitter signal of described gateway chip and is connected, the signal detection of described double-closed-loop control combined chip/dropout State-output pin is also connected with the dropout state input pin of described gateway chip, the burst of described double-closed-loop control combined chip enables homophase input pin and is connected with the burst enable homophase output pin of described gateway chip；The serial data interface of described double-closed-loop control combined chip connects pin and is connected pin connection with the serial data interface of described gateway chip, and the serial clock interface of described double-closed-loop control combined chip connects pin and is connected pin connection with the serial clock interface of described gateway chip.
3. ONU terminal unit as claimed in claim 1, it is characterised in that described electrical interface module is RJ45 interface.
4. ONU terminal unit as claimed any one in claims 1 to 3, it is characterised in that also including the DC/DC power supply for providing multiple power sources, described DC/DC power supply is connected with described primary processor.
5. as claimed any one in claims 1 to 3 ONU terminal unit, it is characterised in that also including the memory element of systems soft ware for storing ONU terminal unit, described memory element is connected with described primary processor.
6. ONU terminal unit as claimed in claim 5, it is characterised in that described memory element is FLASH memory.
7. as claimed any one in claims 1 to 3 ONU terminal unit, it is characterised in that also including the buffer unit of packet for buffer memory ONU terminal unit, described buffer unit is connected with described primary processor.
8. ONU terminal unit as claimed in claim 7, it is characterised in that described buffer unit is DDR memory.
9. ONU terminal unit as claimed any one in claims 1 to 3, it is characterised in that also including for receiving and dispatching the rs 232 serial interface signal serial communication interface with upgrading and the systems soft ware of management ONU terminal unit, described serial communication interface is connected with described primary processor.
10. ONU terminal unit as claimed any one in claims 1 to 3, it is characterised in that also including state indicating device, described state indicating device is connected with described primary processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620086611.7U CN205385483U (en) | 2016-01-28 | 2016-01-28 | Onu terminal equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620086611.7U CN205385483U (en) | 2016-01-28 | 2016-01-28 | Onu terminal equipment |
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| Publication Number | Publication Date |
|---|---|
| CN205385483U true CN205385483U (en) | 2016-07-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620086611.7U Expired - Fee Related CN205385483U (en) | 2016-01-28 | 2016-01-28 | Onu terminal equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109068292A (en) * | 2018-08-07 | 2018-12-21 | 上海博泰悦臻电子设备制造有限公司 | Car-mounted terminal and its intelligent gateway |
-
2016
- 2016-01-28 CN CN201620086611.7U patent/CN205385483U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109068292A (en) * | 2018-08-07 | 2018-12-21 | 上海博泰悦臻电子设备制造有限公司 | Car-mounted terminal and its intelligent gateway |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160713 Termination date: 20190128 |
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| CF01 | Termination of patent right due to non-payment of annual fee |