CN205355054U - Display thin film transistor structure and display - Google Patents
Display thin film transistor structure and display Download PDFInfo
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- CN205355054U CN205355054U CN201620104895.8U CN201620104895U CN205355054U CN 205355054 U CN205355054 U CN 205355054U CN 201620104895 U CN201620104895 U CN 201620104895U CN 205355054 U CN205355054 U CN 205355054U
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Abstract
The utility model discloses a display thin film transistor structure and display, this display thin film transistor structure is including forming the thin film transistor on the base plate, the 2nd thin film transistor, the source electrode lead wire, the drain lead, the grid is had a common boundary and the dielectric layer, this source electrode lead wire links to each other with a thin film transistor's source electrode, this drain lead links to each other with a thin film transistor's drain electrode, it forms the breach to break off between this source electrode lead wire and the 2nd thin film transistor's the source electrode or between this drain lead and the 2nd thin film transistor's the drain electrode, this grid is had a common boundary corresponding to this breach setting. The display, including a plurality of pixels that are array arrangement, every pixel is equipped with foretell display thin film transistor structure. It is spare through parallelly connected one or more thin film transistor conduct on the thin film transistor in original pixel circuit, when the appearance of original thin film transistor is bad, sees through the restoration method and launch spare thin film transistor, can thoroughly restore bad point, change and can only become the dim spot with the bright spot at present, and the dim spot can't prosthetic current situation.
Description
Technical field
This utility model relates to Display Technique field, especially relates to a kind of display membrane transistor arrangement and has the display of this thin-film transistor structure.
Background technology
OLED is to utilize Organic Light Emitting Diode (OrganicLight-EmittingDiode, OLED) display screen made, due to its have from main light emission, contrast is high, thickness is thin, response speed is fast, power is low, can be used for flexible panel and use a series of advantages such as temperature range is wide, low-voltage direct drives, wide, the various colors in visual angle, compared with liquid crystal display, OLED it is not necessary to backlight, its response speed is up to 1000 times of liquid crystal display, and manufacturing cost is but lower than the liquid crystal display of equal resolution.Therefore OLED is expected to become main flow flat panel display of future generation, is one of the maximum technology that receives publicity in current flat panel display.
The basic structure of OLED screen body is: include a glass substrate, it is formed with the organic light-emitting units being made up of each layers such as image element circuit, anode, organic luminous layer, negative electrodes on the glass substrate, and with cap, organic light-emitting units is encapsulated between glass substrate and cap, anode, negative electrode are drawn by going between in position, non-light-emitting area, bind with integrated circuit (IC) or flexible PCB (FPC).Wherein, image element circuit mainly includes thin film transistor (TFT) (TFT) and the circuit (scanning line, data wire etc.) being connected with TFT.The Main Function of TFT is to drive the pixel on display, and each pixel is at least driven by a TFT, therefore includes the array structure being made up of multiple TFT in the display.
In flat faced display manufacture process, due to some unpredictable factors, for instance little particle dust or process deviation usually can cause bad generation; particularly when defect occurs when TFT part; often causing point defect, the bad point phenomenon namely generally said, so-called bad point refers to defective pixel.Point defect restorative procedure conventional at present is, by laser, TFT is broken into short circuit or open circuit, thus bright spot is repaired into dim spot, and dim spot will be unable to repair, and will cause that when dim spot exceedes some display defective products occurs.
Utility model content
The purpose of this utility model is in that to provide a kind of display membrane transistor arrangement, and it can thoroughly repair bad point, changes and bright spot can only become dim spot at present, and the present situation that dim spot cannot be repaired.
This utility model provides a kind of display membrane transistor arrangement, including forming the first film transistor on substrate, second thin film transistor (TFT), source lead, drain lead, grid is had a common boundary and dielectric layer, each thin film transistor (TFT) includes semiconductor layer, grid, source electrode and drain electrode, this grid is had a common boundary, the grid of this first film transistor and the grid of this second thin film transistor (TFT) are arranged in the first metal layer, this source lead, this drain lead, the source electrode of the source electrode of this first film transistor and drain electrode and this second thin film transistor (TFT) and drain electrode are arranged in the second metal level, this source lead is connected with the source electrode of this first film transistor, this drain lead is connected with the drain electrode of this first film transistor, between the source electrode of this source lead and this second thin film transistor (TFT) or the separated formation breach of the drain electrode of this drain lead and this second thin film transistor (TFT), this grid is had a common boundary and is arranged corresponding to this breach, this dielectric layer is arranged between this first metal layer and this second metal level.
Further, this breach of separated formation of the source electrode of this source lead and this second thin film transistor (TFT), this grid is had a common boundary between this source lead and this grid is had a common boundary and is respectively provided with overlay region between the source electrode of this second thin film transistor (TFT), and this drain lead is connected with the drain electrode of this second thin film transistor (TFT).
Further, this breach of separated formation of the drain electrode of this drain lead and this second thin film transistor (TFT), this grid is had a common boundary between this drain lead and this grid is had a common boundary and is respectively provided with overlay region between the drain electrode of this second thin film transistor (TFT), and this source lead is connected with the source electrode of this second thin film transistor (TFT).
Further, this display membrane transistor arrangement also includes scanning line, data wire and pixel electrode, the grid of this first film transistor and the grid of this second thin film transistor (TFT) are electrically connected with this scanning line, this source lead is electrically connected with this data wire, and this drain lead is electrically connected with this pixel electrode.
Further, the semiconductor layer of the semiconductor layer of this first film transistor and this second thin film transistor (TFT) is formed on the substrate, the semiconductor layer overlying lid of the semiconductor layer of this first film transistor and this second thin film transistor (TFT) is formed with insulating barrier, this grid is had a common boundary, the grid of this first film transistor and the grid of this second thin film transistor (TFT) are formed on which insulating layer, this dielectric layer is formed on which insulating layer, this dielectric layer covers this grid and has a common boundary, the grid of this first film transistor and the grid of this second thin film transistor (TFT), this source lead, this drain lead, the source electrode of the source electrode of this first film transistor and drain electrode and this second thin film transistor (TFT) and drain electrode are formed on this dielectric layer.
Further, this substrate being also formed with cushion, the semiconductor layer of the semiconductor layer of this first film transistor and this second thin film transistor (TFT) is formed on this cushion.
Further, this dielectric layer and this insulating barrier are provided with multiple source contact openings and multiple drain contact hole, the source electrode of this first film transistor is electrically connected by the semiconductor layer of one of them source contact openings with this first film transistor, the source electrode of this second thin film transistor (TFT) is electrically connected by the semiconductor layer of another source contact openings with this second thin film transistor (TFT), the drain electrode of this first film transistor is electrically connected by the semiconductor layer of one of them drain contact hole with this first film transistor, the drain electrode of this second thin film transistor (TFT) is electrically connected by the semiconductor layer of another drain contact hole with this second thin film transistor (TFT).
Further, this dielectric layer is also formed with planarization layer, this planarization layer covers this source lead, this drain lead, the source electrode of this first film transistor and the source electrode of drain electrode and this second thin film transistor (TFT) and drain electrode, this planarization layer is provided with pixel electrode contact hole, this pixel electrode is formed on this planarization layer, and this pixel electrode is electrically connected with this drain lead by this pixel electrode contact hole.
Further, this grid is had a common boundary, the grid of this first film transistor and the grid of this second thin film transistor (TFT) are formed on the substrate, this dielectric layer is formed on the substrate and covers this grid to be had a common boundary, the grid of this first film transistor and the grid of this second thin film transistor (TFT), this source lead, this drain lead, the source electrode of the source electrode of this first film transistor and drain electrode and this second thin film transistor (TFT) and drain electrode are formed on this dielectric layer, this dielectric layer is formed with insulating barrier, this insulating barrier covers this source lead, this drain lead, the source electrode of the source electrode of this first film transistor and drain electrode and this second thin film transistor (TFT) and drain electrode.
Further, the semiconductor layer of the semiconductor layer of this first film transistor and this second thin film transistor (TFT) is formed on this dielectric layer, the source electrode of this first film transistor is spaced from each other with drain electrode and all directly contacts with the semiconductor layer of this first film transistor, and the source electrode of this second thin film transistor (TFT) is spaced from each other with drain electrode and all directly contacts with the semiconductor layer of this second thin film transistor (TFT).
Further, this pixel electrode is formed on which insulating layer, is provided with pixel electrode contact hole in this insulating barrier, and this pixel electrode is electrically connected with this drain lead by this pixel electrode contact hole.
This utility model also provides for a kind of display, and including the multiple pixels being arranged in array, each pixel is provided with display membrane transistor arrangement as above.
Further, this display is OLED display or liquid crystal display.
The display membrane transistor arrangement that this utility model provides, by one or more thin film transistor (TFT)s in parallel on the thin film transistor (TFT) in original image element circuit as backup, when original thin film transistor (TFT) occurs bad, backup thin film transistor (TFT) is enabled through restorative procedure, can thoroughly repair bad point, change and bright spot can only be become dim spot at present, and the present situation that dim spot cannot be repaired.
Accompanying drawing explanation
Fig. 1 is the floor map of display membrane transistor arrangement in this utility model first embodiment.
Fig. 2 a is the cut-away diagram in Fig. 1 along I-I line.
Fig. 2 b is the cut-away diagram in Fig. 1 along II-II line.
Fig. 2 c is the cut-away diagram in Fig. 1 along III-III line.
Fig. 3 is the floor map forming two semiconductor layers in this utility model first embodiment.
Fig. 4 is the floor map that in this utility model first embodiment, formation grid and grid are had a common boundary.
Fig. 5 is the floor map forming source drain contact hole in this utility model first embodiment.
Fig. 6 is the floor map forming source/drain and source/drain lead-in wire in this utility model first embodiment.
Fig. 7 is the floor map forming pixel electrode contact hole in this utility model first embodiment.
Fig. 8 is the floor map of display membrane transistor arrangement in this utility model the second embodiment.
Fig. 9 is the floor map of display membrane transistor arrangement in this utility model the 3rd embodiment.
Figure 10 a is the cut-away diagram in Fig. 9 along IV-IV line.
Figure 10 b is the cut-away diagram in Fig. 9 along V-V line.
Figure 10 c is the cut-away diagram in Fig. 9 along line VI--VI.
Detailed description of the invention
For further setting forth that this utility model is reach technical approach and effect that predetermined utility model purpose is taked, below in conjunction with drawings and Examples, to detailed description of the invention of the present utility model, structure, feature and effect thereof, describe in detail as after.
Fig. 1 is the floor map of display membrane transistor arrangement in this utility model first embodiment, and Fig. 2 a is the cut-away diagram in Fig. 1 along I-I line, and Fig. 2 b is the cut-away diagram in Fig. 1 along II-II line, and Fig. 2 c is the cut-away diagram in Fig. 1 along III-III line.Please joining Fig. 1, Fig. 2 a to Fig. 2 b, the display membrane transistor arrangement that the present embodiment provides includes being formed the first film transistor A on the substrate 10, the second thin film transistor (TFT) B, source lead 11, drain lead 12, grid have a common boundary 13 and dielectric layer 14.Each thin film transistor (TFT) A, B include semiconductor layer 21, grid 22, source electrode 23 and drain electrode 24.Grid has a common boundary 13, the grid 22 of the first film transistor A and the grid 22 of the second thin film transistor (TFT) B are arranged in the first metal layer.Source lead 11, drain lead 12, the source electrode 23 of the first film transistor A and source electrode 23 and the drain electrode 24 of drain electrode 24 and the second thin film transistor (TFT) B are arranged in the second metal level.Source lead 11 is connected with the source electrode 23 of the first film transistor A, and drain lead 12 is connected with the drain electrode 24 of the first film transistor A.The separated formation breach 30 of the source electrode 23 of source lead 11 and the second thin film transistor (TFT) B, grid is had a common boundary 13 and is arranged corresponding to this breach 30.Dielectric layer 14 is arranged between this first metal layer and this second metal level.
In the present embodiment, the separated formation breach 30 of the source electrode 23 of source lead 11 and the second thin film transistor (TFT) B, grid is had a common boundary 13 and is arranged corresponding to this breach 30, grid is had a common boundary between 13 and source lead 11 and grid have a common boundary 13 and second thin film transistor (TFT) B source electrode 23 between be respectively provided with overlay region, drain lead 12 is connected with the drain electrode 24 of the second thin film transistor (TFT) B, but this utility model is not limited to this.In this utility model the second embodiment, as shown in Figure 8, can also be, the separated formation breach 30 of the drain electrode 24 of drain lead 12 and the second thin film transistor (TFT) B, grid is had a common boundary 13 and is arranged corresponding to this breach 30, grid is had a common boundary between 13 and drain lead 12 and grid have a common boundary 13 and second thin film transistor (TFT) B drain electrode 24 between be respectively provided with overlay region, source lead 11 is connected with the source electrode 23 of the second thin film transistor (TFT) B.
As it is shown in figure 1, this display membrane transistor arrangement includes two thin film transistor (TFT)s A, B, under normal circumstances, the first film transistor A works, and the second thin film transistor (TFT) B is as standby thin film transistor (TFT), and the second thin film transistor (TFT) B is owing to existing breach 30 and open circuit.Formed at source lead 11 and source electrode 23 connecting place of the first film transistor A and standby interrupt district (in figure a region), have a common boundary 13 at grid and form standby connected region (in figure b region) with source electrode 23 overlay region of source lead 11 and the second thin film transistor (TFT) B.When the first film transistor A causes short circuit or other defect to lose efficacy because of defect, reparation means can be used, laser cutting function such as laser cutting machine, the a region that the source electrode 23 of source lead 11 with the first film transistor A is connected is interrupted, makes the source electrode 23 of source lead 11 and the first film transistor A disconnect；Use reparation means simultaneously, welding function such as laser cutting machine, weld in standby connected region, grid is had a common boundary 13 two ends and forms short circuit with the source electrode 23 of source lead 11 and the second thin film transistor (TFT) B in b region respectively, make to have a common boundary 13 by grid between source lead 11 and the source electrode 23 of the second thin film transistor (TFT) B to electrically connect, so that the first film transistor A open circuit, the second thin film transistor (TFT) B connection, realize enabling the second standby thin film transistor (TFT) B, therefore can thoroughly repair bad point.
This display membrane transistor arrangement also includes scanning line (not shown), data wire (not shown) and pixel electrode 15, the grid 22 of the first film transistor A and the grid 22 of the second thin film transistor (TFT) B electrically connect with this scanning line, source lead 11 electrically connects with this data wire, and drain lead 12 electrically connects with this pixel electrode 15.
As it is shown in figure 1, in the present embodiment, it is connected as a single entity by grid lead 25 between grid 22 and the grid 22 of the second thin film transistor (TFT) B of the first film transistor A.
In the present embodiment, the semiconductor layer 21 of the first film transistor A and the semiconductor layer 21 of the second thin film transistor (TFT) B are formed on the substrate 10.The semiconductor layer 21 of the first film transistor A and the semiconductor layer 21 overlying lid of the second thin film transistor (TFT) B are formed with insulating barrier 16.Grid has a common boundary 13, the grid 22 of the first film transistor A and the grid 22 of the second thin film transistor (TFT) B are formed on insulating barrier 16.Dielectric layer 14 is formed on insulating barrier 16, dielectric layer 14 cover grid have a common boundary 13, the grid 22 of the grid 22 of the first film transistor A and the second thin film transistor (TFT) B.Source lead 11, drain lead 12, the source electrode 23 of the first film transistor A and the source electrode 23 of drain electrode 24 and the second thin film transistor (TFT) B and drain electrode 24 formation are on dielectric layer 14.
Further, in the present embodiment, substrate 10 being also formed with cushion 17, the semiconductor layer 21 of the first film transistor A and the semiconductor layer 21 of the second thin film transistor (TFT) B are formed on cushion 17.
In the present embodiment, dielectric layer 14 and insulating barrier 16 are provided with multiple source contact openings 31 and multiple drain contact hole 32, the source electrode 23 of the first film transistor A is electrically connected by the semiconductor layer 21 of one of them source contact openings 31 with the first film transistor A, the source electrode 23 of the second thin film transistor (TFT) B is electrically connected by the semiconductor layer 21 of another source contact openings 31 and the second thin film transistor (TFT) B, the drain electrode 24 of the first film transistor A is electrically connected by the semiconductor layer 21 of one of them drain contact hole 32 with the first film transistor A, the drain electrode 24 of the second thin film transistor (TFT) B is electrically connected by the semiconductor layer 21 of another drain contact hole 32 and the second thin film transistor (TFT) B.
In the present embodiment, dielectric layer 14 is also formed with planarization layer 18, planarization layer 18 covers source lead 11, drain lead 12, the source electrode 23 of the first film transistor A and the source electrode 23 of drain electrode 24 and the second thin film transistor (TFT) B and drain electrode 24, is provided with pixel electrode contact hole 33 in planarization layer 18.Pixel electrode 15 is formed on planarization layer 18, and pixel electrode 15 is electrically connected with drain lead 12 by this pixel electrode contact hole 33.
Fig. 3 is the floor map forming two semiconductor layers in this utility model, as shown in Fig. 3, Fig. 2 a to Fig. 2 b, forms the semiconductor layer 21 of the first film transistor A and the semiconductor layer 21 of the second thin film transistor (TFT) B on the substrate 10.The semiconductor layer 21 of the first film transistor A and the semiconductor layer 21 of the second thin film transistor (TFT) B are spaced on the substrate 10.Substrate 10 can be glass or plastics.Semiconductor layer 21 can be non-crystalline silicon (a-Si), polysilicon (poly-Si) or metal-oxide such as IGZO, ITZO.Further, it is also possible to first form cushion 17 on the substrate 10, on cushion 17, the semiconductor layer 21 of the first film transistor A and the semiconductor layer 21 of the second thin film transistor (TFT) B are then formed.Cushion 17 can be silicon oxide layer (SiOx) or silicon nitride layer (SiNx) or other insulating film layers.
Fig. 4 is the floor map that in this utility model first embodiment, formation grid and grid are had a common boundary, as shown in Fig. 4, Fig. 2 a to Fig. 2 b, insulating barrier 16 is become with the semiconductor layer 21 overlying cap-shaped of the second thin film transistor (TFT) B at the semiconductor layer 21 of the first film transistor A, formation of deposits the first metal layer on insulating barrier 16, is patterned to form grid on insulating barrier 16 and have a common boundary 13, the grid 22 of the grid 22 of the first film transistor A and the second thin film transistor (TFT) B to this first metal layer.Grid is had a common boundary 13 and is arranged near the grid 22 of the second thin film transistor (TFT) B.The grid 22 of the first film transistor A and the grid 22 of the second thin film transistor (TFT) B connect as one.The first metal layer can adopt the metal or alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, it would however also be possible to employ the laminated film being made up of multiple layer metal thin film.
Fig. 5 is the floor map forming source drain contact hole in this utility model first embodiment, as shown in Fig. 5, Fig. 2 a to Fig. 2 b, insulating barrier 16 is formed dielectric layer 14, dielectric layer 14 cover grid have a common boundary 13, the grid 22 of the grid 22 of the first film transistor A and the second thin film transistor (TFT) B, and in dielectric layer 14 and insulating barrier 16, form two source contact openings 31 and two drain contact holes 32.Dielectric layer 14 can be silicon oxide layer or silicon nitride layer or other insulating film layers.
Fig. 6 is the floor map forming source/drain and source/drain lead-in wire in this utility model first embodiment, shown in Fig. 6, Fig. 2 a to Fig. 2 b, formation of deposits the second metal level on dielectric layer 14, is patterned this second metal level to form source lead 11, drain lead 12, the source electrode 23 of the first film transistor A and the source electrode 23 of drain electrode 24 and the second thin film transistor (TFT) B and drain electrode 24 on dielectric layer 14.Source lead 11 is connected with the source electrode 23 of the first film transistor A, drain lead 12 is connected with the drain electrode 24 of the first film transistor A, the separated formation breach 30 of the source electrode 23 of source lead 11 and the second thin film transistor (TFT) B, grid is had a common boundary 13 and is arranged corresponding to this breach 30, grid is had a common boundary between 13 and source lead 11 and grid have a common boundary 13 and second thin film transistor (TFT) B source electrode 23 between be respectively provided with overlay region, drain lead 12 is connected with the drain electrode 24 of the second thin film transistor (TFT) B.The source electrode 23 of the first film transistor A is electrically connected by the semiconductor layer 21 of one of them source contact openings 31 with the first film transistor A, the source electrode 23 of the second thin film transistor (TFT) B is electrically connected by the semiconductor layer 21 of another source contact openings 31 and the second thin film transistor (TFT) B, the drain electrode 24 of the first film transistor A is electrically connected by the semiconductor layer 21 of one of them drain contact hole 32 with the first film transistor A, and the drain electrode 24 of the second thin film transistor (TFT) B is electrically connected by the semiconductor layer 21 of another drain contact hole 32 and the second thin film transistor (TFT) B.Second metal level can adopt the metal or alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, it would however also be possible to employ the laminated film being made up of multiple layer metal thin film.
Fig. 7 is the floor map forming pixel electrode contact hole in this utility model first embodiment, shown in Fig. 7, Fig. 2 a to Fig. 2 b, dielectric layer 14 is formed planarization layer 18, planarization layer 18 covers source lead 11, drain lead 12, the source electrode 23 of the first film transistor A and the source electrode 23 of drain electrode 24 and the second thin film transistor (TFT) B and drain electrode 24, and forms pixel electrode contact hole 33 in planarization layer 18.Planarization layer 18 can be polyimides (Polyimide), silicon oxide layer or silicon nitride layer.
Fig. 1 is the floor map of display membrane transistor arrangement in this utility model first embodiment, as shown in Figure 1, Figure 2 shown in a to Fig. 2 b, also forming pixel electrode 15 on planarization layer 18, pixel electrode 15 is electrically connected with drain lead 12 by this pixel electrode contact hole 33.
Further, the each organic function layer (such as electron injecting layer, electron transfer layer, organic luminous layer, hole transmission layer, hole injection layer) forming OLED can also be made on planarization layer 18, and on organic function layer, make formation negative electrode layer.Therefore, the display membrane transistor arrangement that the present embodiment provides can make and be formed as OLED display.
In the present embodiment, the first film transistor A and the second thin film transistor (TFT) B all adopts top gate structure, but this utility model is not limited to this, and in other embodiments, above-mentioned the first film transistor A and the second thin film transistor (TFT) B can also adopt bottom grating structure.
Fig. 9 is the floor map of display membrane transistor arrangement in this utility model the 3rd embodiment, and Figure 10 a is the cut-away diagram in Fig. 9 along IV-IV line, and Figure 10 b is the cut-away diagram in Fig. 9 along V-V line, and Figure 10 c is the cut-away diagram in Fig. 9 along line VI--VI.Please join Fig. 9, Figure 10 a to Figure 10 b, in the present embodiment, the first film transistor A and the second thin film transistor (TFT) B adopts bottom grating structure, and the first film transistor A and the second thin film transistor (TFT) B can be produced on the array base palte 10 of liquid crystal display, therefore the display membrane transistor arrangement that the present embodiment provides can with colored filter substrate (colorfilter, CF, not shown) collocation making is formed as liquid crystal display.
As shown in Fig. 9, Figure 10 a to Figure 10 b, specifically, in the present embodiment, grid has a common boundary 13, the grid 22 of the first film transistor A and the grid 22 of the second thin film transistor (TFT) B are formed on the substrate 10.Dielectric layer 14 formed on the substrate 10 and cover grid have a common boundary 13, the grid 22 of the grid 22 of the first film transistor A and the second thin film transistor (TFT) B.Source lead 11, drain lead 12, the source electrode 23 of the first film transistor A and the source electrode 23 of drain electrode 24 and the second thin film transistor (TFT) B and drain electrode 24 formation are on dielectric layer 14.Being formed with insulating barrier 16 on dielectric layer 14, insulating barrier 16 covers source lead 11, drain lead 12, the source electrode 23 of the first film transistor A and the source electrode 23 of drain electrode 24 and the second thin film transistor (TFT) B and drain electrode 24.
In the present embodiment, the semiconductor layer 21 of the first film transistor A and the semiconductor layer 21 of the second thin film transistor (TFT) B are formed on dielectric layer 14.The source electrode 23 of the first film transistor A is spaced from each other with drain electrode 24 and all directly contacts with the semiconductor layer 21 of the first film transistor A, and the source electrode 23 of the second thin film transistor (TFT) B is spaced from each other with drain electrode 24 and all directly contacts with the semiconductor layer 21 of the second thin film transistor (TFT) B.
In the present embodiment, pixel electrode 15 is formed on insulating barrier 16, is provided with pixel electrode contact hole 33 in insulating barrier 16, and pixel electrode 15 is electrically connected with drain lead 12 by this pixel electrode contact hole 33.
This utility model also provides for a kind of display, and including the multiple pixels being arranged in array, wherein each pixel is provided with above-mentioned display membrane transistor arrangement.This display can be OLED display or liquid crystal display.Owing to being equipped with two thin film transistor (TFT)s (the first film transistor A and the second thin film transistor (TFT) B) in each pixel, wherein the second thin film transistor (TFT) B is as standby thin film transistor (TFT), when on display, there is defect in certain pixel, laser repairing can be utilized the first film transistor A open circuit, by the second standby thin film transistor (TFT) B connection, thus bad point can thoroughly be repaired.
The display membrane transistor arrangement that this utility model provides, by one or more thin film transistor (TFT)s in parallel on the thin film transistor (TFT) in original image element circuit as backup, when original thin film transistor (TFT) occurs bad, backup thin film transistor (TFT) is enabled through restorative procedure, can thoroughly repair bad point, change and bright spot can only be become dim spot at present, and the present situation that dim spot cannot be repaired.
The above, it it is only preferred embodiment of the present utility model, not this utility model is done any pro forma restriction, although this utility model is disclosed above with preferred embodiment, but it is not limited to this utility model, any those skilled in the art, without departing within the scope of technical solutions of the utility model, when the technology contents of available the disclosure above makes a little change or is modified to the Equivalent embodiments of equivalent variations, in every case it is without departing from technical solutions of the utility model content, any simple modification above example made according to technical spirit of the present utility model, equivalent variations and modification, all still fall within the scope of technical solutions of the utility model.
Claims (13)
1. a display membrane transistor arrangement, it is characterized in that, including forming the first film transistor (A) on substrate (10), second thin film transistor (TFT) (B), source lead (11), drain lead (12), grid has a common boundary (13) and dielectric layer (14), each thin film transistor (TFT) (A, B) semiconductor layer (21) is included, grid (22), source electrode (23) and drain electrode (24), this grid has a common boundary (13), the grid (22) of this first film transistor (A) and the grid (22) of this second thin film transistor (TFT) (B) are arranged in the first metal layer, this source lead (11), this drain lead (12), the source electrode (23) of this first film transistor (A) and the source electrode (23) of drain electrode (24) and this second thin film transistor (TFT) (B) and drain electrode (24) are arranged in the second metal level, this source lead (11) is connected with the source electrode (23) of this first film transistor (A), this drain lead (12) is connected with the drain electrode (24) of this first film transistor (A), between the source electrode (23) of this source lead (11) and this second thin film transistor (TFT) (B) or the separated formation breach (30) of the drain electrode (24) of this drain lead (12) and this second thin film transistor (TFT) (B), this grid is had a common boundary (13) and is arranged corresponding to this breach (30), this dielectric layer (14) is arranged between this first metal layer and this second metal level.
2. display membrane transistor arrangement according to claim 1, it is characterized in that, this breach of the separated formation (30) of the source electrode (23) of this source lead (11) and this second thin film transistor (TFT) (B), this grid is had a common boundary between (13) and this source lead (11) and this grid is had a common boundary between the source electrode (23) of (13) and this second thin film transistor (TFT) (B) and is respectively provided with overlay region, and this drain lead (12) is connected with the drain electrode (24) of this second thin film transistor (TFT) (B).
3. display membrane transistor arrangement according to claim 1, it is characterized in that, this breach of the separated formation (30) of the drain electrode (24) of this drain lead (12) and this second thin film transistor (TFT) (B), this grid has a common boundary (13) and this drain lead (12) and this grid is had a common boundary between (13) and is respectively provided with overlay region between the drain electrode (24) of this second thin film transistor (TFT) (B), and this source lead (11) is connected with the source electrode (23) of this second thin film transistor (TFT) (B).
4. display membrane transistor arrangement according to claim 1, it is characterized in that, this display membrane transistor arrangement also includes scanning line, data wire and pixel electrode (15), the grid (22) of this first film transistor (A) and the grid (22) of this second thin film transistor (TFT) (B) are electrically connected with this scanning line, this source lead (11) is electrically connected with this data wire, and this drain lead (12) is electrically connected with this pixel electrode (15).
5. display membrane transistor arrangement according to claim 4, it is characterized in that, the semiconductor layer (21) of this first film transistor (A) and the semiconductor layer (21) of this second thin film transistor (TFT) (B) are formed on this substrate (10), the semiconductor layer (21) of this first film transistor (A) and semiconductor layer (21) the overlying lid of this second thin film transistor (TFT) (B) are formed with insulating barrier (16), this grid has a common boundary (13), the grid (22) of this first film transistor (A) and the grid (22) of this second thin film transistor (TFT) (B) are formed on this insulating barrier (16), this dielectric layer (14) is formed on this insulating barrier (16), this dielectric layer (14) covers this grid and has a common boundary (13), the grid (22) of this first film transistor (A) and the grid (22) of this second thin film transistor (TFT) (B), this source lead (11), this drain lead (12), the source electrode (23) of this first film transistor (A) and the source electrode (23) of drain electrode (24) and this second thin film transistor (TFT) (B) and drain electrode (24) are formed on this dielectric layer (14).
6. display membrane transistor arrangement according to claim 5, it is characterized in that, being also formed with cushion (17) on this substrate (10), the semiconductor layer (21) of this first film transistor (A) and the semiconductor layer (21) of this second thin film transistor (TFT) (B) are formed on this cushion (17).
7. display membrane transistor arrangement according to claim 5, it is characterized in that, this dielectric layer (14) and this insulating barrier (16) are provided with multiple source contact openings (31) and multiple drain contact hole (32), the source electrode (23) of this first film transistor (A) is electrically connected by the semiconductor layer (21) of one of them source contact openings (31) with this first film transistor (A), the source electrode (23) of this second thin film transistor (TFT) (B) is electrically connected by the semiconductor layer (21) of another source contact openings (31) with this second thin film transistor (TFT) (B), the drain electrode (24) of this first film transistor (A) is electrically connected by the semiconductor layer (21) of one of them drain contact hole (32) with this first film transistor (A), the drain electrode (24) of this second thin film transistor (TFT) (B) is electrically connected by the semiconductor layer (21) of another drain contact hole (32) with this second thin film transistor (TFT) (B).
8. display membrane transistor arrangement according to claim 5, it is characterized in that, this dielectric layer (14) is also formed with planarization layer (18), this planarization layer (18) covers this source lead (11), this drain lead (12), the source electrode (23) of the source electrode (23) of this first film transistor (A) and drain electrode (24) and this second thin film transistor (TFT) (B) and drain (24), this planarization layer (18) is provided with pixel electrode contact hole (33), this pixel electrode (15) is formed on this planarization layer (18), this pixel electrode (15) is electrically connected with this drain lead (12) by this pixel electrode contact hole (33).
9. display membrane transistor arrangement according to claim 4, it is characterized in that, this grid has a common boundary (13), the grid (22) of this first film transistor (A) and the grid (22) of this second thin film transistor (TFT) (B) are formed on this substrate (10), this dielectric layer (14) is formed on this substrate (10) and covers this grid has a common boundary (13), the grid (22) of this first film transistor (A) and the grid (22) of this second thin film transistor (TFT) (B), this source lead (11), this drain lead (12), the source electrode (23) of this first film transistor (A) and the source electrode (23) of drain electrode (24) and this second thin film transistor (TFT) (B) and drain electrode (24) are formed on this dielectric layer (14), this dielectric layer (14) is formed insulating barrier (16), this insulating barrier (16) covers this source lead (11), this drain lead (12), the source electrode (23) of the source electrode (23) of this first film transistor (A) and drain electrode (24) and this second thin film transistor (TFT) (B) and drain (24).
10. display membrane transistor arrangement according to claim 9, it is characterized in that, the semiconductor layer (21) of this first film transistor (A) and the semiconductor layer (21) of this second thin film transistor (TFT) (B) are formed on this dielectric layer (14), the source electrode (23) of this first film transistor (A) is spaced from each other with drain electrode (24) and all directly contacts with the semiconductor layer (21) of this first film transistor (A), the source electrode (23) of this second thin film transistor (TFT) (B) is spaced from each other with drain electrode (24) and all directly contacts with the semiconductor layer (21) of this second thin film transistor (TFT) (B).
11. display membrane transistor arrangement according to claim 9, it is characterized in that, this pixel electrode (15) is formed on this insulating barrier (16), being provided with pixel electrode contact hole (33) in this insulating barrier (16), this pixel electrode (15) is electrically connected with this drain lead (12) by this pixel electrode contact hole (33).
12. a display, including the multiple pixels being arranged in array, it is characterised in that each pixel is provided with the display membrane transistor arrangement as described in any one of claim 1 to 11.
13. display according to claim 12, it is characterised in that this display is OLED display or liquid crystal display.
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