CN205281481U - NANDFlash's data processing device - Google Patents
NANDFlash's data processing device Download PDFInfo
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- CN205281481U CN205281481U CN201521130278.7U CN201521130278U CN205281481U CN 205281481 U CN205281481 U CN 205281481U CN 201521130278 U CN201521130278 U CN 201521130278U CN 205281481 U CN205281481 U CN 205281481U
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- 238000002955 isolation Methods 0.000 claims abstract description 32
- 238000012360 testing method Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 abstract description 16
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 229910052742 iron Inorganic materials 0.000 description 4
- 238000003672 processing method Methods 0.000 description 4
- 238000013500 data storage Methods 0.000 description 1
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Abstract
The embodiment of the utility model discloses NANDFlash's data processing device. The device includes: storage row group, keep apart register and control register, output of the isolation register that each storage row group corresponds, the first control of the control register that corresponds with this storage row group is held and is connected, and the output of each control register is connected with the input of next control register, keep apart the fine or not state that the register is used for the record storage row to organize to transmit fine or not state to the control register, the input of control register is used for acquireing control impuls, and the second control end is used for acquireing the gating signal of control register, if keep apart in the register the pending target storage row group of record for bad group, handles next storage row perform data of group of data bus and target storage row groups and operates. The utility model discloses the process of seeking the actual physical address that outside logical address of visiting is corresponding when reading or writing into the buffer memory data has been simplified to the scheme, has reduced consuming timely.
Description
Technical field
The utility model embodiment relates to data storage technology, particularly relates to the data processing equipment of a kind of NANDFlash.
Background technology
All need to be stored in buffer memory data before programming every time and after reading with the non-volatilization flash memory (NANDFlash) of nand-type. NANDFlash exists bad row Exchange rings, namely when the row existing defects having, need to replace by redundant columns, Fig. 1 is NANDFlash memory row schematic diagram in prior art, as shown in Figure 1, when memory row group A exists bad arranging, it would be desirable to the data being stored into group A are stored into replacement group A ', cause the logical address of outside access and inner actual physical address can not order be corresponding completely. So when reading or write data cached, it is necessary to go to find actual physical address corresponding to the outside logical address accessed.
But the process found is very consuming time, especially reaching 400MB/S when lower interface speed, wanting to find within the short time complete, the requirement of circuit designers and technique is very high.
Practical novel content
The utility model provides the data processing equipment of a kind of NANDFlash, finds the process of actual physical address corresponding to the outside logical address accessed, reduce consuming time when reading to be reduced at or write data cached.
First aspect, the utility model embodiment provides the data processing equipment of a kind of NANDFlash, and described device comprises memory row group, isolation register and control register, wherein;
The output terminal of the isolation register that each memory row group is corresponding, the first control end of the control register corresponding with this memory row group connects, and the output terminal of each control register is connected with the input terminus of next control register;
Described isolation register for recording the fine or not state of memory row group, and by described quality state transfer to described control register;
The input terminus of described control register is for obtaining setting pulse, 2nd control end is for obtaining the gating signal of control register, if recording pending target memory row group in described isolation register is bad group, next memory row group of data bus and described target memory row group is performed data processing operation.
The utility model embodiment is by the fine or not state of isolation register record memory row group, and by the fine or not state transfer of memory row group to control register, when data processing, if recording pending target memory row group in described isolation register is bad group, then next memory row group of data bus and described target memory row group is performed data processing operation by control register, simplify the process of actual physical address corresponding to the logical address finding outside access when reading or write data cached, reduce consuming time.
Accompanying drawing explanation
Fig. 1 is NANDFlash memory row schematic diagram in prior art;
Fig. 2 is the schema of the data processing method of the data device execution of the NANDFlash that the utility model embodiment provides;
Fig. 3 is the NANDFlash memory row schematic diagram in the utility model embodiment;
Fig. 4 is the schema of the data processing method of the data device execution of the NANDFlash provided in the utility model embodiment;
Fig. 5 is the structure iron of the data processing equipment of a kind of NANDFlash in the utility model embodiment;
Fig. 6 is the structure iron of the control register in the utility model embodiment.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail. It should be appreciated that specific embodiment described herein is only for explaining the utility model, but not to restriction of the present utility model. It also should be noted that, for convenience of description, accompanying drawing illustrate only the part relevant to the utility model and not all structure.
Fig. 2 is the schema of the data processing method of the data device execution of the NANDFlash that the utility model embodiment provides, the present embodiment is applicable in the situation that NANDFlash during data cached process exists bad row, as shown in Figure 2, described method specifically can comprise the steps:
The fine or not state of step 110, isolation register record memory row group.
Concrete, the corresponding isolation register of each memory row group, the write when carrying out memory row and test of the value of described isolation register, for recording the fine or not state of memory row group, wherein memory row group may be group, it is also possible to bad group. A memory row group is made up of multiple memory row, such as, it is possible to be made up of 8,16 or 32 memory rows, is classified as bad as long as there is a storage in memory row group, then this group memory row is recorded as bad group.
If recording pending target memory row group in step 120 described isolation register is bad group, then next memory row group of data bus and described target memory row group is performed data processing operation by control register.
Concrete, in data writing process, if target memory row group is bad group, then the data on data bus are write in next memory row group of described target memory row group by control register; In data read process, if target memory row group is bad group, then control register controls next the memory row group reading data of described data bus from described target memory row group.
Fig. 3 is the NANDFlash memory row schematic diagram in the utility model embodiment, as shown in Figure 3, scheme of the present utility model is when reading and writing data, memory row is redistributed, all memory rows are all made no exception, compared to part memory row in existing NANDFlash memory row be arm's length standard row, part memory row is redundant columns, this embodiment simplifies the structure of memory row. In Fig. 3, each small rectangle represents a memory row group, when writing data, the input terminus of the control register that target memory row group A is corresponding exists writes setting pulse, if target memory row group A as well group, writing setting pulse normal through control register, data write target memory row group A; If target memory row group A is bad group, write setting pulse and skip control register corresponding to target memory row group, it is transferred to the control register that next memory row group A' is corresponding, data corresponding to target memory row group A are written to next memory row group A', the replacement group replacing target memory row group A is found without the need to arriving redundant columns again, simplify replacement process, accelerate the speed writing data.
Reading according to time and above-mentioned to write data procedures similar, when target memory row group is for bad group, directly skip target memory row group, read the data that next memory row group is corresponding, like this reading according to time, it is not necessary to from redundant columns, find replacement group again, accelerate reading data speed. The scheme of the present embodiment makes the logical address of outside access corresponding with actual physical address successively order, when reading and writing data, only need to carry out successively according to the order of memory row group, accelerate read or write speed.
The technical scheme of the present embodiment, by isolating the fine or not state of register record memory row group, when data processing, if recording pending target memory row group in described isolation register is bad group, then next memory row group of data bus and described target memory row group is performed data processing operation by control register, simplify the process of actual physical address corresponding to the logical address finding outside access when reading or write data cached, reduce consuming time.
Fig. 4 is the schema of the data processing method of the data device execution of the NANDFlash that the utility model embodiment provides, and as shown in Figure 4, described method specifically can comprise the steps:
Step 210, address control module determine the actual physical address that the first address of the logical address of described target memory row group is corresponding.
Wherein, when inputting read-write instruction and read-write logical address user, address control module inquires about the actual physical address of memory row group corresponding to described logical address, to carry out the read-write of data. Concrete, before first data write or reading, it is possible to given default time value, it being used for finding physical address corresponding to first address, shown default time value can be 300ns etc.
The fine or not state of step 220, isolation register record memory row group.
Concrete, before the fine or not state of isolation register record memory row group, it is also possible to comprising: the fine or not state of test each memory row group of module testing. NANDFlash exists the test module of test storage row, after outside tester table sends test instruction to described test module, the test module fine or not state that test storage arranges successively, and the fine or not state of each memory row group is stored into isolation register.
If recording pending target memory row group in step 230 described isolation register is bad group, then next memory row group of data bus and described target memory row group is performed data processing operation by control register.
Concrete, when reading and writing data, can according to the number of the length setting timeticks of data, write by corresponding memory row group successively from the memory row group of first address according to timeticks or read data, directly skip when running into bad group, continue next memory row group is performed corresponding read-write operation, the total length of memory row can be controlled like this, making it possible to any memory allocated space, available space becomes big.
Optionally, control register also comprises after next memory row group of data bus and described target memory row group is performed data processing operation: the logical address of memory row group of memory module record write data and the corresponding relation of actual physical address. The corresponding relation of record logical address and actual physical address facilitates and carries out write operation distribute storage space next time, and when reading data, it is possible to the very fast actual physical address finding the logical address of outside access corresponding, accelerate read or write speed.
Fig. 5 is the structure iron of the data processing equipment of a kind of NANDFlash in the utility model embodiment, and as shown in Figure 5, the data processing equipment of described NANDFlash comprises memory row group 310, isolation register 320 and control register 330, wherein;
The output terminal of the isolation register 320 of each memory row group 310 correspondence, the first control end of the control register 330 corresponding with this memory row group 310 connects, and the output terminal of each control register 330 is connected with the input terminus of next control register 330;
Isolate register 320 for recording the fine or not state of memory row group 310, and by described quality state transfer to control register 330;
The input terminus of control register 330 is for obtaining setting pulse, 2nd control end is for obtaining the gating signal of control register 330, if isolation register 320 recording pending target memory row group 310 for bad row, next memory row group 310 of data bus and target memory row group 310 is performed data processing operation.
Wherein, control register 330 specifically for: in data writing process, if target memory row group is bad group, the data on data bus are write in next memory row group of described target memory row group; In data read process, if target memory row group is bad group, then controls described data bus and read data from next memory row group of described target memory row group.
Concrete, a memory row group is made up of multiple memory row, such as, it is possible to be made up of 8,16 or 32 memory rows, is classified as bad as long as there is a storage in memory row group, then this group memory row is recorded as bad group. in Fig. 5, each small rectangle of the first row represents a memory row group, the corresponding isolation register 320 of each memory row group 310, control register 330 can corresponding one or more memory row group 310, Fig. 5 illustrate only the situation of the corresponding control register 330 of a memory row group 310, as shown in Figure 5, first control end of the control register 330 that the output terminal of the isolation register 320 of each memory row group 310 correspondence is corresponding with this memory row group 310 connects, when a certain memory row group 310 is for bad group, setting pulse skips the corresponding control register 330 of this evil idea group, it is transferred to the control register 330 of next memory row group 310 correspondence, next memory row group 310 is carried out corresponding data processing operation.
When the corresponding multiple memory row group 310 of control register 330, the output terminal of multiple isolation registers 320 of multiple memory row group 310 correspondence is all connected with the first control end of this control register 330, and this kind of situation can by coming control register 330 timesharing multiplexing multiple memory row groups 310 of this control register 330 correspondence to be read and write data respectively.
Fig. 6 is the structure iron of the control register in the utility model embodiment, and as shown in Figure 6, ISO is the first control end of control register 330, IS1 is the 2nd control end, and IN is input terminus, and OUT is output terminal, CLK is clock signal input terminal, and CLKB is the non-signal input terminus of clock. When the memory row group of control register 330 correspondence is target memory row group, the value of the gating signal that the 2nd control end IS1 gets is 1, there is setting pulse in its input terminus IN, the value of pulse is 1, when target memory row group is as well organized, the value of ISO end input is after 0, clock period, setting pulse is exported by control register 330, data write or reading target memory row group; When target memory row group is for bad group, the value of ISO end input is 1, then the direct set of output terminal OUT of control register is 1, setting pulse directly skips control register 330 corresponding to target memory row group, after the clock period, setting pulse is exported by the control register 330 that next memory row group is corresponding, next group of data write or reading target memory row group.
Further, described device also comprises: memory module, for recording the logical address of memory row group and the corresponding relation of actual physical address of write data.
Further, described device also comprises: address control module, it is connected with the output terminal of described memory module and the 2nd control end of control register respectively, for the actual physical address that to determine the first address of the logical address of described target memory row group corresponding, and the gating signal to described control register transmit control register.
Further, described device also comprises: test module, is connected with the input terminus of described isolation register, for testing the fine or not state of each memory row group, and the described isolation register by described quality state transfer.
The data processing equipment of the NANDFlash that the present embodiment provides is by the fine or not state of isolation register record memory row group, and by the fine or not state transfer of memory row group to control register, when data processing, if recording pending target memory row group in described isolation register is bad group, then next memory row group of data bus and described target memory row group is performed data processing operation by control register, simplify the process of actual physical address corresponding to the logical address finding outside access when reading or write data cached, reduce consuming time.
Note, above are only better embodiment of the present utility model and institute's application technology principle. It is understood by those skilled in the art that the utility model is not limited to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and protection domain of the present utility model can not be departed from. Therefore, although the utility model being described in further detail by above embodiment, but the utility model is not limited only to above embodiment, when not departing from the utility model and conceive, other equivalence embodiments more can also be comprised, and scope of the present utility model is determined by appended right.
Claims (5)
1. the data processing equipment of a NANDFlash, it is characterised in that, comprise memory row group, isolation register and control register, wherein;
The output terminal of the isolation register that each memory row group is corresponding, the first control end of the control register corresponding with this memory row group connects, and the output terminal of each control register is connected with the input terminus of next control register;
Described isolation register for recording the fine or not state of memory row group, and by described quality state transfer to described control register;
The input terminus of described control register is for obtaining setting pulse, 2nd control end is for obtaining the gating signal of control register, if recording pending target memory row group in described isolation register is bad group, next memory row group of data bus and described target memory row group is performed data processing operation.
2. device according to claim 1, it is characterised in that, described control register specifically for:
Data on data bus are write in next memory row group of described target memory row group; Or,
Control described data bus and read data from next memory row group of described target memory row group.
3. device according to claim 2, it is characterised in that, also comprise:
Memory module, for recording the logical address of memory row group and the corresponding relation of actual physical address of write data.
4. device according to claim 3, it is characterised in that, also comprise:
Address control module, it is connected with the output terminal of described memory module and the 2nd control end of control register respectively, for the actual physical address that to determine the first address of the logical address of described target memory row group corresponding, and the gating signal to described control register transmit control register.
5. device according to claim 1, it is characterised in that, also comprise:
Test module, is connected with the input terminus of described isolation register, for testing the fine or not state of each memory row group, and the described isolation register by described quality state transfer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201521130278.7U CN205281481U (en) | 2015-12-30 | 2015-12-30 | NANDFlash's data processing device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201521130278.7U CN205281481U (en) | 2015-12-30 | 2015-12-30 | NANDFlash's data processing device |
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| CN205281481U true CN205281481U (en) | 2016-06-01 |
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
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