CN205263799U

CN205263799U - Treatment circuit of indiscriminate preface response package of PCIe link

Info

Publication number: CN205263799U
Application number: CN201521037193.4U
Authority: CN
Inventors: 杨海波; 袁晓军; 王玉欢; 李攀; 霍卫涛
Original assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Current assignee: Xian Xiangteng Microelectronics Technology Co Ltd
Priority date: 2015-12-11
Filing date: 2015-12-11
Publication date: 2016-05-25
Anticipated expiration: 2025-12-11

Abstract

The utility model relates to a treatment circuit of indiscriminate preface response package of PCIe link, this circuit contain TAG interpolation module, FIFO group module, TAG judges and FIFO writes the entry control module and FIFO reads out control module, TAG adds the module and links to each other with local device and treater, FIFO group module is judged with TAG respectively and FIFO writes the entry control module and reads out control module with FIFO and link to each other, and TAG judges and FIFO writes the entry control module and links to each other with treater and FIFO group module, and it is continuous with the local device that FIFO reads out control module. The utility model discloses in having avoided the PCIe communication process effectively, indiscriminate preface problem is wrapped in the response that the host computer was replied.

Description

A kind for the treatment of circuit of PCIe link circuit out of order respond packet

Technical field

The utility model belongs to IC design technology, relates to locating of a kind of PCIe link circuit out of order respond packetReason circuit.

Background technology

In the transfer of data of PCIe link, due to main frame (especially PowerPC series main frame) insideDesign optimization, often there will be the out of order phenomenon of respond packet of reply.

Traditional way is that the packet of host response is all directly carried out to out of order reception, then at local deviceRecombinating according to data characteristic in inside, causes local device indoor design complexity.

Utility model content

In order to solve the problem of mentioning in above-mentioned background, the utility model provides a kind of PCIe link circuit out of order to ringThe treatment circuit that should wrap, before the respond packet of carrying out self processor enters local device by this circuit by its byOrganize according to order, greatly reduced the design complexities of local device inside.

Technical solution of the present utility model is: the utility model is a kind of PCIe link circuit out of order respond packetTreatment circuit, its special character is: this circuit comprises TAG and adds module, FIFO pack module, TAGJudgement and FIFO writes control module and FIFO reads control module; TAG add module and local device andProcessor is connected, and described FIFO pack module writes control module and FIFO with TAG judgement and FIFO respectivelyRead control module and be connected, TAG judgement and FIFO write control module and processor and FIFO pack module phaseConnect, FIFO reads control module and is connected with local device.

The TAG field that above-mentioned TAG adds in the request bag that module is local device is added correct TAG, theThe TAG field of a request bag is 1, and the TAG field of follow-up request bag adds 1 successively, and this TAG getsValue scope is 1～N, and N is the credit value that local device is corresponding.

Above-mentioned FIFO pack module comprises N FIFO, the credit value N that N is local device, each FIFO'sCapacity can be stored a respond packet from main frame just.

Above-mentioned TAG judgement and FIFO write control module and receive for controlling from the respond packet of main frame, byTAG field one in the request bag that TAG field in the packet returning in main frame and local device sendCause, therefore TAG judgement and FIFO write control module and are write correspondence according to TAG field in respond packetFIFO in, the respond packet that TAG field is 0 writes FIFO0, the respond packet that TAG field is 1 is writeEnter FIFO1 ..., the respond packet that TAG field is N writes FIFON.

Above-mentioned FIFO reads control module and reads for controlling according to the numeric order of FIFO, works as reading orderArrived certain FIFO, and temporary transient countless certificates in this FIFO force to wait for, until it has number also to read,Then read next FIFO.

The treatment circuit of the PCIe link circuit out of order respond packet that the utility model provides is by increasing outward at local deviceAdd the mode for the treatment of circuit, by increasing TAG field in local device request bag, TAG field is opened from 1Beginning increases progressively, until reach the credit value of local device. In treatment circuit, be arranged at the letter of local device simultaneouslyThe N matching with a value N FIFO carrys out the respond packet of self processor for sequential storage, then reads by TAGGo out control module and package, ensure that data and the order of PCIe packet before entering local device is equalCorrectly, avoided the problem of PCIe link circuit out of order respond packet, and thoroughly solved group in local deviceThe resource burden that bag causes, has great reference to the design of other link circuit out of order bags.

Brief description of the drawings

Fig. 1 is configuration diagram of the present utility model.

Detailed description of the invention

Below in conjunction with drawings and Examples, the utility model is described further:

Referring to Fig. 1, the utility model comprise TAG add module 1, FIFO pack module 2, TAG judgement andFIFO writes control module 3 and FIFO reads control module 4.

TAG adds module 1 and is connected with local device and processor, and TAG interpolation module 1 is local deviceTAG field in request bag is added correct TAG, and the TAG field of first request bag is 1, follow-upThe TAG field of request bag adds 1 successively, and the span of this TAG is 1～N, and N is the letter that local device is correspondingBy value.

FIFO pack module 2 is with TAG judgement and FIFO writes control module 3 and FIFO reads control module 4Be connected, FIFO pack module 2 comprises N FIFO, the credit value N that N is local device, each FIFO'sCapacity can be stored a respond packet from main frame just.

TAG judgement and FIFO write control module 3 and are connected with processor and FIFO pack module 2, and TAG sentencesDisconnected and FIFO writes control module 3 and receives for controlling from the respond packet of main frame, because main frame returnsTAG field in the request bag that TAG field in packet sends with local device is consistent, and therefore TAG sentencesDisconnected and FIFO writes control module 3 and is write in corresponding FIFO, according to TAG field in respond packetTAG field is that 0 respond packet writes FIFO0, and the respond packet that TAG field is 1 writes FIFO1 ..., TAGField is that the respond packet of N writes FIFON.

FIFO reads control module 4 and is connected with FIFO pack module 2 and local device, and FIFO reads control mouldPiece 4 is read for controlling according to the numeric order of FIFO, when reading order has arrived certain FIFO, and this FIFOIn temporary transient countless certificates, force to wait for, until it has number and reads, then read next FIFO.

Finally it should be noted that: above embodiment is only in order to the technical solution of the utility model to be described, but not rightIts restriction; Although the utility model is explained with reference to previous embodiment, this area commonTechnical staff is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified,Or part technical characterictic is wherein equal to replacement; And these amendments or replacement do not make corresponding skillThe essence of art scheme departs from the spirit and scope of the each embodiment technical scheme of the utility model.

Claims

1. a treatment circuit for PCIe link circuit out of order respond packet, is characterized in that: this circuit comprises TAGAdd module, FIFO pack module, TAG judgement and FIFO writes control module and FIFO reads control module;TAG add module be connected with local device and processor, described FIFO pack module respectively with TAG judge andFIFO writes control module and reads control module with FIFO and be connected, and TAG judgement and FIFO write control moduleBe connected with processor and FIFO pack module, FIFO reads control module and is connected with local device.

2. the treatment circuit of PCIe link circuit out of order respond packet according to claim 1, is characterized in that:The TAG field that described TAG adds in the request bag that module is local device is added correct TAG, firstThe TAG field of request bag is 1, and the TAG field of follow-up request bag adds 1 successively, the value model of this TAGEnclosing is 1～N, and N is the credit value that local device is corresponding.

3. the treatment circuit of PCIe link circuit out of order respond packet according to claim 2, is characterized in that:Described FIFO pack module comprises N FIFO, the credit value N that N is local device, the capacity of each FIFOJust can store a respond packet from main frame.

4. the treatment circuit of PCIe link circuit out of order respond packet according to claim 3, is characterized in that:Described TAG judgement and FIFO write control module and receive for controlling from the respond packet of main frame, due to masterTAG field in the request bag that TAG field in the packet that machine returns sends with local device is consistent, because ofThis TAG judgement and FIFO write control module and are write corresponding FIFO according to TAG field in respond packetIn, the respond packet that TAG field is 0 writes FIFO0, and the respond packet that TAG field is 1 writes FIFO1 ..., the respond packet that TAG field is N writes FIFON.

5. the treatment circuit of PCIe link circuit out of order respond packet according to claim 4, is characterized in that:Described FIFO reads control module and reads for controlling according to the numeric order of FIFO, when reading order has arrivedCertain FIFO, and temporary transient countless certificates in this FIFO, force to wait for, until it has number and has read, turnsAnd read next FIFO.