CN205142256U - EPA bus and HART bus communication network bridge - Google Patents
EPA bus and HART bus communication network bridge Download PDFInfo
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- CN205142256U CN205142256U CN201520875545.7U CN201520875545U CN205142256U CN 205142256 U CN205142256 U CN 205142256U CN 201520875545 U CN201520875545 U CN 201520875545U CN 205142256 U CN205142256 U CN 205142256U
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- 230000002093 peripheral effect Effects 0.000 claims abstract description 20
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Abstract
The utility model relates to a EPA bus and HART bus communication network bridge, it includes HART bus interface, core control module and EPA bus interface, HART bus interface includes HART chip and peripheral circuit, core control module includes ARM control chip and peripheral circuit, EPA bus interface includes EPA network chip and peripheral circuit and network transformer, wherein HART chip and peripheral circuit link to each other with ARM control chip, EPA network chip and peripheral circuit link to each other with ARM control chip and peripheral circuit, network transformer respectively. The technical effect is that the mutual communication between HART bus and EPA bus is realized, HART equipment and EPA equipment can coexist in the same system, and when the equipment of industrial process control system is upgraded, because new and old equipment can be compatible, the system reconstruction cost is greatly reduced.
Description
Technical field
The utility model relates to the field bus communication bridge in industrial stokehold, the communication bridge particularly between a kind of EPA bus and HART bus.
Background technology
There is multiple bus standard at industrial automation at present, fieldbus popular at present mainly contains CAN(control area net（CAN） network), PROFIBUS(Process FieldbusROFIBUS), HART(highway addressable remote transducer), FF(foundation fieldbus), LonWorks.HART field bus technique wherein based on HART technology is most widely used a kind of field bus technique in the world.These bus standards are mostly formulated and promotion and implementation by esbablished corporation in automatic field.Due to reasons such as respective interests and technical know-hows, different bus standards causes communication difficulties between various bus, access mutually and operation cannot be realized between bus apparatus, when the device upgrade of industrial process control system, significantly incompatible between existing equipment and new equipment, thus causing used equipment to eliminate, system reform cost also improves thereupon greatly.
Deposit at current multiple fieldbus, under situation that cannot be unified, Industrial Ethernet becomes new developing direction, and it has outstanding features such as being widely used, with low cost, technical resource abundant, reliability is high, transmission speed is fast.Industrial automation Ethernet EPA bus standard is that one has wide application prospect at present, and has the industrial Ethernet technology of China's independent intellectual property right, and other bus and the mutual communication of EPA bus become the focus studied at present.
Summary of the invention
In view of above-mentioned prior art situation, the purpose of this utility model is to provide a kind of EPA bus and HART bus communication bridge, this bridge makes current widely used HART bus signals convert EPA bus signals to, realizes HART equipment and EPA coexistence in same system.
The technical scheme taked is, a kind of EPA bus and HART bus communication bridge, it is characterized in that: it comprises HART bus interface, kernel control module and EPA bus interface, HART bus interface comprises HART chip and peripheral circuit thereof, kernel control module comprises ARM control chip and peripheral circuit thereof, EPA bus interface comprises EPA network chip and peripheral circuit thereof and network transformer, wherein HART chip and peripheral circuit thereof are connected with ARM control chip, EPA network chip and peripheral circuit thereof respectively with ARM control chip and peripheral circuit thereof, network transformer is connected.
The beneficial effect that the utility model produces is: the mutual communication realizing HART bus and EPA bus, makes HART equipment and EPA equipment can coexist in same system, when the device upgrade of industrial process control system, greatly reduces system reform cost.
Accompanying drawing explanation
Fig. 1 is the utility model catenation principle block diagram.
Fig. 2 is the utility model HART bus interface electrical schematic diagram.
Fig. 3 is the utility model kernel control module and EPA bus interface electrical schematic diagram.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in further detail.
As shown in Figure 1, 2, 3, EPA bus and HART bus communication bridge comprise HART bus interface, kernel control module and EPA bus interface, HART bus interface comprises HART chip and peripheral circuit thereof, kernel control module and EPA bus interface comprise ARM control chip, EPA network chip and peripheral circuit thereof and transformer L, wherein HART chip and peripheral circuit thereof are connected with ARM control chip, and EPA network chip and peripheral circuit thereof are connected with ARM control chip and peripheral circuit thereof, network transformer respectively.(see figure 1)
HART chip adopts A5191 chip, and ARM control chip adopts AT91SAM7x256 chip, and EPA network chip adopts RTL8201BL chip, and network transformer adopts the PRJ-005A transformer of band network interface, and transformer L is self-control.
The pin two 5 of A5191 chip is connected with the pin 81 of AT91SAM7x256 chip, the pin two 3 of A5191 chip is connected with the pin 82 of AT91SAM7x256 chip, the pin two 2 of A5191 chip and the pin 86 of AT91SAM7x256 chip, the pin 6 of A5191 chip connects, the pin 7 of the one termination A5191 chip of electric capacity C1, the pin 8 of another termination electronic switch ADG1419 chip of electric capacity C1, the pin one 5 of the one termination A5191 chip of resistance R1, the other end of resistance R1 and one end of electric capacity C2, one end of electric capacity C3, one end of resistance R3 connects, the other end of electric capacity C2 is connected with one end of resistance R2, the other end ground connection of resistance R3, the other end of electric capacity C3 is connected with the pin two of electronic switch ADG1419 chip, the other end of resistance R2 and one end of resistance R5, the pin one 4 of A5191 chip connects, the other end ground connection of resistance R5, the pin one of electronic switch ADG1419 chip is connected with the pin one of transformer L, the pin two ground connection of transformer L, the pin 3 of transformer L, 4 are concatenated into HART bus.(see figure 2)
The pin two 5 of RTL8201BL chip is connected with the pin two 8 of AT91SAM7x256 chip, the pin two 6 of RTL8201BL chip is connected with the pin two 7 of AT91SAM7x256 chip, the pin 6 of RTL8201BL chip is connected with the pin 34 of AT91SAM7x256 chip, the pin 5 of RTL8201BL chip is connected with the pin 31 of AT91SAM7x256 chip, the pin 4 of RTL8201BL chip is connected with the pin 44 of AT91SAM7x256 chip, the pin 3 of RTL8201BL chip is connected with the pin 45 of AT91SAM7x256 chip, the pin two of RTL8201BL chip is connected with the pin 41 of AT91SAM7x256 chip, the pin 7 of RTL8201BL chip is connected with the pin 40 of AT91SAM7x256 chip, the pin two 2 of RTL8201BL chip is connected with the pin 35 of AT91SAM7x256 chip, the pin two 1 of RTL8201BL chip is connected with the pin 34 of AT91SAM7x256 chip, the pin two 0 of RTL8201BL chip is connected with the pin 31 of AT91SAM7x256 chip, the pin one 9 of RTL8201BL chip is connected with the pin 30 of AT91SAM7x256 chip, the pin one 8 of RTL8201BL chip is connected with the pin two 9 of AT91SAM7x256 chip, the pin one 6 of RTL8201BL chip is connected with the pin 36 of AT91SAM7x256 chip, the pin one of RTL8201BL chip is connected with the pin 53 of AT91SAM7x256 chip, the pin two 3 of RTL8201BL chip is connected with the pin 54 of AT91SAM7x256 chip, the pin two 4 of RTL8201BL chip is connected with the pin 38 of AT91SAM7x256 chip, the pin 3 of PRJ-005A transformer (network transformer of band network interface) is connected with the pin 31 of RTL8201BL chip, the pin 6 of PRJ-005A transformer is connected with the pin 30 of RTL8201BL chip, and the pin one of PRJ-005A transformer is connected with the pin 34 of RTL8201BL chip, the pin two of PRJ-005A transformer is connected with the pin 33 of RTL8201BL chip, and the pin 5 of PRJ-005A transformer is connected with one end of electric capacity C5, the other end ground connection of electric capacity C5.(see figure 3), the prefabricated software systems of ARM control chip AT91SAM7x256, and transplant the ICP/IP protocol having embedded OS uC/OS-II and LwIP(to simplify) agreement, and add EPA layer on this basis to realize EPA agreement, and add HART protocol conversion code in application layer.
Claims (1)
1. an EPA bus and HART bus communication bridge, it is characterized in that: it comprises bus interface, kernel control module and EPA bus interface, described HART bus interface comprises transformer L and HART chip and peripheral circuit thereof, the described kernel control module EPA bus interface comprised described in ARM control chip and peripheral circuit thereof comprises EPA network chip and peripheral circuit thereof and network transformer, wherein HART chip adopts A5191 chip, ARM control chip adopts AT91SAM7x256 chip, EPA network chip adopts RTL8201BL chip, network transformer adopts the PRJ-005A transformer of band network interface, A5191 chip is connected with AT91SAM7x256 chip and is connected with the pin 81 of AT91SAM7x256 chip for the pin two 5 of A5191 chip, the pin two 3 of A5191 chip is connected with the pin 82 of AT91SAM7x256 chip, the pin two 2 of A5191 chip and the pin 86 of AT91SAM7x256 chip, the pin 6 of A5191 chip connects, the pin 7 of the one termination A5191 chip of electric capacity C1, the pin 8 of another termination electronic switch ADG1419 chip of electric capacity C1, the pin one 5 of the one termination A5191 chip of resistance R1, the other end of resistance R1 and one end of electric capacity C2, one end of electric capacity C3, one end of resistance R3 connects, the other end of electric capacity C2 is connected with one end of resistance R2, the other end ground connection of resistance R3, the other end of electric capacity C3 is connected with the pin two of electronic switch ADG1419 chip, the other end of resistance R2 and one end of resistance R5, the pin one 4 of A5191 chip connects, the other end ground connection of resistance R5, the pin one of electronic switch ADG1419 chip is connected with the pin one of transformer L, the pin two ground connection of transformer L, the pin 3 of transformer L, 4 are concatenated into HART bus, RTL8201BL chip is connected with AT91SAM7x256 chip and is connected with the pin two 8 of AT91SAM7x256 chip for the pin two 5 of RTL8201BL chip, the pin two 6 of RTL8201BL chip is connected with the pin two 7 of AT91SAM7x256 chip, the pin 6 of RTL8201BL chip is connected with the pin 34 of AT91SAM7x256 chip, the pin 5 of RTL8201BL chip is connected with the pin 31 of AT91SAM7x256 chip, the pin 4 of RTL8201BL chip is connected with the pin 44 of AT91SAM7x256 chip, the pin 3 of RTL8201BL chip is connected with the pin 45 of AT91SAM7x256 chip, the pin two of RTL8201BL chip is connected with the pin 41 of AT91SAM7x256 chip, the pin 7 of RTL8201BL chip is connected with the pin 40 of AT91SAM7x256 chip, the pin two 2 of RTL8201BL chip is connected with the pin 35 of AT91SAM7x256 chip, the pin two 1 of RTL8201BL chip is connected with the pin 34 of AT91SAM7x256 chip, the pin two 0 of RTL8201BL chip is connected with the pin 31 of AT91SAM7x256 chip, the pin one 9 of RTL8201BL chip is connected with the pin 30 of AT91SAM7x256 chip, the pin one 8 of RTL8201BL chip is connected with the pin two 9 of AT91SAM7x256 chip, the pin one 6 of RTL8201BL chip is connected with the pin 36 of AT91SAM7x256 chip, the pin one of RTL8201BL chip is connected with the pin 53 of AT91SAM7x256 chip, the pin two 3 of RTL8201BL chip is connected with the pin 54 of AT91SAM7x256 chip, the pin two 4 of RTL8201BL chip is connected with the pin 38 of AT91SAM7x256 chip, PRJ-005A transformer is connected with RTL8201BL chip and is connected with the pin 31 of RTL8201BL chip for the pin 3 of PRJ-005A transformer, the pin 6 of PRJ-005A transformer is connected with the pin 30 of RTL8201BL chip, the pin one of PRJ-005A transformer is connected with the pin 34 of RTL8201BL chip, the pin two of PRJ-005A transformer is connected with the pin 33 of RTL8201BL chip, the pin 5 of PRJ-005A transformer is connected with one end of electric capacity C5, the other end ground connection of electric capacity C5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520875545.7U CN205142256U (en) | 2015-11-05 | 2015-11-05 | EPA bus and HART bus communication network bridge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520875545.7U CN205142256U (en) | 2015-11-05 | 2015-11-05 | EPA bus and HART bus communication network bridge |
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| Publication Number | Publication Date |
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| CN205142256U true CN205142256U (en) | 2016-04-06 |
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| CN201520875545.7U Expired - Fee Related CN205142256U (en) | 2015-11-05 | 2015-11-05 | EPA bus and HART bus communication network bridge |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105227417A (en) * | 2015-11-05 | 2016-01-06 | 中环天仪股份有限公司 | EPA bus and HART bus communication bridge |
| CN110930820A (en) * | 2019-12-12 | 2020-03-27 | 中环天仪股份有限公司 | HART bus protocol learning system |
-
2015
- 2015-11-05 CN CN201520875545.7U patent/CN205142256U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105227417A (en) * | 2015-11-05 | 2016-01-06 | 中环天仪股份有限公司 | EPA bus and HART bus communication bridge |
| CN110930820A (en) * | 2019-12-12 | 2020-03-27 | 中环天仪股份有限公司 | HART bus protocol learning system |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160406 |
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| CF01 | Termination of patent right due to non-payment of annual fee |