CN205120876U - Fault detection apparatus for super capacitor - Google Patents
Fault detection apparatus for super capacitor Download PDFInfo
- Publication number
- CN205120876U CN205120876U CN201520931198.5U CN201520931198U CN205120876U CN 205120876 U CN205120876 U CN 205120876U CN 201520931198 U CN201520931198 U CN 201520931198U CN 205120876 U CN205120876 U CN 205120876U
- Authority
- CN
- China
- Prior art keywords
- circuit
- interface circuit
- signal
- super capacitor
- processor circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 87
- 238000001514 detection method Methods 0.000 title claims abstract description 75
- 238000003745 diagnosis Methods 0.000 claims abstract description 4
- 238000004891 communication Methods 0.000 claims description 54
- 238000000034 method Methods 0.000 claims description 46
- 238000006243 chemical reaction Methods 0.000 claims description 43
- 230000006641 stabilisation Effects 0.000 claims description 7
- 238000011105 stabilization Methods 0.000 claims description 7
- 238000012856 packing Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 abstract 1
- 238000001914 filtration Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 11
- 238000012545 processing Methods 0.000 description 11
- 238000012360 testing method Methods 0.000 description 11
- 238000002955 isolation Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 239000011324 bead Substances 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
Landscapes
- Dc-Dc Converters (AREA)
Abstract
The utility model provides a fault detection apparatus for super capacitor. The device includes: a input filter circuit with be used for the basis for connecting the output interface of super capacitor detected signal the historical output of input filter circuit and the processor circuit that super capacitor failure diagnosis is carried out in current output, the input filter circuit with the processor circuit electricity is connected. The utility model provides an among the fault detection apparatus for super capacitor, processor circuit according to current and before a plurality of super capacitor's of received multichannel detected signal fault detection carries out, effectively avoided disturbing the wrong report that leads to because of the detected signal receives, failing to report the phenomenon, improved the rate of accuracy to super capacitor's fault detection.
Description
Technical field
The utility model relates to technical field of wind power, particularly relates to a kind of super capacitor failure detector.
Background technology
In recent years, along with the lasting of total installation of generating capacity of wind power generating set is risen, the requirement of industry to wind power generating set performance and operational reliability also progressively improves.Pitch-controlled system is as one of the kernel subsystems of wind turbine control system, and its major function has 2 points: one, and when normally running, the change according to wind speed regulates propeller pitch angle, realizes the regulation and control of power; Two, when wind power generating set breaks down, put away the oars fast to stop position, realize brake, ensure the safety of wind power generating set.
For pitch-controlled system, when line voltage is normal, the power driving pitch motor to put away the oars provides by after electrical network rectification; When grid voltage sags or power-off, need back-up source (such as super capacitor) to provide DC voltage for variable pitch driver, realize blade safe feathering, reach the object of safe operation.
But along with the prolongation of super capacitor service time, super capacitor there will be that interior resistive is large, capacitance decay and then cause super capacitor excess temperature or overvoltage, and blast may appear in extreme case, catch fire equivalent risk.When electric network power-fail or other fault, if super capacitor breaks down, then wind power generating set cannot normally be put away the oars, and there is the risk of driving.Therefore, the fault detect of super capacitor is seemed particularly important.
In prior art, with regard to output alarm signal after super capacitor fault being detected.But it is because detection signal is easily interfered, therefore lower to the accuracy rate of the fault detect of super capacitor.
Utility model content
Embodiment of the present utility model provides a kind of super capacitor failure detector, to improve the accuracy rate of the fault detect to super capacitor.
For achieving the above object, embodiment of the present utility model adopts following technical scheme:
The utility model provides a kind of super capacitor failure detector, comprise: for connect the output interface of super capacitor detection signal input filter circuit and for export according to the history of described input filter circuit and the processor circuit of super capacitor fault diagnosis is carried out in current output, described input filter circuit is electrically connected with described processor circuit.
Super capacitor failure detector as above also comprises: for receive described processor circuit described super capacitor detection signal is processed after the communication interface circuit of packing data, described communication interface circuit is connected with described processor circuit, is also connected with controller.
In super capacitor failure detector as above, described controller is the main control PLC of wind power generating set.
Also comprise in super capacitor failure detector as above: for carrying out the input interface circuit of level conversion to the output of described input filter circuit, described input interface circuit is electrically connected with described input filter circuit and described processor circuit respectively; For carrying out the output interface circuit of level conversion to the output of described processor circuit, described output interface circuit is electrically connected with described processor circuit; For showing the mark of fault super capacitor and the display circuit of corresponding failure type according to the control signal of described processor circuit, described display circuit is electrically connected with described processor circuit; And/or for carrying out the reset circuit controlled that resets to described processor circuit, described reset circuit is electrically connected with described processor circuit.
Also power circuit is comprised in super capacitor failure detector as above, described power circuit is connected with described processor circuit and described communication interface circuit, is also connected with described input interface circuit, described output interface circuit, described display circuit and/or described reset circuit.
In super capacitor failure detector as above, described power circuit comprises: the power supply stabilization circuit connected successively, the first power voltage step down circuit, electric source filter circuit and second source reduction voltage circuit, described electric source filter circuit is also electrically connected with described processor circuit and described input interface circuit respectively, and described second source reduction voltage circuit is electrically connected with described processor circuit and described input interface circuit; Described second source reduction voltage circuit is also electrically connected with described output interface circuit, described communication interface circuit, described display circuit and described reset circuit respectively.
In super capacitor failure detector as above, described input interface circuit comprises: for isolating multichannel overvoltage detection signal and the overvoltage signal input interface circuit of level conversion process, for isolating multichannel excess temperature detection signal and the excess temperature signal input interface circuit of level conversion process, with for isolating multichannel error-polarity connection detection signal and the error-polarity connection signal input interface circuit of level conversion process, wherein: described overvoltage signal input interface circuit, described excess temperature signal input interface circuit and described error-polarity connection signal input interface circuit all with described input filter circuit, described processor circuit and the electrical connection of described power circuit.
In super capacitor failure detector as above, described output interface circuit comprises: the over voltage alarm signal for exporting described processor circuit is isolated and the overvoltage signal output interface circuit of level conversion process, overtemperature alarm signal for exporting described processor circuit is isolated and level conversion process excess temperature signal output interface circuit, isolate with the error-polarity connection alerting signal for exporting described processor circuit and the error-polarity connection signal output interface circuit of level conversion process, wherein: described overvoltage signal output interface circuit, described excess temperature signal output interface circuit and described error-polarity connection signal output interface circuit are all electrically connected with described processor circuit and described power circuit.
In super capacitor failure detector as above, described display circuit comprises: the first switching device, second switch device, for showing the first display device of super capacitor mark and the second display part for showing fault corresponding types of fault, wherein: described first switching device respectively with described power circuit, described processor circuit and described first display device electrical connection, described second switch device respectively with described power circuit, described processor circuit and the electrical connection of described second display part, described first display device and described second display part are electrically connected with described processor circuit respectively.
In the super capacitor failure detector of the utility model embodiment, processor circuit generates corresponding alerting signal according to the multi-way detecting signal of multiple super capacitors that are current and that receive before, effectively prevent because of detection signal be interfered cause wrong report, fail to report phenomenon, improve the accuracy rate of the fault detect to super capacitor.
Accompanying drawing explanation
The structural representation of the super capacitor failure detector embodiment that Fig. 1 provides for the utility model;
The structural representation of another embodiment of super capacitor failure detector that Fig. 2 provides for the utility model;
Fig. 3 is the structural representation of power circuit in super capacitor failure detector embodiment illustrated in fig. 2;
Fig. 4 is the circuit diagram of a kind of implementation of the power circuit shown in Fig. 3;
Fig. 5 is the structural representation of input interface circuit in super capacitor failure detector embodiment illustrated in fig. 2;
Fig. 6 a is the partial circuit figure of a kind of implementation of the input interface circuit shown in Fig. 5;
Fig. 6 b is the partial circuit figure of a kind of implementation of the input interface circuit shown in Fig. 5;
Fig. 6 c is the partial circuit figure of a kind of implementation of the input interface circuit shown in Fig. 5;
Fig. 7 is the structural representation of output interface circuit in super capacitor failure detector embodiment illustrated in fig. 2;
Fig. 8 is the circuit diagram of a kind of implementation of the output interface circuit shown in Fig. 7;
Fig. 9 is the circuit diagram of a kind of implementation of processor circuit in super capacitor failure detector embodiment illustrated in fig. 2;
Figure 10 is the structural representation of communication interface circuit in super capacitor failure detector embodiment illustrated in fig. 2;
Figure 11 is the structural representation of power supply processing circuit in the communication interface circuit shown in Figure 10;
Figure 12 a is the partial circuit figure of a kind of implementation of the communication interface circuit shown in Figure 10;
Figure 12 b is the partial circuit figure of a kind of implementation of the communication interface circuit shown in Figure 10;
Figure 13 is the structural representation of display circuit in super capacitor failure detector embodiment illustrated in fig. 2;
Figure 14 is the circuit diagram of a kind of implementation of the display circuit shown in Figure 13;
Figure 15 is the circuit diagram of a kind of implementation of reset circuit in super capacitor failure detector embodiment illustrated in fig. 2;
Wherein: 11-input filter circuit; 12-processor circuit; 21-power circuit; 22-input interface circuit; 23-output interface circuit; 24-communication interface circuit; 25-display circuit; 26-reset circuit; 31-power supply stabilization circuit; 32-first power voltage step down circuit; 33-electric source filter circuit; 34-second source reduction voltage circuit; 51-overvoltage signal input interface circuit; 52-excess temperature signal input interface circuit; 53-error-polarity connection signal input interface circuit; 71-overvoltage signal output interface circuit; 72-excess temperature signal output interface circuit; 73-error-polarity connection signal output interface circuit; 101-power supply processing circuit; 102-communication level conversion buffer circuit; 111-communicates reduction voltage circuit; 112-communicates filtering circuit; 113-communicates mu balanced circuit; 131-first switching device; 132-second switch device; 133-first display device; 134-second display part.
Embodiment
Be described in detail below in conjunction with the super capacitor failure detector of accompanying drawing to the utility model embodiment.
Embodiment one
The structural representation of the super capacitor failure detector embodiment that Fig. 1 provides for the utility model.As shown in Figure 1, the super capacitor failure detector of the present embodiment specifically can comprise: for connect the output interface of super capacitor detection signal input filter circuit 11 and for export according to the history of input filter circuit 11 and the processor circuit 12 of super capacitor fault diagnosis is carried out in current output, input filter circuit 11 is electrically connected with processor circuit 12.
Concrete, detection signal specifically can comprise overvoltage detection signal, excess temperature detection signal and error-polarity connection detection signal.Suppose that the quantity of super capacitor is 8, pass by pressure detection signal, due to each super capacitor correspondence one and pass by warm detection signal and a road error-polarity connection detection signal, the 24 road detection signals (8 pass by pressure detection signal, 8 passes by warm detection signal and 8 road error-polarity connection detection signals) that therefore input filter circuit 11 inputs outside carry out filtering process respectively and export processor circuit 12 to.The multi-way detecting signal that processor circuit 12 exports according to input filter circuit 11 that is current and that receive before carries out fault detect to super capacitor, when detect there is fault time, can generate multiple alarm signal and export warn to reach.Such as processor circuit 12 according to input filter circuit 11 that is current and that receive before export 8 pass by pressure detection signal detect super capacitor storage failure time, over voltage alarm signal can be generated, according to current and that receive before input filter circuit 11 export 8 pass by temperature detector survey input have super capacitance stores fault time, overtemperature alarm signal can be generated, when detecting super capacitor storage failure according to 8 road error-polarity connection detection signals of input interface circuit 11 output that is current and that receive before, error-polarity connection alerting signal can be generated, then these alerting signals are exported to outside, corresponding measure is taked in time for testing staff.
Input filter circuit 11 is specifically as follows existing various LC wave filter, can carry out filtering process respectively to ensure the accuracy of detection signal, avoid interference the multi-way detecting signal of input.
Processor circuit 12 can scan the input port of 24 road detection signals as above in timing, and sets 24 registers and be used for the malfunction of preservation 24 road detection signal, and such as low level indicates fault, and high level represents non-fault.When being consecutively detected same road detection signal (namely appearing at the detection signal in same register), such as corresponding with the super capacitor being numbered 2 overvoltage detection signal, when the number of times presenting low level (namely having fault) state exceedes set point number (such as 3 times), judge that overvoltage fault appears in the super capacitor being numbered 2, and generate the over voltage alarm signal output representing overvoltage fault.When above-mentioned 8 pass by pressure detection signal present high level (i.e. non-fault) state or a certain pass by number of times that pressure detection signal presents high level state continuously exceed set point number (such as 5 times) time, then generation indicates state normal signal without overvoltage fault and exports.The process generating overtemperature alarm signal and error-polarity connection alerting signal is the same, repeats no more herein.
In the super capacitor failure detector of the present embodiment, processor circuit is to after the detection signal comprehensive descision of super capacitor that is current and that receive before, carry out fault detect, generate failure detection result, effectively prevent because of detection signal be interfered cause wrong report, fail to report phenomenon, improve the accuracy rate of the fault detect to super capacitor.
Embodiment two
The structural representation of another embodiment of super capacitor failure detector that Fig. 2 provides for the utility model.As shown in Figure 2, the super capacitor failure detector of the present embodiment can also comprise on the basis of super capacitor failure detector embodiment illustrated in fig. 1: the communication interface circuit 24 of the packing data after processing for receiving processor circuit 12 pairs of super capacitor detection signals, communication interface circuit 24 is connected with processor circuit 12, is also connected with controller.
Particularly, after processor circuit 12 generates testing result according to multi-way detecting signal that is current and that receive before, by testing result as alerting signal or state normal signal export communication interface circuit 24 to, thus controller can be sent to, carry out control treatment for controller.While receiving at communication interface circuit 24 information transmitting testing result, the testing result signal also comprised processor circuit 12 exports carries out protocol conversion process and exports.Described controller can be the main control PLC of wind power generating set.
Such as, processor circuit 12 generates testing result signal according to the fault condition detection signal determined and exports communication interface circuit 24 to.The testing result signal that communication interface circuit 24 pairs of processor circuits 12 export carries out protocol conversion process, namely the data of the form that communication protocol needs are converted to, packed data are sent to outside programmable logic controller (PLC) (ProgrammableLogicController is called for short PLC) etc.Communication interface circuit 24 specifically can be based on controller local area network's (ControllerAreaNetwork is called for short CAN) bus communication interface circuit of the agreements such as CANopen, the RS485 bus communication interface circuit, RS232 bus communication interface circuit etc. based on Modbus agreement.
Further, the super capacitor failure detector of the present embodiment can also comprise on the basis of super capacitor failure detector embodiment illustrated in fig. 1: for carrying out the input interface circuit 22 of level conversion to the output of input filter circuit 11, input interface circuit 22 is electrically connected with input filter circuit 11 and processor circuit 12 respectively; For carrying out the output interface circuit 23 of level conversion to the output of processor circuit 12, output interface circuit 23 is electrically connected with processor circuit 12; For showing the mark of fault super capacitor and the display circuit 25 of corresponding failure type according to the control signal of processor circuit 12, display circuit 25 is electrically connected with processor circuit 12, and/or, for carrying out the reset circuit 26 controlled that resets to processor circuit 12, reset circuit 26 is electrically connected with processor circuit 12.
Wherein, reset circuit 26 is specifically as follows watchdog circuit, exports reset signal when program fleet or hardware crash, reset processing is carried out to processor circuit 12, such as by register clearing etc., make processor circuit 12 return to original state, avoid program fleet or hardware to crash.
Wherein, output interface circuit 23, carries out level conversion process for what export processor circuit 12 and exports as alerting signal (over voltage alarm signal, overtemperature alarm signal and error-polarity connection alerting signal).
Further, as shown in Figure 2, above-mentioned super capacitor failure detector also comprises power circuit 21, and power circuit 21 is connected with processor circuit 12 and communication interface circuit 24, is also connected with input interface circuit 22, output interface circuit 23, display circuit 25 and/or reset circuit 26.Power circuit 21 is for powering for foregoing circuit unit.
Following content will be specifically described power circuit 21, input interface circuit 22, output interface circuit 23, communication interface circuit 24, display circuit 25.
As shown in Figure 3, power circuit 21 specifically can comprise: power supply stabilization circuit 31, the first power voltage step down circuit 32, electric source filter circuit 33 and the second source reduction voltage circuit 34 that connect successively.Electric source filter circuit 33 is also electrically connected with processor circuit 12 and input interface circuit 22 respectively, and second source reduction voltage circuit 34 is electrically connected with processor circuit 12 and input interface circuit 22.
Particularly, power supply stabilization circuit 31, for remaining on the first power supply signal of input within the scope of setting voltage.First power voltage step down circuit 32, the electric signal for exporting power supply stabilization circuit 31 is isolated and step-down process obtains second source signal.Electric source filter circuit 33, carries out filtering process for the second source signal exported the first power voltage step down circuit 32, and exports second source reduction voltage circuit 34, input interface circuit 22 and processor circuit 12 respectively to.Second source reduction voltage circuit 34, carry out step-down process for the second source signal after the filtering process that exports electric source filter circuit 33 and obtain the 3rd power supply signal, and export input interface circuit 22, processor circuit 12, output interface circuit 23, communication interface circuit 24, display circuit 25 and reset circuit 26 respectively to.
Fig. 4 is the circuit diagram of a kind of implementation of the power circuit shown in Fig. 3.As shown in Figure 4, power supply stabilization circuit 31 comprises: gas-discharge tube D7, resistance R10 and R11, fuse F1 and F2, transient voltage suppressor diode D6, D8 and D9, diode D5 and electrochemical capacitor C17, and the first power supply signal for the 24V inputted outside remains on about 24V.First power voltage step down circuit 32 comprises DC/DC insulating power supply chip U6, for isolate first power supply signal of 24V and step-down process obtains the second source signal of 5V.Electric source filter circuit 33 comprises: electric capacity C15, C12, C13, C14 and C16, inductance L 1 and resistance R9, for carrying out filtering process to the second source signal of 5V, and export second source reduction voltage circuit 34, input interface circuit 22 and processor circuit 12 to by+5VDC port.Second source reduction voltage circuit 34 comprises electric capacity C21, C20, C22, C19 and level transferring chip U16, for carrying out the 3rd power supply signal that step-down process obtains 3.3V to the second source signal of the 5V after filtering process, and export input interface circuit 22, processor circuit 12, output interface circuit 23, communication interface circuit 24, display circuit 25 and reset circuit 26 to by+3.3V port.
In addition, second source reduction voltage circuit 34 is also electrically connected with output interface circuit 23, communication interface circuit 24, display circuit 25 and reset circuit 26 respectively, for powering for these circuit units.
As shown in Figure 5, input interface circuit 22 can specifically comprise: for isolating multichannel overvoltage detection signal and the overvoltage signal input interface circuit 51 of level conversion process, for isolating multichannel excess temperature detection signal and the excess temperature signal input interface circuit 52 of level conversion process, with for isolating multichannel error-polarity connection detection signal and the error-polarity connection signal input interface circuit 53 of level conversion process, wherein: overvoltage signal input interface circuit 51, excess temperature signal input interface circuit 52 and error-polarity connection signal input interface circuit 53 all with input filter circuit 11, processor circuit 12 and power circuit 21 are electrically connected, and the signal obtained after processing the most at last exports processor circuit 12 to.
Fig. 6 a, 6b and 6c are respectively the specific implementation circuit of overvoltage signal input interface circuit 51 in input interface circuit 22, excess temperature signal input interface circuit 52 and error-polarity connection signal input interface circuit 53.
As shown in Figure 6 a, overvoltage signal input interface circuit 51 comprises resistance RS2, RS3 and level transferring chip U3, multichannel overvoltage detection signal Module-1-V ~ Module-8-V for the multiple super capacitors to input isolates respectively and level conversion process obtains multichannel overvoltage detection signal OVER-V1 ~ OVER-V8, and exports processor circuit 12 to by OVER-V [1.8] port.+ 5VDC is the input port of the second source signal that power circuit 21 exports, and+3.3V is the input port of the 3rd power supply signal that power circuit 21 exports.When overvoltage detection signal Module-1-V ~ Module-8-V is low level 0V, indicate overvoltage fault, when overvoltage detection signal Module-1-V ~ Module-8-V is high level 5V, indicate without overvoltage fault.Accordingly, when overvoltage detection signal OVER-V1 ~ OVER-V8 is low level 0V, indicate overvoltage fault, when overvoltage detection signal OVER-V1 ~ OVER-V8 is high level 3.3V, indicate without overvoltage fault.
As shown in Figure 6 b, excess temperature signal input interface circuit 52 comprises resistance RS4, RS5 and level transferring chip U4, multichannel excess temperature detection signal Module-1-T ~ Module-8-T for the multiple super capacitors to input isolates respectively and level conversion process obtains multichannel excess temperature detection signal OVER-T1 ~ OVER-T8, and exports processor circuit 12 to by OVER-T [1.8] port.+ 5VDC is the input port of the second source signal that power circuit 21 exports, and+3.3V is the input port of the 3rd power supply signal that power circuit 21 exports.When to have served as warm detection signal Module-1-T ~ Module-8-T be low level 0V, indicate excess temperature fault, when to have served as warm detection signal Module-1-T ~ Module-8-T be high level 5V, indicate without excess temperature fault.Accordingly, when to have served as warm detection signal OVER-T1 ~ OVER-T8 be low level 0V, indicate excess temperature fault, when to have served as warm detection signal OVER-T1 ~ OVER-T8 be high level 3.3V, indicate without excess temperature fault.
As fig. 6 c, error-polarity connection signal input interface circuit 53 comprises resistance RS6, RS7 and level transferring chip U5, multichannel error-polarity connection detection signal Module-1-R ~ Module-8-R for the multiple super capacitors to input isolates respectively and level conversion process obtains multichannel error-polarity connection detection signal OVER-R1 ~ OVER-R8, and exports processor circuit 12 to by OVER-R [1.8] port.+ 5VDC is the input port of the second source signal that power circuit 21 exports, and+3.3V is the input port of the 3rd power supply signal that power circuit 21 exports.When error-polarity connection detection signal Module-1-R ~ Module-8-R is low level 0V, indicate reversal connection fault, when error-polarity connection detection signal Module-1-R ~ Module-8-R is high level 5V, indicate without reversal connection fault.Accordingly, when error-polarity connection detection signal OVER-R1 ~ OVER-R8 is low level 0V, indicate reversal connection fault, when error-polarity connection detection signal OVER-R1 ~ OVER-R8 is high level 3.3V, indicate without reversal connection fault.
Certainly, level height also can adjust as required with the relation of above-mentioned various malfunction.
Further, as shown in Figure 7, output interface circuit 23 specifically can comprise: the over voltage alarm signal for exporting processor circuit 12 is isolated and the overvoltage signal output interface circuit 71 of level conversion process, overtemperature alarm signal for exporting processor circuit 12 is isolated and level conversion process excess temperature the signal output interface circuit 72 and error-polarity connection alerting signal for exporting processor circuit is isolated and the error-polarity connection signal output interface circuit 73 of level conversion process, wherein: overvoltage signal output interface circuit 71, excess temperature signal output interface circuit 72 and error-polarity connection signal output interface circuit 73 are all electrically connected with processor circuit 12 and power circuit 21.
Fig. 8 is the circuit diagram of a kind of implementation of the output interface circuit shown in Fig. 7.As shown in Figure 8, overvoltage signal output interface circuit 71 comprises level transferring chip U7, resistance R12 and R13, diode D10 and D11 and electric capacity C18, for the over voltage alarm signal VNOUT1 exported by VNOUT [1.6] port accepts processor circuit 12, after isolation and level conversion process, obtain over voltage alarm signal OUTPUT1 and exported by OUTPUT1 port.+ 3.3V is the input port of the 3rd power supply signal of the 3.3V that power circuit 21 exports, and+24VDC is the input port of the power supply signal of outside 24V.When overvoltage alerting signal OUTPUT1 is low level 0V, indicate overvoltage fault.Accordingly, when overvoltage alerting signal OUTPUT1 is high level 24V, indicate without overvoltage fault.Optionally, the external power source signal of 12V or 5V can also be adopted as working power.
Excess temperature signal output interface circuit 72 comprises level transferring chip U8, resistance R14 and R15, diode D12 and D13 and electric capacity C19, for the overtemperature alarm signal VNOUT2 exported by VNOUT [1.6] port accepts processor circuit 12, after isolation and level conversion process, obtain overtemperature alarm signal OUTPUT2 and exported by OUTPUT2 port.+ 3.3V is the input port of the 3rd power supply signal that power circuit 21 exports, and+24VDC is the input port of outside 24V power supply signal.When excess temperature alerting signal OUTPUT2 is low level 0V, indicate excess temperature fault.Accordingly, when excess temperature alerting signal OUTPUT2 is high level 24V, indicate without excess temperature fault.
Error-polarity connection signal output interface circuit 73 comprises level transferring chip U9, resistance R16 and R17, diode D14-D15 and electric capacity C20, for the error-polarity connection alerting signal VNOUT3 exported by VNOUT [1.6] port accepts processor circuit 12, after isolation and level conversion process, obtain error-polarity connection alerting signal OUTPUT3 and exported by OUTPUT3 port.+ 3.3V is the input port of the 3rd power supply signal that power circuit 21 exports, and+24VDC is the input port of outside 24V power supply signal.When error-polarity connection alerting signal OUTPUT3 is low level 0V, indicate reversal connection fault.Accordingly, when excess temperature alerting signal OUTPUT3 is high level 24V, indicate without reversal connection fault.
Further, Fig. 9 is a kind of specific implementation circuit diagram of above-mentioned processor circuit 12.As shown in Figure 9, multichannel overvoltage detection signal OVER-V1 ~ OVER-V8 that the processor circuit 12 be made up of chip U1 etc. is exported by the overvoltage signal input interface circuit 51 in OVER-V [1.8] port accepts input interface circuit 22, and generate one and pass by pressure alerting signal VNOUT1 and export output interface circuit 23 to by VNOUT [1.6] port; By multichannel excess temperature detection signal OVER-T1 ~ OVER-T8 that excess temperature signal input interface circuit 52 in OVER-T [1.8] port accepts input interface circuit 22 exports, and generate one and pass by warm alerting signal VNOUT2 and export output interface circuit 23 to by VNOUT [1.6] port; By multichannel error-polarity connection detection signal OVER-R1 ~ OVER-R8 that error-polarity connection signal input interface circuit 53 in OVER-R [1.8] port accepts input interface circuit 22 exports, and generate a road error-polarity connection alerting signal VNOUT3 and export output interface circuit 23 to by VNOUT [1.6] port.When overvoltage alerting signal VNOUT1, overtemperature alarm signal VNOUT2 or error-polarity connection alerting signal VNOUT3 are low level (as 0V), indicate overvoltage fault, excess temperature reversal connection fault or reversal connection fault.Accordingly, when overvoltage alerting signal VNOUT1, overtemperature alarm signal VNOUT2 or error-polarity connection alerting signal VNOUT3 are high level (as 3.3V), indicate without overvoltage fault, excess temperature reversal connection fault or reversal connection fault.+ 5VDC is the input port of the second source signal of the 5V that power circuit 21 exports, and+3.3V is the input port of the 3rd power supply signal of the 3.3V that power circuit 21 exports, and RESET is the input port of the reset signal that reset circuit 26 exports.
The processor circuit 12 be made up of chip U1 etc. also generates testing result signal UCAIRXD and UCAITXD according to multichannel overvoltage detection signal OVER-V1 ~ OVER-V8, multichannel excess temperature detection signal OVER-T1 ~ OVER-T8 and multichannel error-polarity connection detection signal OVER-R1 ~ OVER-R8 and exports communication interface circuit 24 to respectively by UCAIRXD port and UCAITXD port.
The processor circuit 12 be made up of chip U1 etc. is also according to multichannel overvoltage detection signal OVER-V1 ~ OVER-V8, multichannel excess temperature detection signal OVER-T1 ~ OVER-T8 and multichannel error-polarity connection detection signal OVER-R1 ~ OVER-R8 generates the first switch controlling signal LED-SWITCH1, second switch control signal LED-SWITCH2 and Multiple-shower control signal Display0 ~ Display7 is respectively by LED-SWITCH1 port, LED-SWITCH2 port and Display [0.7] port export display circuit 25 to.First switch controlling signal LED-SWITCH1, second switch control signal LED-SWITCH2 and Multiple-shower control signal Display0 ~ Display7 are 0 or 1.
Further, as shown in Figure 10, above-mentioned communication interface circuit 24 specifically can comprise: power supply processing circuit 101 and communication level conversion buffer circuit 102.Wherein: communication level conversion buffer circuit 102 is electrically connected with processor circuit 12, power circuit 21 and power supply processing circuit 101 respectively.Communication level conversion buffer circuit 102, the testing result signal for exporting processor circuit 12 is isolated and level conversion process.Power supply processing circuit 101, for providing working power for communication level conversion buffer circuit 102.Power circuit 21 is also for providing working power for communication level conversion buffer circuit 102.
Further, Figure 11 is the structural representation of power supply processing circuit in the communication interface circuit shown in Figure 10.As shown in figure 11, power supply processing circuit 101 specifically can comprise: communication reduction voltage circuit 111, communication filtering circuit 112 and the mu balanced circuit 113 that communicates, wherein: communication filtering circuit 112 is electrically connected with the mu balanced circuit 113 that communicates with the reduction voltage circuit 111 that communicates respectively, communication mu balanced circuit 113 is changed buffer circuit 102 with communication level and is electrically connected.Communication reduction voltage circuit 111, obtains the 5th power supply signal for carrying out step-down process to the 4th power supply signal of input.Communication filtering circuit 112, carries out filtering process for the 5th power supply signal exported communication reduction voltage circuit 111.Communication mu balanced circuit 113, for remaining on the 5th power supply signal after the filtering process that exports of communication filtering circuit 112 within the scope of setting voltage.
Concrete, the circuit diagram that Figure 12 a and Figure 12 b is a kind of implementation of the communication interface circuit shown in Figure 10.As figure 12 a shows, communication level conversion buffer circuit 102 comprises level transferring chip U18, electric capacity C28 and agreement level transferring chip U19, for testing result signal UCAIRXD and UCAITXD exported by UCAIRXD port and UCAITXD port accepts processor circuit 12, carry out isolating and exporting outside PLC to by 1,2 ports of connector J7 after level conversion process.+ 5.0V
-vDC is the input port of the 5th power supply signal of the 5V that power supply processing circuit 101 exports, and+3.3V is the input port of the 3rd power supply signal of the 3.3V that power circuit exports.
As shown in Figure 12b, communication reduction voltage circuit 111 comprises electric capacity C26, C27 and C25, level transferring chip U17, and the 4th power supply signal for the 24V inputted outside carries out the 5th power supply signal that step-down process obtains 5V.Communication filtering circuit 112 comprises magnetic bead FB1, for carrying out filtering process to the 5th power supply signal of 5V.Communication mu balanced circuit 113 comprises electric capacity C23, C24, resistance R41 and R42 and transient voltage suppressor diode D21, for the 5th power supply signal of the 5V after filtering process is remained on about 5V, and passes through+5.0V
-vDC port exports communication level conversion buffer circuit 102 to.+ 24VDC is the input port of the 4th power supply signal of the 24V of outside input.
Further, as shown in figure 13, above-mentioned display circuit 25 specifically can comprise: the first switching device 131, second switch device 132, for showing the first display device 133 of super capacitor mark and the second display part 132 for showing fault corresponding types of fault, wherein: the first switching device 131 respectively with power circuit 21, processor circuit 12 and the first display device 133 are electrically connected, second switch device 132 respectively with power circuit 21, processor circuit 12 and second display part 134 are electrically connected, first display device 133 and second display part 132 are electrically connected with processor circuit 12 respectively.
Particularly, the first switching device 131, under the control of the first switch controlling signal that exports at processor circuit 12, is switched on or switched off the electrical connection between power circuit 21 and the first display device 133.Second switch device 132, under the control of second switch control signal that exports at processor circuit 12, is switched on or switched off the electrical connection between power circuit 21 and second display part 134.First display device 133, for when connecting the electrical connection with power circuit 21 by the first switching device 131, shows the numbering that the super capacitor of fault is corresponding under the control of the Multiple-shower control signal of processor circuit 12 output.Second display part 134, for when connecting the electrical connection with power circuit 21 by second switch device 132, shows the numbering of type corresponding to fault under the control of the Multiple-shower control signal of processor circuit 12 output.Such as, when overvoltage fault appears in the super capacitor being numbered 2, the first display device 133 shows numbering 2 corresponding to the super capacitor of fault, and second display part 134 shows the numbering 1 of type corresponding to overvoltage fault.
Display circuit 25 specifically can be two or multidigit nixie tube, LCDs etc.
Concrete, Figure 14 is the circuit diagram of a kind of implementation of the display circuit shown in Figure 13.As shown in figure 14, triode Q1 as the first switching device 131, by LED-SWITCH1 port accepts processor circuit 12 export the first switch controlling signal LED-SWITCH1.Triode Q2 as second switch device 132, by LED-SWITCH2 port accepts processor circuit 12 export second switch control signal LED-SWITCH2.Charactron DS1 is as the first display device 133, and the Multiple-shower control signal Display0 ~ Display7 exported by Display [0.7] port accepts processor circuit 12, shows the numbering that the super capacitor of fault is corresponding.Charactron DS2 is as second display part 134, and the Multiple-shower control signal Display0 ~ Display7 exported by Display [0.7] port accepts processor circuit 12, shows the numbering of type corresponding to fault.+ 3.3V is the input port of the 3rd power supply signal of the 3.3V that power circuit 21 exports.When the first switch controlling signal LED-SWITCH1 is high level 1, triode Q1 closes thus electrical connection between interrupting power circuit 21 and charactron DS1, and charactron DS1 does not show any data.When the first switch controlling signal LED-SWITCH1 is low level 0, triode Q1 opens thus the electrical connection switched on power between circuit 21 and charactron DS1, and charactron DS1 shows numbering corresponding to the super capacitor of fault under the control of Multiple-shower control signal Display0 ~ Display7.When second switch control signal LED-SWITCH2 is high level 1, triode Q2 closes thus electrical connection between interrupting power circuit 21 and charactron DS2, and charactron DS2 does not show any data.When second switch control signal LED-SWITCH2 is low level 0, triode Q2 opens thus the electrical connection switched on power between circuit 21 and charactron DS2, and charactron DS2 shows the numbering of type corresponding to fault under the control of Multiple-shower control signal Display0 ~ Display7.
Further, Figure 15 is the circuit diagram of a kind of implementation of above-mentioned reset circuit.As shown in figure 15, the reset circuit 26 be made up of chip U2 and toggle switch S1 exports reset signal to processor circuit 12 by RESET port.+ 3.3V is the input port of the 3rd power supply signal of the 3.3V that power circuit exports.
In the super capacitor failure detector of the present embodiment, processor circuit generates corresponding alerting signal, testing result signal and display control signal according to the multi-way detecting signal of multiple super capacitors that are current and that receive before, effectively prevent because of detection signal be interfered cause wrong report, fail to report phenomenon, improve the accuracy rate of the fault detect to super capacitor.
The above; be only embodiment of the present utility model; but protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; change can be expected easily or replace, all should be encompassed within protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with the protection domain of described claim.
Claims (9)
1. a super capacitor failure detector, it is characterized in that, comprise: for connect the output interface of super capacitor detection signal input filter circuit and for export according to the history of described input filter circuit and the processor circuit of super capacitor fault diagnosis is carried out in current output, described input filter circuit is electrically connected with described processor circuit.
2. device according to claim 1, it is characterized in that, also comprise: for receive described processor circuit described super capacitor detection signal is processed after the communication interface circuit of packing data, described communication interface circuit is connected with described processor circuit, is also connected with controller.
3. device according to claim 2, is characterized in that, described controller is the main control PLC of wind power generating set.
4. the device according to Claims 2 or 3, is characterized in that, also comprises:
For carrying out the input interface circuit of level conversion to the output of described input filter circuit, described input interface circuit is electrically connected with described input filter circuit and described processor circuit respectively; For carrying out the output interface circuit of level conversion to the output of described processor circuit, described output interface circuit is electrically connected with described processor circuit; For showing the mark of fault super capacitor and the display circuit of corresponding failure type according to the control signal of described processor circuit, described display circuit is electrically connected with described processor circuit; And/or for carrying out the reset circuit controlled that resets to described processor circuit, described reset circuit is electrically connected with described processor circuit.
5. device according to claim 4, it is characterized in that, also comprise power circuit, described power circuit is connected with described processor circuit and described communication interface circuit, is also connected with described input interface circuit, described output interface circuit, described display circuit and/or described reset circuit.
6. device according to claim 5, is characterized in that, described power circuit comprises:
The power supply stabilization circuit connected successively, the first power voltage step down circuit, electric source filter circuit and second source reduction voltage circuit, described electric source filter circuit is also electrically connected with described processor circuit and described input interface circuit respectively, and described second source reduction voltage circuit is electrically connected with described processor circuit and described input interface circuit; Described second source reduction voltage circuit is also electrically connected with described output interface circuit, described communication interface circuit, described display circuit and described reset circuit respectively.
7. device according to claim 5, it is characterized in that, described input interface circuit comprises: for multichannel overvoltage detection signal is isolated and level conversion process overvoltage signal input interface circuit, for multichannel excess temperature detection signal is isolated and level conversion process excess temperature signal input interface circuit and for isolating multichannel error-polarity connection detection signal and the error-polarity connection signal input interface circuit of level conversion process, wherein:
Described overvoltage signal input interface circuit, described excess temperature signal input interface circuit and described error-polarity connection signal input interface circuit are all electrically connected with described input filter circuit, described processor circuit and described power circuit.
8. device according to claim 5, it is characterized in that, described output interface circuit comprises: the over voltage alarm signal for exporting described processor circuit isolate and level conversion process overvoltage signal output interface circuit, to isolate for the overtemperature alarm signal exported described processor circuit and level conversion process excess temperature signal output interface circuit and the error-polarity connection alerting signal for exporting described processor circuit is isolated and the error-polarity connection signal output interface circuit of level conversion process, wherein:
Described overvoltage signal output interface circuit, described excess temperature signal output interface circuit and described error-polarity connection signal output interface circuit are all electrically connected with described processor circuit and described power circuit.
9. device according to claim 5, it is characterized in that, described display circuit comprises: the first switching device, second switch device, for showing first display device of super capacitor mark of fault and second display part for showing fault corresponding types, wherein:
Described first switching device is electrically connected with described power circuit, described processor circuit and described first display device respectively, described second switch device is electrically connected with described power circuit, described processor circuit and described second display part respectively, and described first display device and described second display part are electrically connected with described processor circuit respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520931198.5U CN205120876U (en) | 2015-11-19 | 2015-11-19 | Fault detection apparatus for super capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520931198.5U CN205120876U (en) | 2015-11-19 | 2015-11-19 | Fault detection apparatus for super capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205120876U true CN205120876U (en) | 2016-03-30 |
Family
ID=55576471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520931198.5U Active CN205120876U (en) | 2015-11-19 | 2015-11-19 | Fault detection apparatus for super capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205120876U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105277831A (en) * | 2015-11-19 | 2016-01-27 | 北京天诚同创电气有限公司 | Super capacitor fault detection device |
-
2015
- 2015-11-19 CN CN201520931198.5U patent/CN205120876U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105277831A (en) * | 2015-11-19 | 2016-01-27 | 北京天诚同创电气有限公司 | Super capacitor fault detection device |
| CN105277831B (en) * | 2015-11-19 | 2018-10-23 | 北京天诚同创电气有限公司 | super capacitor fault detection device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101738565B (en) | Adaptive fault indicator | |
| CN202795632U (en) | Two-wire electric fire monitoring system | |
| CN103472309B (en) | Insulation Inspection Device for Direct-Current System and method | |
| CN106443350B (en) | Fault-line selecting method, device and the equipment of arc suppression coil earthing system | |
| CN111208388A (en) | Ship insulation monitoring and fault positioning embedded device | |
| CN106646079A (en) | Online direct-current grounding monitoring system for power distribution automation terminal | |
| CN106569096B (en) | A kind of tuning on-line method of power distribution network single-phase fault | |
| CN205120876U (en) | Fault detection apparatus for super capacitor | |
| CN105277831A (en) | Super capacitor fault detection device | |
| CN106199235A (en) | A kind of island detection method based on fundamental frequency with switching frequency time impedance | |
| CN206281924U (en) | A kind of distribution power automation terminal DC earthing on-line monitoring system | |
| CN101718830A (en) | Direct current ground fault detection device based on LabVIEW software and wavelet transform | |
| CN104142648A (en) | Management and control terminal of urban rail traffic low-voltage power distribution system | |
| CN204535758U (en) | Power transmission and transforming equipment integration monitoring device | |
| CN201294152Y (en) | Microcomputer monitoring and harmony-eliminating device for voltage transformator | |
| CN110943542A (en) | Storage device applied to data of high-voltage direct-current power transmission system | |
| CN205724867U (en) | A kind of small current grounding system single-phase grounding selecting protection device | |
| CN204666765U (en) | A kind of low-voltage alternating-current electrical network on-Line Monitor Device | |
| CN104535894B (en) | Earth fault line selection method and device under the double-bus method of operation | |
| CN204966989U (en) | Take switch board safety monitoring device of temperature detection | |
| CN203455412U (en) | DC system insulation monitoring device | |
| CN107651550B (en) | A kind of staircase malfunction monitoring and prior-warning device | |
| CN203630273U (en) | Bridge-type direct-current fault monitoring alarm | |
| CN205404697U (en) | Multi -functional high voltage insulation on -line monitoring device | |
| CN201854085U (en) | Bus coupler segmented monitoring protection and comprehensive self-automatic input device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |