CN205105380U - Compression limit circuit - Google Patents
Compression limit circuit Download PDFInfo
- Publication number
- CN205105380U CN205105380U CN201520881216.3U CN201520881216U CN205105380U CN 205105380 U CN205105380 U CN 205105380U CN 201520881216 U CN201520881216 U CN 201520881216U CN 205105380 U CN205105380 U CN 205105380U
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- China
- Prior art keywords
- resistance
- triode
- pin
- operational amplifier
- effect transistor
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- Expired - Fee Related
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- 230000006835 compression Effects 0.000 title claims abstract description 25
- 238000007906 compression Methods 0.000 title claims abstract description 25
- 230000005669 field effect Effects 0.000 claims abstract description 23
- 230000000694 effects Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
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- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Abstract
The utility model provides a compression limit circuit, belongs to the sound system field of making, including resistance R1 -R8, operational amplifier OP, field effect transistor Q1, triode Q2 -Q3 and electric capacity C1, pin 2 with operational amplifier OP after resistance R2 establishes ties with resistance R3 is connected, operational amplifier OP's 3 ground connection of pin, field effect transistor Q1's drain electrode is connected between resistance R2 and resistance R3, source electrode ground connection, and the grid is connected with triode Q2's collecting electrode behind resistance R5, resistance R8 one end sets up between field effect transistor Q1 and resistance R5, electric capacity C1 and resistance R8 are parallelly connected, triode Q2's base is connected with triode Q3's collecting electrode, triode Q3's base is connected between the resistance R4 and resistance R7 that establish ties, amplitude limiting accuse through resistance R4 and resistance R7 is pressed, and triode Q2 and the enlarged of triode Q3 switch on, reaches the regulation of resistance R2 and field effect transistor Q1 amplitude limiting and realizes handling to incoming signal's compression amplitude limiting, and control range is wide, and the distortion is little, and circuit structure is simple, and is with low costs, is suitable for popularization and application.
Description
Technical field
The utility model belongs to sound system and manufactures field, particularly relates to a kind of compression amplitude limiter circuit.
Background technology
Along with the continuous lifting of living standard, various stereo set has entered into the life of people, in stereo component system, the dynamic range of general program source signal is very wide, the dynamic range of audio system equipment is much smaller by comparison, as symphony can reach 100dB, and sound reinforcement system employing is analog machine, its dynamic range is only at 80dB, this does not cause with regard to requiring to decay to the actual level of sound source and produces too drastic distortion, along with the fast development of economy, people are more and more higher for stereo set requirement in this respect, compression amplitude limiter circuit is before can not meet the demand of people.
Summary of the invention
The utility model is intended to solve the problem, and provides a kind of compression amplitude limiter circuit.
One compression amplitude limiter circuit described in the utility model, comprises resistance R1-R8, operational amplifier OP, field effect transistor Q1, triode Q2-Q3 and electric capacity C1; Described operational amplifier OP is provided with pin one, pin two and pin 3, and wherein, pin one is output, pin two is inverting input, pin 3 is normal phase input end; It is characterized in that: one end external circuits input of described resistance R2, be connected with the pin two of operational amplifier OP after the other end and resistance R3 connect; Pin 3 ground connection of operational amplifier OP; Between the pin two that described resistance R1 is arranged at operational amplifier OP and pin one; The pin one external circuits output of described operational amplifier OP; The drain electrode of described field effect transistor Q1 is connected between resistance R2 and resistance R3, source ground, and grid is connected with the collector electrode of triode Q2 after resistance R5; Resistance R8 one end is arranged between field effect transistor Q1 and resistance R5, other end connection-VSS; Electric capacity C1 is in parallel with resistance R8; Emitter access+VCC after resistance R6 of triode Q2, base stage is connected with the collector electrode of triode Q3; The grounded emitter of triode Q3, base stage is connected between the resistance R4 of series connection and resistance R7; The other end of resistance R4 is connected with the pin one of operational amplifier OP; The other end ground connection of resistance R7.
Compression amplitude limiter circuit described in the utility model, is characterized in that: described field effect transistor Q1 is 2SK246 field effect transistor.
Compression amplitude limiter circuit described in the utility model, is characterized in that: described triode Q2 is PNP type triode.
Compression amplitude limiter circuit described in the utility model, is characterized in that: described triode Q3 is NPN type triode.
Compression amplitude limiter circuit described in the utility model, is characterized in that: described triode Q2 is 2N5401PNP type triode.
Compression amplitude limiter circuit described in the utility model, is characterized in that: described triode Q3 is 2N5551NPN type triode.
Compression amplitude limiter circuit described in the utility model, by the amplitude limit pressure control of resistance R4 and resistance R7, the amplification conducting effect of triode Q2 and triode Q3, and resistance R2 and field effect transistor Q1 amplitude limit regulate, the common compression amplitude limiting processing realized for input signal, and the adjustable range of compression amplitude limiter circuit described in the utility model is wide, distortion is little, and circuit structure is simple, low cost of manufacture, is suitable for applying.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of compression amplitude limiter circuit described in the utility model.
Embodiment
One compression amplitude limiter circuit described in the utility model, as shown in Figure 1, comprises resistance R1-R8, operational amplifier OP, field effect transistor Q1, triode Q2-Q3 and electric capacity C1; Described operational amplifier OP is provided with pin one, pin two and pin 3, and wherein, pin one is output, pin two is inverting input, pin 3 is normal phase input end; One end external circuits input of described resistance R2, is connected with the pin two of operational amplifier OP after the other end and resistance R3 connect; Pin 3 ground connection of operational amplifier OP; Between the pin two that described resistance R1 is arranged at operational amplifier OP and pin one; The pin one external circuits output of described operational amplifier OP; The drain electrode of described field effect transistor Q1 is connected between resistance R2 and resistance R3, source ground, and grid is connected with the collector electrode of triode Q2 after resistance R5; Resistance R8 one end is arranged between field effect transistor Q1 and resistance R5, other end connection-VSS; Electric capacity C1 is in parallel with resistance R8; Emitter access+VCC after resistance R6 of triode Q2, base stage is connected with the collector electrode of triode Q3; The grounded emitter of triode Q3, base stage is connected between the resistance R4 of series connection and resistance R7; The other end of resistance R4 is connected with the pin one of operational amplifier OP; The other end ground connection of resistance R7.
Compression amplitude limiter circuit described in the utility model, described field effect transistor Q1 is 2SK246 field effect transistor.Described triode Q2 is PNP type triode.Described triode Q3 is NPN type triode.
Compression amplitude limiter circuit described in the utility model, described triode Q2 is 2N5401PNP type triode.Described triode Q3 is 2N5551NPN type triode.
Wherein, resistance R4 and resistance R7 does the effect that amplitude limit starts to control voltage sampling; Triode Q2 and triode Q3 does and amplifies conducting effect; Amplitude limit regulating action is done in resistance R2 and field effect transistor Q1 conducting.
During enforcement: when output signal voltage amplitude is a bit to maximum distortion, adjusting resistance R4 and resistance R3 makes triode Q3 amplify conducting, making triode Q2 amplification conducting positive supply is added to field effect transistor Q1 again makes it be operated in switch-turn-ON states, by conducting internal resistance and the resistance R2 dividing potential drop of field effect transistor Q1, the input signal of operational amplifier OP is reduced, make the signal of operational amplifier OP export reduce and undistorted.In concrete implementation process, signal output amplitude can the parameter of adjusting resistance R4 and resistance R3 according to actual needs than setting.
Claims (6)
1. compress an amplitude limiter circuit, comprise resistance R1-R8, operational amplifier OP, field effect transistor Q1, triode Q2-Q3 and electric capacity C1; Described operational amplifier OP is provided with pin one, pin two and pin 3, and wherein, pin one is output, pin two is inverting input, pin 3 is normal phase input end; It is characterized in that: one end external circuits input of described resistance R2, be connected with the pin two of operational amplifier OP after the other end and resistance R3 connect; Pin 3 ground connection of operational amplifier OP; Between the pin two that described resistance R1 is arranged at operational amplifier OP and pin one; The pin one external circuits output of described operational amplifier OP; The drain electrode of described field effect transistor Q1 is connected between resistance R2 and resistance R3, source ground, and grid is connected with the collector electrode of triode Q2 after resistance R5; Resistance R8 one end is arranged between field effect transistor Q1 and resistance R5, other end connection-VSS; Electric capacity C1 is in parallel with resistance R8; Emitter access+VCC after resistance R6 of triode Q2, base stage is connected with the collector electrode of triode Q3; The grounded emitter of triode Q3, base stage is connected between the resistance R4 of series connection and resistance R7; The other end of resistance R4 is connected with the pin one of operational amplifier OP; The other end ground connection of resistance R7.
2. compression amplitude limiter circuit according to claim 1, is characterized in that: described field effect transistor Q1 is 2SK246 field effect transistor.
3. compression amplitude limiter circuit according to claim 2, is characterized in that: described triode Q2 is PNP type triode.
4. compression amplitude limiter circuit according to claim 3, is characterized in that: described triode Q3 is NPN type triode.
5. compression amplitude limiter circuit according to claim 4, is characterized in that: described triode Q2 is 2N5401PNP type triode.
6. compression amplitude limiter circuit according to claim 5, is characterized in that: described triode Q3 is 2N5551NPN type triode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520881216.3U CN205105380U (en) | 2015-11-05 | 2015-11-05 | Compression limit circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520881216.3U CN205105380U (en) | 2015-11-05 | 2015-11-05 | Compression limit circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205105380U true CN205105380U (en) | 2016-03-23 |
Family
ID=55521128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520881216.3U Expired - Fee Related CN205105380U (en) | 2015-11-05 | 2015-11-05 | Compression limit circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205105380U (en) |
-
2015
- 2015-11-05 CN CN201520881216.3U patent/CN205105380U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160323 Termination date: 20211105 |