CN205105095U - Two-phase DC-DC converter and phase-locked loop thereof - Google Patents
Two-phase DC-DC converter and phase-locked loop thereof Download PDFInfo
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- CN205105095U CN205105095U CN201520878932.6U CN201520878932U CN205105095U CN 205105095 U CN205105095 U CN 205105095U CN 201520878932 U CN201520878932 U CN 201520878932U CN 205105095 U CN205105095 U CN 205105095U
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Abstract
The application discloses a two-phase DC-DC converter and a phase-locked loop thereof. The two-phase DC-DC converter includes: the device comprises an input port, an output port, a first power switch circuit, a first on-time calculator, a first off-time generator, a first RS trigger, a second power switch circuit, a second on-time calculator, a second off-time generator, a second RS trigger, an RS latch, a first charging and discharging capacitor, a charging current source and a discharging current source. The two-phase DC-DC converter adjusts the conduction time of the switch of the second power switch circuit through the phase-locked loop circuit, so that the phase difference of the two paths of power switch circuits is effectively controlled to be 180 degrees.
Description
Technical field
The utility model relates to a kind of electronic circuit, and more particularly, the utility model relates to a kind of two-phase dc-dc converter and phase-locked loop thereof.
Background technology
In power conversion system, constant on-time (constantontime, COT) controls due to superior transient response, is widely applied in dc-dc converter.But compared to Peak Current-Mode Controlled Circuit, its switching frequency of power conversion system that COT controls can not be well controlled.
Especially at two-phase or multiphase DC in DC converter, because the switching frequency of system can not be well controlled, therefore, the phase place of not going the same way between output stage can not be efficiently controlled.
Utility model content
Therefore the purpose of this utility model is the above-mentioned technical problem solving prior art, proposes a kind of two-phase dc-dc converter and phase-locked loop thereof of improvement.
According to embodiment of the present utility model, propose a kind of two-phase dc-dc converter, comprising: input port, receive input voltage; Output port, provides output voltage; First power switch circuit, is coupled between input port and output port; First ON time calculator, receives input voltage, output voltage and the first logic control signal, produces the first ON time signal; First opening time generator, receive reference voltage, characterize the first current sampling signal of flowing through the electric current of the first power switch circuit and characterize the feedback voltage of output voltage, produce first opening time signal; First rest-set flip-flop, there is the RESET input, set input and output, its the RESET input is coupled to the first ON time calculator and receives the first ON time signal, its set input be coupled to first opening time generator receive first opening time signal, described first rest-set flip-flop based on the first ON time signal and first opening time signal, produce the first logic control signal, in order to control the operation of the first power switch circuit; Second power switch circuit, and the first power switch circuit coupled in parallel is between input port and output port; Second ON time calculator, receives input voltage, output voltage, the second logic control signal and charging/discharging voltage, produces the second ON time signal; Second opening time generator, receive reference voltage, characterize and flow through the second current sampling signal and the feedback voltage of the electric current of the second power switch circuit, produce second opening time signal; Second rest-set flip-flop, there is the RESET input, set input and output, its the RESET input is coupled to the second ON time calculator and receives the second ON time signal, its set input be coupled to second opening time generator receive second opening time signal, described second rest-set flip-flop based on the second ON time signal and second opening time signal, produce the second logic control signal, in order to control the operation of the second power switch circuit; RS latch, there is set input, the RESET input and output, the output that its set input is coupled to the first rest-set flip-flop receives the first logic control signal, the output that its RESET input is coupled to the second rest-set flip-flop receives the second logic control signal, described RS latch, based on the first logic control signal and the second logic control signal, produces square-wave signal at its output; First charge and discharge capacitance; Charging current source, gives the first charge and discharge capacitance charging when square-wave signal is the first state; Discharging current source, gives the first charge and discharge capacitance electric discharge when square-wave signal is the second state; The voltage at wherein said first charge and discharge capacitance two ends is the charging/discharging voltage being delivered to the second ON time calculator.
According to embodiment of the present utility model, described two-phase dc-dc converter also comprises: the first short pulse circuit, receives the first logic control signal, produces the set input of the first short pulse signal to RS latch; Second short pulse circuit, receives the second logic control signal, produces the second short pulse signal the RESET input to RS latch.
According to embodiment of the present utility model, the electric current that wherein said charging current source and discharging current source provide is equal.
According to embodiment of the present utility model, wherein said second ON time calculator comprises: intermediate node; Controlled current source, in intermediate node, place provides controlled charge current; Push-pull circuit, receives the charging/discharging voltage at the first charge and discharge capacitance two ends, produces boost charge electric current in intermediate node place; Second charge and discharge capacitance and reset switch, coupled in parallel is at intermediate node with reference between ground; Reset short pulse circuit, receives the second logic control signal, produces the control end of reset short pulse signal to reset switch; Controlled voltage signal generator, produces controlled voltage signal; Charging comparator, there is first input end, the second input and output, its first input end receives controlled voltage signal, its second input is coupled to the voltage that intermediate node receives the second charge and discharge capacitance two ends, and described charging comparator produces described second ON time signal based on the voltage at controlled voltage signal and the second charge and discharge capacitance two ends.
According to embodiment of the present utility model, described two-phase dc-dc converter also comprises: charging resistor, described first charge and discharge capacitance via charging resistor by charging and discharging.
According to embodiment of the present utility model, also proposed a kind of phase-locked loop circuit, for correcting the phase difference of the first power switch circuit and the second power switch circuit in two-phase dc-dc converter, the operation of described first power switch circuit be controlled by by the first ON time signal and first opening time signal deciding the first logic control signal, the operation of described second power switch circuit be controlled by by the second ON time signal and second opening time signal deciding the second logic control signal, described phase-locked loop circuit comprises: RS latch, there is set input, the RESET input and output, its set input receives the first logic control signal, its the RESET input receives the second logic control signal, described RS latch is based on the first logic control signal and the second logic control signal, square-wave signal is produced at its output, first charge and discharge capacitance, charging current source, gives the first charge and discharge capacitance charging when square-wave signal is the first state, discharging current source, gives the first charge and discharge capacitance electric discharge when square-wave signal is the second state, the voltage at wherein said first charge and discharge capacitance two ends is in order to adjust the second ON time signal.
According to embodiment of the present utility model, described phase-locked loop circuit also comprises: the first short pulse circuit, receives the first logic control signal, produces the set input of the first short pulse signal to RS latch; Second short pulse circuit, receives the second logic control signal, produces the second short pulse signal the RESET input to RS latch.
According to embodiment of the present utility model, described phase-locked loop circuit also comprises: charging resistor, described first charge and discharge capacitance via charging resistor by charging and discharging.
According to embodiment of the present utility model, described phase-locked loop circuit also comprises: push-pull circuit, receives the voltage at the first charge and discharge capacitance two ends, produces boost charge electric current, in order to adjust the second ON time signal.
According to embodiment of the present utility model, the electric current that wherein said charging current source and discharging current source provide is equal.
According to above-mentioned two-phase dc-dc converter and the phase-locked loop thereof of the utility model each side, the phase difference of two-way power switch circuit is controlled effectively at 180 degree.
Accompanying drawing explanation
Fig. 1 shows two-phase dc-dc converter 100 schematic diagram according to the utility model embodiment;
Fig. 2 illustrates the structural representation of the two-phase dc-dc converter 200 according to the utility model embodiment;
Fig. 3 illustrates the structural representation of the two-phase dc-dc converter 300 according to the utility model embodiment;
Fig. 4 illustrates the structural representation of the first ON time calculator 104 according to the utility model embodiment and the second ON time calculator 204;
Fig. 5 shows the structural representation of the controlled voltage signal generator 46 according to the utility model embodiment;
Fig. 6 shows the structural representation of the controlled voltage signal generator 46 according to the utility model embodiment;
Fig. 7 shows the electrical block diagram of the controlled current source 42 according to the utility model embodiment;
Fig. 8 diagrammatically illustrates the method flow diagram 400 for two-phase dc-dc converter according to the utility model embodiment.
Embodiment
To specific embodiment of the utility model be described in detail below, it should be noted that the embodiments described herein is only for illustrating, is not limited to the utility model.In the following description, in order to provide thorough understanding of the present utility model, a large amount of specific detail has been set forth.But, those of ordinary skill in the art be it is evident that: these specific detail need not be adopted to carry out the utility model.In other instances, in order to avoid obscuring the utility model, do not specifically describe known circuit, material or method.
In whole specification, " embodiment ", " embodiment ", " example " or mentioning of " example " are meaned: the special characteristic, structure or the characteristic that describe in conjunction with this embodiment or example are comprised at least one embodiment of the utility model.Therefore, the phrase " in one embodiment " occurred in each place of whole specification, " in an embodiment ", " example " or " example " differ to establish a capital and refer to embodiment or example.In addition, can with any suitable combination and/or sub-portfolio by specific feature, structure or property combination in one or more embodiment or example.In addition, it should be understood by one skilled in the art that the accompanying drawing provided at this is all for illustrative purposes, and accompanying drawing is not necessarily drawn in proportion.Should be appreciated that when claim element " be couple to " or " being connected to " another element time, it can be directly couple or be couple to another element or can there is intermediary element.On the contrary, when claim element " be directly coupled to " or " being directly connected to " another element time, there is not intermediary element.Identical Reference numeral indicates identical element.Term "and/or" used herein comprises any and all combinations of one or more relevant project listed.
Fig. 1 shows two-phase dc-dc converter 100 schematic diagram according to the utility model embodiment.In the embodiment shown in fig. 1, described two-phase dc-dc converter 100 comprises: input port 101, receives input voltage vin; Output port 102, provides output voltage V
o; First power switch circuit 103, is coupled between input port 101 and output port 102; First ON time calculator 104, receives input voltage vin, output voltage V
owith the first logic control signal PWM1, produce the first ON time signal ton1; First opening time generator 105, receive reference voltage Vr, characterize the first current sampling signal I flowing through the electric current of the first power switch circuit 103
cS1, and characterize output voltage V
ofeedback voltage V
fB, produce first opening time signal toff1; First rest-set flip-flop 106, there is the RESET input R, set input S and output Q, its the RESET input R is coupled to the first ON time calculator 104 and receives the first ON time signal ton1, its set input S be coupled to first opening time generator 105 receive first opening time signal toff1, described first rest-set flip-flop 106 based on the first ON time signal ton1 and first opening time signal toff1, produce the first logic control signal PWM1, in order to control the operation of the first power switch circuit 103; Second power switch circuit 203, and the first power switch circuit 103 coupled in parallel is between input port 101 and output port 102; Second ON time calculator 204, receives input voltage vin, output voltage V
o, the second logic control signal PWM2 and charging/discharging voltage V
c, produce the second ON time signal ton2; Second opening time generator 205, receive reference voltage Vr, characterize the second current sampling signal I flowing through the electric current of the second power switch circuit 203
cS2, and characterize output voltage V
ofeedback voltage V
fB, produce second opening time signal toff2; Second rest-set flip-flop 206, there is the RESET input R, set input S and output Q, its the RESET input R is coupled to the second ON time calculator 204 and receives the second ON time signal ton2, its set input S be coupled to second opening time generator 205 receive second opening time signal toff2, described second rest-set flip-flop 206 based on the second ON time signal ton2 and second opening time signal toff2, produce the second logic control signal PWM2, in order to control the operation of the second power switch circuit 203; RS latch 107, there is set input S, the RESET input R and output Q, the output that its set input S is coupled to the first rest-set flip-flop 106 receives the first logic control signal PWM1, the output that its RESET input R is coupled to the second rest-set flip-flop 206 receives the second logic control signal PWM2, described RS latch 107, based on the first logic control signal PWM1 and the second logic control signal PWM2, produces square-wave signal at its output Q; Charging current source 108, described charging current source 108 charges to when square-wave signal is the first state (as logic is high) the first charge and discharge capacitance 110; Discharging current source 109, described discharging current source 109 discharges to when square-wave signal is the second state (as logic low) the first charge and discharge capacitance 110; Described first charge and discharge capacitance 110, its both end voltage is the charging/discharging voltage V being delivered to the second ON time calculator 204
c.
In one embodiment, the electric current that provides of charging current source 108 and discharging current source 109 is equal.
In one embodiment, described first opening time generator 105 to comprise: error amplifier EA, has first input end, the second input and output, and its first input end receives feedback voltage V
fB, the second input produces reference voltage Vr, and described error amplifier EA is by feedback voltage V
fBamplify and integration with the difference of reference voltage Vr, produce error amplification signal at its output; Voltage comparator COM, has first input end, the second input and output, and its first input end is coupled to error amplifier EA and receives error amplification signal, and the second input receives the first current sampling signal I
cS1, described voltage comparator COM relative error amplifying signal and the first current sampling signal I
cS1size, its output produce described first opening time signal toff1.
Fig. 2 illustrates the structural representation of the two-phase dc-dc converter 200 according to the utility model embodiment.The dc-dc of two-phase shown in Fig. 2 converter 200 is similar to the dc-dc of two-phase shown in Fig. 1 converter 100, with the dc-dc of two-phase shown in Fig. 1 converter 100 unlike, the dc-dc of two-phase shown in Fig. 2 converter 200 comprises further: the first short pulse circuit 111, receive the first logic control signal PWM1, and respond the rising edge of the first logic control signal PWM1, produce the set input S of the first short pulse signal to RS latch 107; Second short pulse circuit 112, receives the second logic control signal PWM2, and responds the rising edge of the second logic control signal PWM2, produces the RESET input R of the second short pulse signal to RS latch 107.
Fig. 3 illustrates the structural representation of the two-phase dc-dc converter 300 according to the utility model embodiment.The dc-dc of two-phase shown in Fig. 3 converter 300 is similar to the dc-dc of two-phase shown in Fig. 2 converter 200, with the dc-dc of two-phase shown in Fig. 2 converter 200 unlike, the dc-dc of two-phase shown in Fig. 3 converter 300 comprises further: charging resistor 113, described first charge and discharge capacitance 110 via charging resistor 113 by charging and discharging.
Be in operation, wish that the phase-difference control of the first logic control signal PWM1 and the second logic control signal PWM2 is at 180 degree.When the rising edge of the first logic control signal PWM1 arrives, RS latch 107 is set, and square-wave signal saltus step is logic high, and now charging current source 108 starts to charge to the first charge and discharge capacitance 110; When the rising edge of the second logic control signal PWM2 arrives, RS latch 107 is reset, and square-wave signal saltus step is logic low, and now discharging current source 109 starts to discharge to the first charge and discharge capacitance 110.Therefore, if the phase difference of the first logic control signal PWM1 and the second logic control signal PWM2 is 180 degree, then the duty ratio of square-wave signal is the charging/discharging voltage V at the 50%, first charge and discharge capacitance 110 two ends
cmean value will remain unchanged; If the phase difference of the first logic control signal PWM1 and the second logic control signal PWM2 is less than 180 degree, then the duty ratio of square-wave signal is less than 50%, the charging/discharging voltage V at the first charge and discharge capacitance 110 two ends
cmean value will reduce; If the phase difference of the first logic control signal PWM1 and the second logic control signal PWM2 is greater than 180 degree, then the duty ratio of square-wave signal is greater than 50%, the charging/discharging voltage V at the first charge and discharge capacitance 110 two ends
cmean value will increase.
As charging/discharging voltage V
cmean value increase time, the second ON time calculator 204 responds the charging/discharging voltage V of this increase
c, the second ON time signal ton2 is increased.Correspondingly, the switching frequency of the second power switch circuit 203 also increases.That is, the cycle of the second power switch circuit 203 reduces, and the phase difference of the first logic control signal PWM1 and the second logic control signal PWM2 is reduced, thus makes both phase differences return 180 degree.
As charging/discharging voltage V
cmean value reduce time, the second ON time calculator 204 responds the charging/discharging voltage V of this reduction
c, the second ON time signal ton2 is reduced.Correspondingly, the switching frequency of the second power switch circuit 203 also reduces.That is, the cycle of the second power switch circuit 203 increases, and the phase difference of the first logic control signal PWM1 and the second logic control signal PWM2 is increased, thus makes both phase differences return 180 degree.
That is, embodiment of the present utility model provides a kind of phase discriminator and phase-locked loop circuit, this phase discriminator identifies the phase place of the first logic control signal PWM1 and the second logic control signal PWM2 by RS latch 107, charging current source 108, discharging current source 109 and the first charge and discharge capacitance 110, and adjusted the frequency of the second power switch circuit 203 by adjustment second ON time signal ton2, thus the phase difference of the first power switch circuit 103 and the second power switch circuit 203 is made to maintain 180 degree.This phase-locked loop circuit comprises: RS latch 107, there is set input S, the RESET input R and output Q, its set input R receives the first logic control signal PWM1, its the RESET input R receives the second logic control signal PWM2, described RS latch, based on the first logic control signal PWM1 and the second logic control signal PWM2, produces square-wave signal at its output Q; First charge and discharge capacitance 110; Charging current source 108, charges to when square-wave signal is the first state the first charge and discharge capacitance 110; Discharging current source 109, discharges to when square-wave signal is the second state the first charge and discharge capacitance 110; The voltage V at wherein said first charge and discharge capacitance 110 two ends
cin order to adjust the second ON time signal ton2.
Fig. 4 illustrates the structural representation of the first ON time calculator 104 according to the utility model embodiment and the second ON time calculator 204.In the embodiment shown in fig. 4, described first ON time calculator 104 comprises: intermediate node 40; Controlled current source 42, in intermediate node 40, place provides controlled charge current I1; Second charge and discharge capacitance 43 and reset switch 44, coupled in parallel is at intermediate node 40 with reference between ground; Reset short pulse circuit 45, receives the second logic control signal PWM2, and responds the rising edge of the second logic control signal PWM2, produces the control end of reset short pulse signal to reset switch 44; Controlled voltage signal generator 46, produces controlled voltage signal V
cON; Charging comparator 47, has first input end, the second input and output, and its first input end receives controlled voltage signal V
cON, its second input is coupled to the voltage that intermediate node 40 receives the second charge and discharge capacitance 43 two ends, and described charging comparator 47 is based on controlled voltage signal V
cONdescribed second ON time signal ton2 is produced with the voltage at the second charge and discharge capacitance 43 two ends.Described second ON time calculator 204 comprises described first ON time calculator 104, also comprises: push-pull circuit 41, receives the charging/discharging voltage V at the first charge and discharge capacitance 110 two ends
c, produce boost charge electric current I in intermediate node 40 place
c.
In one embodiment, described first power switch circuit 103 and the second power switch circuit 203 adopt identical circuit topology.When the first power switch circuit 103 and the second power switch circuit 203 all adopt buck topology time, the first ON time signal ton1 and the second ON time signal ton2 all with output voltage V
obe directly proportional, be inversely proportional to input voltage vin.When the first power switch circuit 103 and the second power switch circuit 203 all adopt boost topology time, the first ON time signal ton1 and the second ON time signal ton2 all with output voltage V
obe directly proportional with the difference of input voltage vin, with output voltage V
obe inversely proportional to.
In one embodiment, when the first power switch circuit 103 and the second power switch circuit 203 adopt buck topology, described controlled charge current I1 is directly proportional to input voltage vin, described controlled voltage signal V
cONwith output voltage V
obe directly proportional; When the first power switch circuit 103 and the second power switch circuit 203 adopt boost topology, described controlled charge current I1 and output voltage V
obe directly proportional, described controlled voltage signal V
cONwith output voltage V
obe directly proportional with the difference of input voltage vin.
Fig. 5 shows the structural representation of the controlled voltage signal generator 46 according to the utility model embodiment.In the embodiment shown in fig. 5, described controlled voltage signal generator 46 comprises: the first pull-up current mirror 61, has input, the first current terminal and the second current terminal, and its input receives input voltage vin, and the first current terminal coupling resistance value is the resistance 64 of R1; Pull-down current mirror 62, has electric current and enters end and electric outflow end, and its electric current enters the second current terminal that end is coupled to the first pull-up current mirror 61; Second pull-up current mirror 63, has input, the first current terminal and the second current terminal, and its input receives output voltage V
o, its first current terminal is coupled to the resistance 65 that the electric outflow end of pull-down current mirror 62 and resistance value are R2, and its second current terminal coupling resistance value is the resistance 66 of R1; Wherein said resistance 65 both end voltage is described controlled voltage signal V
cON.By calculating, known
Fig. 6 shows the structural representation of the controlled voltage signal generator 46 according to the utility model embodiment.In the embodiment shown in fig. 6, described controlled voltage signal generator 46 comprises: operational amplifier 67, there is first input end, the second input and output, the resistance 68 that its first input end is R1 by resistance value receives input voltage vin, and the resistance 69 that its second input is R1 by resistance value receives output voltage V
o; Its output is coupled to its second input by transistor 70; Resistance value is R2 resistance 71, is coupled between transistor 70 and reference ground.By calculating, known
Therefore, the signal generator of controlled voltage shown in Fig. 5 and Fig. 6 46 can be applicable to the occasion that the first power switch circuit 103 and the second power switch circuit 203 adopt boost topology.
Fig. 7 shows the electrical block diagram of the controlled current source 42 according to the utility model embodiment.In the embodiment shown in fig. 7, described controlled current source 42 comprises: operational amplifier 21, has first input end, the second input and output, and the resistance 22 that its first input end is R1 via resistance value receives output voltage V
o, be that the resistance 23 of R2 is coupled to reference to ground via resistance value; Its second input is coupled to its output via transistor 24, is that the resistance 25 of R3 is coupled to reference to ground via resistance value; 3rd pull-up current mirror 25, have electric current and enter end and electric outflow end, its electric current enters end and is coupled to transistor 24, and its electric outflow end provides described controlled charge current I1.By calculating, known
Therefore, controlled current source 42 shown in Fig. 7 can be applicable to the occasion that the first power switch circuit 103 and the second power switch circuit 203 adopt boost topology.
Although above embodiments only show the structural representation of controlled current source 42 and controlled voltage signal generator 46 when the first power switch circuit 103 and the second power switch circuit 203 adopt boost topology.But those skilled in the art should recognize, by simple amendment, the structural representation of controlled current source 42 and controlled voltage signal generator 46 when the first power switch circuit 103 and the second power switch circuit 203 adopt buck topology can be obtained.Because it is not the purpose of this utility model place, for simplicity's sake, no longer describe in detail.
Fig. 8 diagrammatically illustrates the method flow diagram 400 for two-phase dc-dc converter according to the utility model embodiment.Described two-phase dc-dc converter comprises the first power switch circuit and second power switch circuit of coupled in parallel, and both jointly receive input voltage, provide output voltage, and described method comprises:
Step 401, provide characterize output voltage feedback voltage, characterize flow through the electric current of the first power switch circuit the first current sampling signal, characterize and flow through the second current sampling signal of the electric current of the second power switch circuit.
Step 402, responsive feedback voltage, the first current sampling signal and reference voltage, produce first opening time signal; Responsive feedback voltage, the second current sampling signal and reference voltage, produce second opening time signal.In one embodiment, this step comprises: the difference of feedback voltage and reference voltage amplified and integration obtains error amplification signal, relative error amplifying signal and the first current sampling signal, obtain first opening time signal; Relative error amplifying signal and the second current sampling signal, obtain second opening time signal.
Step 403, response input voltage, output voltage and the first logic control signal, produce the first ON time signal.In one embodiment, respond the rising edge of the first logic control signal, reset an electric capacity shorter pulse times section; Described capacitor charging is given subsequently by controlled charge current; The voltage at response electric capacity two ends and controlled voltage signal, produce described first ON time signal.Wherein, when the first power switch circuit and the second power switch circuit all adopt buck topology, described controlled charge current is directly proportional to input voltage, described controlled voltage signal is directly proportional to output voltage; When the first power switch circuit and the second power switch circuit all adopt boost topology, described controlled charge current is directly proportional to output voltage, and described controlled voltage signal is directly proportional to the difference of output voltage and input voltage.
Step 404, respond the first ON time signal and first opening time signal, produce described first logic control signal.In one embodiment, the rising edge saltus step that the first logic control signal responds the first ON time signal is logic high, respond first opening time signal rising edge saltus step be logic low.
Step 405, responds described first logic control signal and the second logic control signal, produces square-wave signal.In one embodiment, the rising edge saltus step that described square-wave signal responds the first logic control signal is logic high, and the rising edge saltus step responding the second logic control signal is logic low.
Step 406, response square-wave signal, produces charging/discharging voltage.In one embodiment, when square-wave signal is logic high, described charging/discharging voltage linearly rises; When square-wave signal is logic low, described charging/discharging voltage linearly declines.
Step 407, response charging/discharging voltage, produces boost charge electric current.In one embodiment, described boost charge electric current is realized by push-pull circuit.
Step 408, response input voltage, output voltage, the second logic control signal and boost charge electric current, produce the second ON time signal.In one embodiment, respond the rising edge of the first logic control signal, reset an electric capacity shorter pulse times section; Described capacitor charging is given subsequently by controlled charge current and boost charge electric current; Respond voltage and the controlled voltage signal at described electric capacity two ends, produce described second ON time signal.Wherein, when the first power switch circuit and the second power switch circuit all adopt buck topology, described controlled charge current is directly proportional to input voltage, described controlled voltage signal is directly proportional to output voltage; When the first power switch circuit and the second power switch circuit all adopt boost topology, described controlled charge current is directly proportional to output voltage, and described controlled voltage signal is directly proportional to the difference of output voltage and input voltage.
Step 409, respond the second ON time signal and second opening time signal, produce described second logic control signal; Wherein said first logic control signal and the second logic control signal are in order to control the operation of the first power switch circuit and the second power switch circuit respectively.
Compared with existing two-phase dc-dc converter, the two-phase dc-dc converter of foregoing embodiments and method thereof can control the phase difference of two-way power switch circuit effectively.Be different from prior art, the two-phase dc-dc converter of foregoing embodiments and the logic control signal of method response limiting two-way power switch circuit thereof, produce square-wave signal.When the duty ratio of square-wave signal is not equal to 50%, by adjusting the switch conduction times of the second road power switch circuit, the phase difference of two-way power switch circuit is made to return 180 degree.
Although exemplary embodiment describe the utility model with reference to several, should be appreciated that term used illustrates and exemplary and nonrestrictive term.Specifically can implement in a variety of forms due to the utility model and not depart from spirit or the essence of utility model, so be to be understood that, above-described embodiment is not limited to any aforesaid details, and explain widely in the spirit and scope that should limit in claim of enclosing, therefore fall into whole change in claim or its equivalent scope and remodeling and all should be claim of enclosing and contained.
Claims (10)
1. a two-phase dc-dc converter, is characterized in that, comprising:
Input port, receives input voltage;
Output port, provides output voltage;
First power switch circuit, is coupled between input port and output port;
First ON time calculator, receives input voltage, output voltage and the first logic control signal, produces the first ON time signal;
First opening time generator, receive reference voltage, characterize the first current sampling signal of flowing through the electric current of the first power switch circuit and characterize the feedback voltage of output voltage, produce first opening time signal;
First rest-set flip-flop, there is the RESET input, set input and output, its the RESET input is coupled to the first ON time calculator and receives the first ON time signal, its set input be coupled to first opening time generator receive first opening time signal, described first rest-set flip-flop based on the first ON time signal and first opening time signal, produce the first logic control signal, in order to control the operation of the first power switch circuit;
Second power switch circuit, and the first power switch circuit coupled in parallel is between input port and output port;
Second ON time calculator, receives input voltage, output voltage, the second logic control signal and charging/discharging voltage, produces the second ON time signal;
Second opening time generator, receive reference voltage, characterize and flow through the second current sampling signal and the feedback voltage of the electric current of the second power switch circuit, produce second opening time signal;
Second rest-set flip-flop, there is the RESET input, set input and output, its the RESET input is coupled to the second ON time calculator and receives the second ON time signal, its set input be coupled to second opening time generator receive second opening time signal, described second rest-set flip-flop based on the second ON time signal and second opening time signal, produce the second logic control signal, in order to control the operation of the second power switch circuit;
RS latch, there is set input, the RESET input and output, the output that its set input is coupled to the first rest-set flip-flop receives the first logic control signal, the output that its RESET input is coupled to the second rest-set flip-flop receives the second logic control signal, described RS latch, based on the first logic control signal and the second logic control signal, produces square-wave signal at its output;
First charge and discharge capacitance;
Charging current source, gives the first charge and discharge capacitance charging when square-wave signal is the first state;
Discharging current source, gives the first charge and discharge capacitance electric discharge when square-wave signal is the second state; The voltage at wherein said first charge and discharge capacitance two ends is the charging/discharging voltage being delivered to the second ON time calculator.
2. two-phase dc-dc converter as claimed in claim 1, is characterized in that, also comprise:
First short pulse circuit, receives the first logic control signal, produces the set input of the first short pulse signal to RS latch;
Second short pulse circuit, receives the second logic control signal, produces the second short pulse signal the RESET input to RS latch.
3. two-phase dc-dc converter as claimed in claim 1, it is characterized in that, the electric current that wherein said charging current source and discharging current source provide is equal.
4. two-phase dc-dc converter as claimed in claim 1, it is characterized in that, wherein said second ON time calculator comprises:
Intermediate node;
Controlled current source, in intermediate node, place provides controlled charge current;
Push-pull circuit, receives the charging/discharging voltage at the first charge and discharge capacitance two ends, produces boost charge electric current in intermediate node place;
Second charge and discharge capacitance and reset switch, coupled in parallel is at intermediate node with reference between ground;
Reset short pulse circuit, receives the second logic control signal, produces the control end of reset short pulse signal to reset switch;
Controlled voltage signal generator, produces controlled voltage signal;
Charging comparator, there is first input end, the second input and output, its first input end receives controlled voltage signal, its second input is coupled to the voltage that intermediate node receives the second charge and discharge capacitance two ends, and described charging comparator produces described second ON time signal based on the voltage at controlled voltage signal and the second charge and discharge capacitance two ends.
5. two-phase dc-dc converter as claimed in claim 1, is characterized in that, also comprise: charging resistor, described first charge and discharge capacitance via charging resistor by charging and discharging.
6. a phase-locked loop circuit, for correcting the phase difference of the first power switch circuit and the second power switch circuit in two-phase dc-dc converter, the operation of described first power switch circuit be controlled by by the first ON time signal and first opening time signal deciding the first logic control signal, the operation of described second power switch circuit be controlled by by the second ON time signal and second opening time signal deciding the second logic control signal, it is characterized in that, described phase-locked loop circuit comprises:
RS latch, there is set input, the RESET input and output, its set input receives the first logic control signal, its the RESET input receives the second logic control signal, described RS latch, based on the first logic control signal and the second logic control signal, produces square-wave signal at its output;
First charge and discharge capacitance;
Charging current source, gives the first charge and discharge capacitance charging when square-wave signal is the first state;
Discharging current source, gives the first charge and discharge capacitance electric discharge when square-wave signal is the second state; The voltage at wherein said first charge and discharge capacitance two ends is in order to adjust the second ON time signal.
7. phase-locked loop circuit as claimed in claim 6, is characterized in that, also comprise:
First short pulse circuit, receives the first logic control signal, produces the set input of the first short pulse signal to RS latch;
Second short pulse circuit, receives the second logic control signal, produces the second short pulse signal the RESET input to RS latch.
8. phase-locked loop circuit as claimed in claim 6, it is characterized in that, the electric current that wherein said charging current source and discharging current source provide is equal.
9. phase-locked loop circuit as claimed in claim 6, is characterized in that, also comprise: charging resistor, described first charge and discharge capacitance via charging resistor by charging and discharging.
10. phase-locked loop circuit as claimed in claim 6, is characterized in that, also comprise: push-pull circuit, receive the voltage at the first charge and discharge capacitance two ends, produces boost charge electric current, in order to adjust the second ON time signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520878932.6U CN205105095U (en) | 2015-11-05 | 2015-11-05 | Two-phase DC-DC converter and phase-locked loop thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520878932.6U CN205105095U (en) | 2015-11-05 | 2015-11-05 | Two-phase DC-DC converter and phase-locked loop thereof |
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| CN205105095U true CN205105095U (en) | 2016-03-23 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105226936A (en) * | 2015-11-05 | 2016-01-06 | 成都芯源系统有限公司 | Two-phase DC-DC converter, phase-locked loop thereof and method |
| CN108614458A (en) * | 2018-05-30 | 2018-10-02 | 中国神华能源股份有限公司 | The determination method and device of trigger, trigger output state |
-
2015
- 2015-11-05 CN CN201520878932.6U patent/CN205105095U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105226936A (en) * | 2015-11-05 | 2016-01-06 | 成都芯源系统有限公司 | Two-phase DC-DC converter, phase-locked loop thereof and method |
| CN108614458A (en) * | 2018-05-30 | 2018-10-02 | 中国神华能源股份有限公司 | The determination method and device of trigger, trigger output state |
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