CN205092045U - Display driver circuit, display device - Google Patents
Display driver circuit, display device Download PDFInfo
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- CN205092045U CN205092045U CN201520891589.9U CN201520891589U CN205092045U CN 205092045 U CN205092045 U CN 205092045U CN 201520891589 U CN201520891589 U CN 201520891589U CN 205092045 U CN205092045 U CN 205092045U
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Abstract
The utility model provides a display driver circuit, display device, display driver circuit wherein includes: timing sequential control unit, modulation unit and top rake unit, wherein: timing sequential control unit connects modulation unit for generate the control signal that the line selected the signal, included top rake width signal and top rake degree of depth signal based on presetting clock signal, and include modulated in width signal and/or degree of depth modulating signal's the 2nd control signal, modulation unit connects the top rake unit for go according to the 2nd control signal modulation and select the control signal of signal in being period of significant level, the top rake unit is used for carrying out the top rake according to the control signal by after the modulation unit modulation to grid voltage signal and handling before output grid voltage signal. Based on the fact, the utility model discloses can solve and appear charging effect between the pixel that bars scanning line of the same profession is connected among the prior art and have apparent the problem of difference, be favorable to the promotion of display effect.
Description
Technical field
The utility model relates to display technique field, is specifically related to a kind of display driver circuit, display device.
Background technology
Existing liquid crystal display (LiquidCrystalDisplay, LCD) in, for the difference of pixel electrode array set-up mode and reversal of poles type, between the pixel that may connect at different rows grid sweep trace, there is the charging effect problem that there were significant differences.Z reversion charge mode in prior art such as shown in Fig. 1 under a kind of double grid framework, the charging polarity of first row data line between front two row pixels is respectively "+", "+", "-", "-".Wherein, as shown in the oblique arrow in Fig. 1, when first row data line transfers "-" at charging polarity to by "+", stray capacitance on the excessive and data line of the span of the voltage magnitude voltage on first row data line can be made to exist one to be dropped to "-" polar voltages changes phase by "+" polar voltages, the existence in this stage can cause the charging effect of the second row first row "-" polarity pixel within the given duration of charging not reach given level, needs the duration of charging more grown just can reach given level in other words compared to other pixels.Based on this, the pixel marked out with shade in Fig. 1 all needs the duration of charging more grown just can reach equal charging effect compared to other pixels, therefore may there is luminous darker or brighter situation due to undercharge when the duration of charging of each pixel is basically identical, finally be reflected in display frame and then may present light and dark striped, affect normal display effect.
Utility model content
For defect of the prior art, the utility model provides a kind of display driver circuit, display device, can solve between pixel that in prior art, different rows grid sweep trace connects and occur the charging effect problem that there were significant differences.
First aspect, the utility model provides a kind of display driver circuit, comprises timing control unit, modulating unit and top rake unit, wherein:
Described timing control unit connects described modulating unit, for generating the first control signal comprising top rake width signal and top rake depth signal based on default clock signal, and comprises the second control signal of bandwidth modulation signals and/or depth modulation signal;
Described modulating unit connects described top rake unit, for modulating described first control signal according to described second control signal;
Described top rake unit is used for before output gate voltage signal, carries out top rake process according to by the first control signal after described modulating unit modulation to gate voltage signal.
Alternatively, described modulating unit comprises depth modulation module; Described depth modulation module is used for the amplitude adjusting described top rake depth signal according to described depth modulation signal.
Alternatively, described depth modulation module comprises the first digital varistor that control end connects described depth modulation signal; The first end of described first digital varistor connects common port; Second end of described first digital varistor connects described top rake unit, and connects described top rake depth signal through the first fixed value resistance.
Alternatively, described depth modulation signal comprises the square-wave pulse of predetermined quantity within each clock period; Described first digital varistor is used for according to the resistance value controlled in each clock period between the quantity determination first end of the square-wave pulse that termination receives and the second end.
Alternatively, described timing control unit also selects signal for generating row; Described modulating unit comprises width modulation module; Described width modulation module is used for selecting signal to be that the phase place of described top rake width signal in the period of significant level adjusts forward or backward according to described bandwidth modulation signals to row described in each.
Alternatively, described width modulation module comprises operational amplifier, the first transistor, transistor seconds, the second digital varistor, the first electric capacity and trigger, wherein:
Positive terminal and the end of oppisite phase of described operational amplifier are connected one that described row selects in signal and predetermined electrical bias voltage respectively, and output terminal connects the grid of described the first transistor and the grid of described transistor seconds;
Described the first transistor and transistor seconds are respectively one in P-type crystal pipe and N-type transistor; The source electrode of described the first transistor is connected described top rake width signal with in drain electrode, and another connects the first end of described second digital varistor; The source electrode of described transistor seconds is connected described top rake width signal with in drain electrode, and another connects described top rake unit;
The control end of described second digital varistor connects described bandwidth modulation signals; Second end of described second digital varistor connects the input end of described trigger, and is connected with common port through the two ends of described first electric capacity;
The output terminal of described trigger is connected with described top rake unit, for exporting high level at input end higher than during predetermined potential.
Alternatively, described bandwidth modulation signals comprises the square-wave pulse of predetermined quantity within each clock period; Described second digital varistor is used for according to the resistance value controlled in each clock period between the quantity determination first end of the square-wave pulse that termination receives and the second end.
Second aspect, the utility model also provides a kind of display device, comprises any one display driver circuit above-mentioned.
Alternatively, described display device also comprises scan drive circuit; Described scan drive circuit connects described top rake unit, for receiving the gate voltage signal from described top rake unit.
As shown from the above technical solution, the utility model is based on the improvement of the structure to display driver circuit, can by second control signal of timing control unit generation for modulating top rake degree, and modulate top rake degree by modulating unit according to the second control signal, and carried out the output of the gate voltage signal after top rake process by top rake unit to scan drive circuit, thus the modulation of top rake degree on grid sweep trace set by realizing.The second control signal generated due to timing control unit can be arranged by software programming, therefore the utility model can provide a kind of mode realizing modulating the top rake degree of the gate voltage signal on any multirow grid sweep trace, can solve between pixel that in prior art, different rows grid sweep trace connects and occur the charging effect problem that there were significant differences, and make the pixel charging effect adjusting manufactured goods become possibility, be conducive to the lifting of display effect, and the reduction of the cost of the aspect such as later stage test, maintenance.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, simply introduce doing one to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram of the Z reversion charge mode in prior art under a kind of double grid framework;
Fig. 2 is the structured flowchart of a kind of display driver circuit in the utility model embodiment;
Fig. 3 is the working timing figure of a kind of display driver circuit in the utility model embodiment;
Fig. 4 is the modulation principle figure of the top rake width signal of a kind of display driver circuit in the utility model embodiment;
Fig. 5 is the circuit structure diagram of the adjustment unit in the utility model embodiment in a kind of display driver circuit;
Fig. 6 is the setting position schematic diagram of a kind of display driver circuit in the utility model embodiment;
Fig. 7 is the steps flow chart schematic diagram of a kind of display drive method in the utility model embodiment.
Embodiment
For making the object of the utility model embodiment, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the utility model embodiment, technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.
Fig. 2 is the structured flowchart of a kind of display driver circuit in the utility model embodiment.See Fig. 2, this display driver circuit comprises timing control unit 21, modulating unit 22 and top rake unit 23, wherein:
Timing control unit 21 connects modulating unit 22, specifically for generating the first control signal comprising top rake width signal OE2 and top rake depth signal AVDD based on default clock signal C PV, and comprise second control signal of bandwidth modulation signals RES-C1 and/or depth modulation signal RES-C2.Be understandable that, this timing control unit 21 can have the sequential control circuit (TimingController for display device in prior art, TCON) framework, thus under the benchmark of identical default clock signal, top rake width signal OE2, the top rake depth signal AVDD all with required waveform arbitrarily can be generated, and bandwidth modulation signals RES-C1 and/or depth modulation signal RES-C2.It should be noted that, above-mentioned each signal is all not shown in Figure 2.
Modulating unit 22 connects top rake unit 23, specifically for modulating above-mentioned first control signal according to above-mentioned second control signal.According to the concrete form of the second control signal and the first control signal, modulating unit 22 can be modulated top rake width signal OE2 and/or top rake depth signal AVDD, to realize the top rake degree specified by the second control signal, modulation such as voltage magnitude can select bleeder circuit or transforming circuit, and delay circuit etc. can be adopted to the modulation on signal sequence, the utility model does not limit this.
Top rake unit 23 for before output gate voltage signal VON, the first control signal after modulating according to modulated unit 22 (can comprise modulated after top rake width signal GVOFF and/or modulated after top rake depth signal THR) top rake process is carried out to gate voltage signal VON.Be understandable that, above-mentioned specifically referring to before output gate voltage signal VON is generated to the node location that can carry out arbitrarily top rake process between being output from gate voltage signal VON.It will also be appreciated that, gate voltage signal VON is the voltage signal that the transistor of control linkage on multirow grid sweep trace is opened line by line, the unlatching of the charging process of pixel electrode in each display frame and the control of the open and close terminated with regard to being subject to these transistors in LCD.Thus, based on the top rake process carried out gate voltage signal VON, the level of charge of pixel electrode corresponding with every a line grid sweep trace by Row sum-equal matrix by a small margin can be carried out in the top rake degree of depth and top rake width two.Be understandable that, the above-mentioned physical circuit implementation to the top rake process that gate voltage signal is carried out is well-known to those skilled in the art, does not repeat them here.
Can find out, the utility model embodiment is based on the improvement of the structure to display driver circuit, can by second control signal of timing control unit generation for modulating top rake degree, and modulate top rake degree by modulating unit according to the second control signal, and carried out the output of the gate voltage signal after top rake process by top rake unit to scan drive circuit, thus the modulation of top rake degree on grid sweep trace set by realizing.The second control signal generated due to timing control unit can be arranged by software programming, and therefore the utility model embodiment can provide a kind of mode realizing modulating the top rake degree of the gate voltage signal on any multirow grid sweep trace.The pixel marked out with shade that such as Fig. 1 addresses all needs the duration of charging more grown just can reach equal charging effect compared to other pixels, therefore may there is luminous darker or brighter situation due to undercharge when the duration of charging of each pixel is basically identical, finally be reflected in display frame and then may present light and dark striped, affect the problem of normal display effect, the utility model embodiment relatively can reduce the top rake degree of the gate voltage signal on grid sweep trace corresponding to pixel that all reduction shades mark out, to compensate the duration of charging of these pixels, the charging effect of all pixels is reached unanimity.So, the utility model embodiment may be used for solving between different rows grid sweep trace connects in prior art pixel and occurs the charging effect problem that there were significant differences, and make the pixel charging effect adjusting manufactured goods become possibility, be conducive to the lifting of display effect, and the reduction of the cost of the aspect such as later stage test, maintenance.
Be understandable that, owing to can realize the adjustment of corresponding level of charge to the modulation of the top rake degree of depth and top rake width, therefore when implementing the utility model, of can choose in the top rake degree of depth and top rake width modulates, also can modulate the top rake degree of depth and top rake width simultaneously, it all can solve between pixel that in prior art, different rows grid sweep trace connects and occur the charging effect problem that there were significant differences, and the utility model does not limit this.
As a kind of example, Fig. 3 is the working timing figure of a kind of display driver circuit in the utility model embodiment.See Fig. 3, under the benchmark of default clock signal C PV, grid control signal OE1 and modulated after top rake width signal GVOFF can determine each rising edge of gate voltage signal VON and the position of negative edge respectively.As shown in the short dash line in Fig. 3, under the triggering of the negative edge of grid control signal OE1, gate voltage signal VON is maximum level by minimum point flat turn; And under the triggering of the rising edge at grid control signal OE1, gate voltage signal VON returns minimum level by peak flat turn.And under the triggering of the rising edge of top rake width signal GVOFF after modulation, gate drive signal VON starts by top rake.Thus, corresponding to arbitrary row grid sweep trace, the distance between the rising edge of the top rake width signal GVOFF after modulation and the rising edge of grid control signal OE1 determines the top rake width of the gate drive signal VON of appropriate section.Be understandable that, if the rising edge of the top rake width signal GVOFF in arbitrary clock period adjusted (namely on a timeline moving to left and moving to right) forward or backward, the top rake width of the gate drive signal VON in this clock period can increase thereupon or shorten.
On the other hand, do not illustrate completely in the drawings, the quantity of the different square-wave pulse that depth modulation signal RES-C2 has within each clock period can carry out which amplitude modulation to top rake depth signal AVDD, to obtain the top rake depth signal THR after modulating; Thus during gate drive signal VON is by top rake, level height is provided by this top rake depth signal THR, level height as gate drive signal VON corresponding with 3 square-wave pulses in Fig. 3 is U1, and the level height of the gate drive signal VON corresponding with 2 square-wave pulses is U2, namely has the different top rake degree of depth.Be understandable that, timing control unit 21 can be used thus to generate the depth modulation signal RES-C2 of the quantity in each clock period with given square-wave pulse, realize the adjustment of the top rake degree of depth of the gate drive signal VON in each clock period, then realize the setting of the level of charge of the pixel electrode corresponding with every a line grid sweep trace.
Be understandable that in addition, the row in Fig. 3 selects signal CS can be generated by timing control unit 21, and can carry out the control of validity in each clock period to modulating unit 22.Such as, row selects signal CS specifically can act on bandwidth modulation signals RES-C1 and depth modulation signal RES-C2, makes row select signal CS to be in bandwidth modulation signals RES-C1 in several time periods of high level and depth modulation signal RES-C2 and is acquiescence waveform (such as RES-C2 all has 3 square-wave pulses during this period).Or in the modulated process that row selects signal CS also can act on the first control signal, internal modulation unit 22 during selecting signal CS to be in significant level of being namely expert at is not modulated one or two signal in the first control signal.Herein, significant level can be one in high level and low level, and high level and low level concrete voltage range can be determined according to application demand, do not repeat them here.Thus, under the row can with random waveform selects the effect of signal CS, degree of freedom and the reliability of above-mentioned level of charge setting can be increased; And be expert at when selecting signal CS to act in the modulated process to the first control signal, it can reduce the working time of modulating unit 22, contributes to the reduction of power consumption and the lifting of response speed.
As an example more specifically, Fig. 4 is the modulation principle figure of the top rake width signal of a kind of display driver circuit in the utility model embodiment.See Fig. 4, depth modulation signal RES-C2 all has 3 square-wave pulses within each clock period; And be expert at select signal CS effect under, be only expert at during selecting signal CS to be the high level of significant level, modulating unit 22 just can adjust the phase place of top rake width signal OE2 within the clock period of place backward.Certainly, the amplitude adjusted backward is determined by the quantity of the square-wave pulse of depth modulation signal RES-C2 within this clock period, and look the difference of application demand, also the adjustment carried out forward can be added in overall setting range.Be understandable that, based on each signal in Fig. 4 waveform representated by input/output relation, adjustment unit 22 can have corresponding circuit structure.
As a kind of concrete example, Fig. 5 is the circuit structure diagram of the adjustment unit in the utility model embodiment in a kind of display driver circuit.See Fig. 5, this adjustment unit specifically comprises depth modulation module 22a and width modulation module 22b, specifically:
Depth modulation module 22a is used for the amplitude adjusting top rake depth signal AVDD according to depth modulation signal REC-C2, to form the top rake depth signal GVOFF after above-mentioned modulation.Specifically, this depth modulation module 22a comprises the first digital varistor DPR1 that control end (being specially upper end in the drawings) connects depth modulation signal.In addition, the first end (being specially right-hand member in the drawings) of the first digital varistor DPR1 connects common port; Second end (being specially left end in the drawings) of the first digital varistor DPR1 connects top rake unit 23, and connects top rake depth signal AVDD through the first fixed value resistance R1.Functionally, under the condition of square-wave pulse (such as shown in Fig. 3) that depth modulation signal RES-C2 comprises predetermined quantity within each clock period, the first digital varistor DPR1 is used for according to the resistance value controlled in each clock period between the quantity determination first end of the square-wave pulse that termination receives and the second end.Thus, dividing between the first digital varistor DPR1 and the first fixed value resistance R1 depresses, the downward which amplitude modulation realizing being subject to depth modulation signal REC-C2 control to top rake depth signal AVDD can be realized, thus the adjustment of the top rake degree of depth corresponded to described by above-mentioned Fig. 3 can be realized.
On the other hand, width modulation module 22b is used for selecting signal CS to be that the phase place of top rake width signal OE2 in the period of significant level adjusts forward or backward according to bandwidth modulation signals RES-C1 to every a line, namely realizes the input/output relation representated by the waveform of each signal in Fig. 4.Specifically, the width modulation module 22b shown in Fig. 5 comprises operational amplifier OP, the first transistor M1, transistor seconds M2, the second digital varistor R2, the first electric capacity C1 and trigger TR, wherein:
The positive terminal of operational amplifier OP and end of oppisite phase respectively connected row select one in signal CS and predetermined electrical bias voltage REF, and output terminal connects the grid of the first transistor M1 and the grid of transistor seconds M2.And the first transistor M1 and transistor seconds M2 is respectively one in P-type crystal pipe and N-type transistor.Based on this, operational amplifier can select the difference signal between signal CS and predetermined electrical bias voltage REF to control the opening and closing of the first transistor M1 and transistor seconds M2 by the row exported.And, be respectively in P-type crystal pipe and N-type transistor due to the first transistor and transistor seconds, therefore to each other always one open and another close.Be understandable that, the level height of predetermined electrical bias voltage REF and the actual crystal tubing type of the first transistor M1 and transistor seconds M2 select the significant level of signal CS to be that high level or low level decide by row, do not repeat them here.
The source electrode of the first transistor M1 is connected top rake width signal OE2 with in drain electrode, and another connects the first end (being specially right-hand member in the drawings) of the second digital varistor DPR2.Such as, the first transistor M1 in Fig. 5 is specially N-type transistor, therefore can open when operational amplifier OP exports high level; And the electrode connecting top rake width signal OE2 is specially the drain electrode of this first transistor M1, the electrode connecting the first end of the second digital varistor DPR2 is specially the source electrode of this first transistor M1.
The source electrode of transistor seconds M2 is connected top rake width signal OE2 with in drain electrode, and another connects top rake unit 23 to export the top rake width signal GVOFF after above-mentioned modulation.Such as, the transistor seconds M2 in Fig. 5 is specially P-type crystal pipe, therefore can open when operational amplifier OP output low level; And the electrode connecting top rake width signal OE2 is specially the drain electrode of this transistor seconds M2, the electrode connecting the first end of top rake unit 23 is specially the source electrode of this transistor seconds M2.Be understandable that, the unlatching of transistor seconds M2 can directly using the voltage turn-on of top rake width signal OE2 to top rake unit 23 part as top rake width signal GVOFF, the waveform shown in this with Fig. 4 is consistent.
In addition, the control end (being specially lower end in the drawings) of the second digital varistor DPR2 connects bandwidth modulation signals RES-C1; Second end (being specially left end in the drawings) of the second digital varistor DPR2 connects the input end of trigger TR, and is connected with common port through the two ends of the first electric capacity C1.Meanwhile, the output terminal of trigger TR is connected with top rake unit 23, for exporting high level at input end higher than during predetermined potential.Wherein, when above-mentioned bandwidth modulation signals RES-C1 comprises predetermined quantity square-wave pulse (such as shown in Fig. 4) within each clock period, the second digital varistor DPR2 can according to the resistance value controlled in each clock period between the quantity determination first end of the square-wave pulse that termination receives and the second end.Thus, the second digital varistor DPR2 that resistance value is controlled by bandwidth modulation signals RES-C1 and the first electric capacity C1 and trigger TR forms RC delay circuit, that is: the RC circuit that the second digital varistor DPR2 and the first electric capacity C1 form can make the voltage of trigger TR input end slowly rise according to the level corresponding with the product of resistance value and capacitance in the rising edge place of top rake width signal OE2 when the first transistor M1 opens, trigger TR at input end not higher than output low level during above-mentioned predetermined potential, and higher than during above-mentioned predetermined potential export high level realize the delayed of rising edge, in like manner, this RC delay circuit of falling edge of top rake width signal OE2 can realize the delayed of negative edge.Thus, the resistance of the second digital varistor DPR2 can be changed to adjust the amplitude of signal lag by bandwidth modulation signals RES-C1, realize the adjustment of the top rake width corresponded to described by above-mentioned Fig. 4.
In Figure 5, top rake unit 23 is specifically arranged in DC output circuit (DC-DC), can circuit structure add and/or multiplexing mode realize, do not repeat them here.In addition, the circuit structure of the arbitrary portion in any one display driver circuit above-mentioned can be replaced by the circuit structure with equivalent signals input/output relation, such as can adopt the digital signal processing chip (DigitalSignalProcess being loaded with corresponding digital signal handling procedure, or field programmable gate array (Field-ProgrammableGateArray DSP), FPGA) realize, the utility model does not limit this.
In addition, as a kind of example of setting position of display driver circuit, Fig. 6 is the setting position schematic diagram of a kind of display driver circuit in the utility model embodiment.Show the viewing area A-A of display panel see Fig. 6, Fig. 6 and be arranged on the display driver circuit of viewing area A-A periphery.Particularly, display driver circuit comprises the grid scan drive circuit SCAN arranging viewing area A-A side on a display panel, this grid scan drive circuit is directly connected with above-mentioned multirow grid sweep trace, with according to the grid low level signal VGL that receives and gate voltage signal VON for every a line grid sweep trace provides gate drive signal.Simultaneously, display driver circuit also comprises the Timing driver unit 21 (be specially sequential control circuit or be arranged in sequential control circuit) be arranged on flexible PCB (being arranged on display panel side), depth modulation module 22a, width modulation module 22b, top rake unit 23 (being arranged in DC output circuit), and unshowned data drive circuit in accompanying drawing.Can find out, except Timing driver unit 21 is also for grid scan drive circuit SCAN provides except grid control signal OE1, the signal transmission relation shown in Fig. 6 is all consistent with mentioned above, does not repeat them here.And fasten and it should be noted that arranging pass, one or two in depth modulation module 22a and width modulation module 22b can be arranged on and can be arranged in DC output circuit (DC-DC) in sequential control circuit (TCON), also, can also as independent circuits vibrational power flow between sequential control circuit and DC output circuit, the utility model does not limit this.
Based on the design of same utility model, the utility model embodiment provides a kind of display device, and this display device comprises any one display driver circuit above-mentioned.It should be noted that, the display device in the present embodiment can be: any product or parts with Presentation Function such as display panel, Electronic Paper, mobile phone, panel computer, televisor, notebook computer, digital album (digital photo frame), navigating instrument.Such as corresponding with Fig. 6, this display device can comprise scan drive circuit, and this scan drive circuit connects top rake unit, and for receiving the gate voltage signal from top rake unit.Be understandable that, owing to including any one display driver circuit above-mentioned, therefore the display device that the utility model embodiment provides can solve between pixel that in prior art, different rows grid sweep trace connects and occur the charging effect problem that there were significant differences, and make the pixel charging effect adjusting manufactured goods become possibility, be conducive to the lifting of display effect, and the reduction of the cost of the aspect such as later stage test, maintenance.
Based on the design of same utility model, Fig. 7 is the steps flow chart schematic diagram of a kind of display drive method in the utility model embodiment.See Fig. 7, this display drive method comprises:
Step 701: generate the first control signal comprising top rake width signal and top rake depth signal based on default clock signal, and comprise the second control signal of bandwidth modulation signals and/or depth modulation signal;
Step 702: modulate the first control signal according to the second control signal;
Step 703: before output gate voltage signal, according to the first control signal after modulated, top rake process is carried out to gate voltage signal.
Be understandable that, the principle of work of any one display driver circuit above-mentioned all can be considered as a kind of embodiment of the display drive method of the utility model embodiment, and with digital signal processing chip (DigitalSignalProcess, or field programmable gate array (Field-ProgrammableGateArray DSP), etc. FPGA) other display driver circuits that the mode that equal circuit structure is replaced obtains also obviously apply the method that the utility model embodiment provides, therefore the display drive method idiographic flow of the utility model embodiment does not repeat them here.It can be seen, the display drive method that the utility model embodiment provides can solve between pixel that in prior art, different rows grid sweep trace connects and occur the charging effect problem that there were significant differences, and make the pixel charging effect adjusting manufactured goods become possibility, be conducive to the lifting of display effect, and the reduction of the cost of the aspect such as later stage test, maintenance.
It should be noted that in description of the present utility model, term " on ", the orientation of the instruction such as D score or position relationship be based on orientation shown in the drawings or position relationship, only the utility model and simplified characterization for convenience of description, instead of the device of instruction or hint indication or element must have specific orientation, with specific azimuth configuration and operation, therefore can not be interpreted as restriction of the present utility model.Unless otherwise clearly defined and limited, term " installation ", " being connected ", " connection " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or connect integratedly; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals.For the ordinary skill in the art, the concrete meaning of above-mentioned term in the utility model can be understood as the case may be.
In instructions of the present utility model, describe a large amount of detail.But can understand, embodiment of the present utility model can be put into practice when not having these details.In some instances, be not shown specifically known method, structure and technology, so that not fuzzy understanding of this description.
Similarly, be to be understood that, to disclose and to help to understand in each utility model aspect one or more to simplify the utility model, in the description above to exemplary embodiment of the present utility model, each feature of the present utility model is grouped together in single embodiment, figure or the description to it sometimes.But, the method for the disclosure should not explained the following intention in reflection: namely the utility model required for protection requires feature more more than the feature clearly recorded in each claim.Or rather, as the following claims reflect, all features of utility model aspect disclosed single embodiment before being to be less than.Therefore, the claims following embodiment are incorporated to this embodiment thus clearly, and wherein each claim itself is as independent embodiment of the present utility model.
It should be noted that above-described embodiment is described the utility model instead of limits the utility model, and those skilled in the art can design alternative embodiment when not departing from the scope of claims.In the claims, any reference symbol between bracket should be configured to limitations on claims.Word " comprises " not to be got rid of existence and does not arrange element in the claims or step.Word "a" or "an" before being positioned at element is not got rid of and be there is multiple such element.The utility model can by means of including the hardware of some different elements and realizing by means of the computing machine of suitably programming.In the unit claim listing some devices, several in these devices can be carry out imbody by same hardware branch.Word first, second and third-class use do not represent any order.Can be title by these word explanations.
Last it is noted that above each embodiment is only in order to illustrate the technical solution of the utility model, be not intended to limit; Although be described in detail the utility model with reference to foregoing embodiments, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of each embodiment technical scheme of the utility model, it all should be encompassed in the middle of the scope of claim of the present utility model and instructions.
Claims (9)
1. a display driver circuit, is characterized in that, comprises timing control unit, modulating unit and top rake unit, wherein:
Described timing control unit connects described modulating unit, for generating the first control signal comprising top rake width signal and top rake depth signal based on default clock signal, and comprises the second control signal of bandwidth modulation signals and/or depth modulation signal;
Described modulating unit connects described top rake unit, for modulating described first control signal according to described second control signal;
Described top rake unit is used for before output gate voltage signal, carries out top rake process according to by the first control signal after described modulating unit modulation to gate voltage signal.
2. display driver circuit according to claim 1, is characterized in that, described modulating unit comprises depth modulation module; Described depth modulation module is used for the amplitude adjusting described top rake depth signal according to described depth modulation signal.
3. display driver circuit according to claim 2, is characterized in that, described depth modulation module comprises the first digital varistor that control end connects described depth modulation signal; The first end of described first digital varistor connects common port; Second end of described first digital varistor connects described top rake unit, and connects described top rake depth signal through the first fixed value resistance.
4. display driver circuit according to claim 3, is characterized in that, described depth modulation signal comprises the square-wave pulse of predetermined quantity within each clock period; Described first digital varistor is used for according to the resistance value controlled in each clock period between the quantity determination first end of the square-wave pulse that termination receives and the second end.
5. display driver circuit according to claim 1, is characterized in that, described timing control unit also selects signal for generating row; Described modulating unit comprises width modulation module; Described width modulation module is used for selecting signal to be that the phase place of described top rake width signal in the period of significant level adjusts forward or backward according to described bandwidth modulation signals to row described in each.
6. display driver circuit according to claim 5, is characterized in that, described width modulation module comprises operational amplifier, the first transistor, transistor seconds, the second digital varistor, the first electric capacity and trigger, wherein:
Positive terminal and the end of oppisite phase of described operational amplifier are connected one that described row selects in signal and predetermined electrical bias voltage respectively, and output terminal connects the grid of described the first transistor and the grid of described transistor seconds;
Described the first transistor and transistor seconds are respectively one in P-type crystal pipe and N-type transistor; The source electrode of described the first transistor is connected described top rake width signal with in drain electrode, and another connects the first end of described second digital varistor; The source electrode of described transistor seconds is connected described top rake width signal with in drain electrode, and another connects described top rake unit;
The control end of described second digital varistor connects described bandwidth modulation signals; Second end of described second digital varistor connects the input end of described trigger, and is connected with common port through the two ends of described first electric capacity;
The output terminal of described trigger is connected with described top rake unit, for exporting high level at input end higher than during predetermined potential.
7. display driver circuit according to claim 6, is characterized in that, described bandwidth modulation signals comprises the square-wave pulse of predetermined quantity within each clock period; Described second digital varistor is used for according to the resistance value controlled in each clock period between the quantity determination first end of the square-wave pulse that termination receives and the second end.
8. a display device, is characterized in that, comprises the display driver circuit according to any one of claim 1 to 7.
9. display device according to claim 8, is characterized in that, described display device also comprises scan drive circuit; Described scan drive circuit connects described top rake unit, for receiving the gate voltage signal from described top rake unit.
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| CN201520891589.9U CN205092045U (en) | 2015-11-09 | 2015-11-09 | Display driver circuit, display device |
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| CN201520891589.9U CN205092045U (en) | 2015-11-09 | 2015-11-09 | Display driver circuit, display device |
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| CN205092045U true CN205092045U (en) | 2016-03-16 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105206248A (en) * | 2015-11-09 | 2015-12-30 | 重庆京东方光电科技有限公司 | Display driving circuit, display device and display driving method |
| CN109272953A (en) * | 2018-10-30 | 2019-01-25 | 惠科股份有限公司 | Signal adjustment circuit and method, display device |
| CN110767186A (en) * | 2019-09-29 | 2020-02-07 | 福建华佳彩有限公司 | Driving method of dual-gate panel |
| CN111243484A (en) * | 2020-02-25 | 2020-06-05 | 福建华佳彩有限公司 | Driving method of double-grid panel for eliminating straight lines |
| WO2020118847A1 (en) * | 2018-12-11 | 2020-06-18 | 深圳市华星光电半导体显示技术有限公司 | Display device and driving method thereof |
| WO2023102956A1 (en) * | 2021-12-07 | 2023-06-15 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display panel |
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2015
- 2015-11-09 CN CN201520891589.9U patent/CN205092045U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105206248A (en) * | 2015-11-09 | 2015-12-30 | 重庆京东方光电科技有限公司 | Display driving circuit, display device and display driving method |
| WO2017080298A1 (en) * | 2015-11-09 | 2017-05-18 | Boe Technology Group Co., Ltd. | Display apparatus, drive circuit, and drive method |
| CN105206248B (en) * | 2015-11-09 | 2019-07-05 | 重庆京东方光电科技有限公司 | Display driver circuit, display device and display driving method |
| CN109272953A (en) * | 2018-10-30 | 2019-01-25 | 惠科股份有限公司 | Signal adjustment circuit and method, display device |
| WO2020118847A1 (en) * | 2018-12-11 | 2020-06-18 | 深圳市华星光电半导体显示技术有限公司 | Display device and driving method thereof |
| CN110767186A (en) * | 2019-09-29 | 2020-02-07 | 福建华佳彩有限公司 | Driving method of dual-gate panel |
| CN111243484A (en) * | 2020-02-25 | 2020-06-05 | 福建华佳彩有限公司 | Driving method of double-grid panel for eliminating straight lines |
| WO2023102956A1 (en) * | 2021-12-07 | 2023-06-15 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and display panel |
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