CN205085328U - SOP biserial semiconductor integrated circuit chip pin shear tool - Google Patents

SOP biserial semiconductor integrated circuit chip pin shear tool Download PDF

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Publication number
CN205085328U
CN205085328U CN201520861197.8U CN201520861197U CN205085328U CN 205085328 U CN205085328 U CN 205085328U CN 201520861197 U CN201520861197 U CN 201520861197U CN 205085328 U CN205085328 U CN 205085328U
Authority
CN
China
Prior art keywords
flat
nose pliers
biserial
sop
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201520861197.8U
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Chinese (zh)
Inventor
李欣林
张正鸿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHENGDU LATEST ELECTRONIC TECHNOLOGY Co Ltd
Original Assignee
CHENGDU LATEST ELECTRONIC TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHENGDU LATEST ELECTRONIC TECHNOLOGY Co Ltd filed Critical CHENGDU LATEST ELECTRONIC TECHNOLOGY Co Ltd
Priority to CN201520861197.8U priority Critical patent/CN205085328U/en
Application granted granted Critical
Publication of CN205085328U publication Critical patent/CN205085328U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Abstract

The utility model discloses a SOP biserial semiconductor integrated circuit chip pin shear tool, it includes mould (1), lower mould (2), plummer (3), pull -out screw (4), spring (5) and mutual articulated flat -nose pliers A (6) and flat -nose pliers B (7), be provided with step hole (9) of intercommunication flat -nose pliers B (7) breach (8) on flat -nose pliers B (7), the both sides of going up mould (1) are provided with side cut A (10), the both sides of lower mould (2) are provided with side cut B (11), be provided with baffle (12) and square hole (13) between two side cut B (11), be provided with screw hole c (16) on kicking block (14), dull and stereotyped (15) set up and enclose the stepping intra -area in two side cut B (11) and baffle (12), screw hole c (16) the threaded connection on step hole (9) and kicking block (14) is run through in pull -out screw (4). The beneficial effects of the utility model are that: low cost, cut the effect good, improve and cut efficiency, alleviate workman intensity of labour.

Description

A kind of SOP biserial semiconductor integrated circuit chip pin shearing instrument
Technical field
The utility model relates to the technical field of semiconductor integrated circuit chip pin shearing, particularly a kind of SOP biserial semiconductor integrated circuit chip pin shearing instrument.
Background technology
Existing SOP biserial semiconductor integrated circuit chip pin is all by manually carrying out shearing and processing, its operating procedure is: first take as SOP biserial semiconductor integrated circuit chip in Fig. 1, rule on the pin wanting cutting again, shear along line place according to designing requirement with scissors again, after shearing as shown in Figure 2, finally the pin of SOP biserial semiconductor integrated circuit chip is welded as shown in Figure 3 with printed circuit board, by this cut mode effect extreme difference, inefficiency, and it is higher to the skill set requirements of employee, in addition, manually carry out adding easily damaging device pin man-hour, the economic benefit of enterprise is greatly reduced by the mode manually sheared, and be difficult to meet the larger demand of market SOP biserial semiconductor integrated circuit chip, therefore do not promote the use of.
Utility model content
The purpose of this utility model is the shortcoming overcoming prior art, provides the SOP biserial semiconductor integrated circuit chip pin shearing instrument that a kind of structure is simple, with low cost, shear effect is excellent, improve shear efficiency, alleviate labor strength.
The purpose of this utility model is achieved through the following technical solutions: a kind of SOP biserial semiconductor integrated circuit chip pin shearing instrument, it comprises patrix, counterdie, plummer, rise and pull out screw, spring and the flat-nose pliers A be hinged and flat-nose pliers B, described flat-nose pliers A and the inner side of flat-nose pliers B are provided with breach, flat-nose pliers B is provided with the stepped hole of the breach being communicated with flat-nose pliers B, described patrix is arranged in the breach of flat-nose pliers A, the both sides of patrix are provided with trimming A, described counterdie is arranged in the breach of flat-nose pliers B, the both sides of counterdie are provided with trimming B, baffle plate and square hole is provided with between two trimming B, described plummer is made up of jacking block and flat board, jacking block is fixed on flat board, jacking block to be arranged in square hole and can to move up and down in square hole, jacking block is provided with screwed hole c, flat board is arranged on two trimming B and baffle plate surrounds in region, described rising is pulled out screw and is run through stepped hole and be threaded with the screwed hole c on jacking block, described spring housing rise pull out on screw, one end of spring has been fixed on pulls out on screw, the other end of spring is fixed on flat-nose pliers B.
Described patrix is provided with screwed hole a, patrix to be threaded with screwed hole a through flat-nose pliers A through mounting screw a and to be fixed on flat-nose pliers A.
Described counterdie is provided with screwed hole b, counterdie to be threaded with screwed hole b through flat-nose pliers B through mounting screw b and to be fixed on flat-nose pliers B.
The utility model has the following advantages: the utility model structure is simple, with low cost, shear effect is excellent, improve shear efficiency, alleviate labor strength.
Accompanying drawing explanation
Fig. 1 is the schematic diagram before SOP biserial semiconductor integrated circuit chip pin shearing;
Fig. 2 is the rear schematic diagram of SOP biserial semiconductor integrated circuit chip pin shearing
Fig. 3 is SOP biserial semiconductor integrated circuit chip and printed circuit board welded structure schematic diagram;
Fig. 4 is structural representation of the present utility model;
Fig. 5 is the A direction view of flat-nose pliers A and the flat-nose pliers B be hinged in Fig. 4;
Fig. 6 is the structural representation of patrix of the present utility model;
Fig. 7 is the structural representation of counterdie of the present utility model;
Fig. 8 is the structural representation of plummer of the present utility model;
In figure, 1-patrix, 2-counterdie, 3-plummer, 4-rises and pulls out screw, 5-spring, 6-flat-nose pliers A, 7-flat-nose pliers B, 8-breach, 9-stepped hole, 10-trimming A, 11-trimming B, 12-baffle plate, 13-square hole, 14-jacking block, 15-is dull and stereotyped, 16-screwed hole c, 17-screwed hole a, 18-mounting screw a, 19-screwed hole b, 20-SOP biserial semiconductor integrated circuit chip.
Detailed description of the invention
Be further described the utility model below in conjunction with accompanying drawing, protection domain of the present utility model is not limited to the following stated:
As Figure 4-8, a kind of SOP biserial semiconductor integrated circuit chip pin shearing instrument, it comprises patrix 1, counterdie 2, plummer 3, rise and pull out screw 4, spring 5 and the flat-nose pliers A6 be hinged and flat-nose pliers B7, described flat-nose pliers A6 and the inner side of flat-nose pliers B7 are provided with breach 8, flat-nose pliers B7 is provided with the stepped hole 9 of the breach 8 being communicated with flat-nose pliers B7, described patrix 1 is arranged in the breach 8 of flat-nose pliers A6, the both sides of patrix 1 are provided with trimming A10, described counterdie 2 is arranged in the breach 8 of flat-nose pliers B7, the both sides of counterdie 2 are provided with trimming B11, baffle plate 12 and square hole 13 is provided with between two trimming B11, baffle plate 12 is for limiting the effect of SOP biserial semiconductor integrated circuit chip position, also serve the effect of location simultaneously, to ensure to cut precision.
As Figure 4-8, plummer 3 is made up of jacking block 14 and dull and stereotyped 15, jacking block 14 is fixed on dull and stereotyped 15, jacking block 14 to be arranged in square hole 13 and can to move up and down in square hole 13, jacking block 14 is provided with screwed hole c16, dull and stereotyped 15 be arranged on two trimming B11 and baffle plate 12 surround in region, described rising is pulled out screw 4 and is run through stepped hole 9 and be threaded with the screwed hole c16 on jacking block 14, described spring 5 has been enclosed within and has pulled out on screw 4, one end of spring 5 has been fixed on pulls out on screw 4, and the other end of spring 5 is fixed on flat-nose pliers B7.Described patrix 1 and the material of counterdie 2 are high-speed tool steel W18Cr4.
As shown in figs. 4-7, patrix 1 is provided with screwed hole a17, patrix 1 to be threaded with screwed hole a17 through flat-nose pliers A6 through mounting screw a18 and to be fixed on flat-nose pliers A6.Counterdie 2 is provided with screwed hole b19, counterdie 2 to be threaded with screwed hole b19 through flat-nose pliers B7 through mounting screw b and to be fixed on flat-nose pliers B7.
The course of work of the present utility model is as follows: first open flat-nose pliers A6 and flat-nose pliers B7, again the pin of SOP biserial semiconductor integrated circuit chip 20 both sides before shearing is ridden on two trimming B11 respectively, close up flat-nose pliers A6 and flat-nose pliers B7 subsequently, under the acting in conjunction of patrix 1 and counterdie 2, make the pin brake forming of SOP biserial semiconductor integrated circuit chip 20, after trimming A10 and trimming B11 closes up, the unnecessary pin of SOP biserial semiconductor integrated circuit chip 20 is cut away, last upwards having pressed pulls out screw 4, rise and pull out screw 4 flat board 15 is up pushed up, dull and stereotyped 15 by finished product SOP biserial semiconductor integrated circuit chip 20 jack-up, thus facilitate the finished product of taking of workman, and whole operation is very simple, greatly alleviate the labour intensity of workman, further increase the shear efficiency of pin, improve economic benefit.

Claims (3)

1. a SOP biserial semiconductor integrated circuit chip pin shearing instrument, it is characterized in that: it comprises patrix (1), counterdie (2), plummer (3), rise and pull out screw (4), spring (5) and the flat-nose pliers A(6 be hinged) and flat-nose pliers B(7), described flat-nose pliers A(6) and flat-nose pliers B(7) inner side be provided with breach (8), flat-nose pliers B(7) on be provided be communicated with flat-nose pliers B(7) the stepped hole (9) of breach (8), described patrix (1) is arranged at flat-nose pliers A(6) breach (8) in, the both sides of patrix (1) are provided with trimming A(10), described counterdie (2) is arranged at flat-nose pliers B(7) breach (8) in, the both sides of counterdie (2) are provided with trimming B(11), two trimming B(11) between be provided with baffle plate (12) and square hole (13), described plummer (3) is made up of jacking block (14) and dull and stereotyped (15), jacking block (14) is fixed on flat board (15), jacking block (14) to be arranged in square hole (13) and can to move up and down in square hole (13), (14) are provided with screwed hole c(16 to jacking block), dull and stereotyped (15) are arranged on two trimming B(11) surround in region with baffle plate (12), described rising is pulled out screw (4) and is run through stepped hole (9) and the screwed hole c(16 on jacking block (14)) be threaded, described spring (5) has been enclosed within and has pulled out on screw (4), one end of spring (5) has been fixed on pulls out on screw (4), the other end of spring (5) is fixed on flat-nose pliers B(7) on.
2. a kind of SOP biserial semiconductor integrated circuit chip pin shearing instrument according to claim 1, it is characterized in that: described patrix (1) is provided with screwed hole a(17), patrix (1) is through mounting screw a(18) through flat-nose pliers A(6) and with screwed hole a(17) be threaded and be fixed on flat-nose pliers A(6) on.
3. a kind of SOP biserial semiconductor integrated circuit chip pin shearing instrument according to claim 1, it is characterized in that: described counterdie (2) is provided with screwed hole b(19), counterdie (2) through mounting screw b through flat-nose pliers B(7) with screwed hole b(19) be threaded and be fixed on flat-nose pliers B(7) on.
CN201520861197.8U 2015-11-02 2015-11-02 SOP biserial semiconductor integrated circuit chip pin shear tool Expired - Fee Related CN205085328U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201520861197.8U CN205085328U (en) 2015-11-02 2015-11-02 SOP biserial semiconductor integrated circuit chip pin shear tool

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201520861197.8U CN205085328U (en) 2015-11-02 2015-11-02 SOP biserial semiconductor integrated circuit chip pin shear tool

Publications (1)

Publication Number Publication Date
CN205085328U true CN205085328U (en) 2016-03-16

Family

ID=55476050

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201520861197.8U Expired - Fee Related CN205085328U (en) 2015-11-02 2015-11-02 SOP biserial semiconductor integrated circuit chip pin shear tool

Country Status (1)

Country Link
CN (1) CN205085328U (en)

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C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160316

Termination date: 20181102