CN205069593U - GPP chip lobe of a leaf structure - Google Patents
GPP chip lobe of a leaf structure Download PDFInfo
- Publication number
- CN205069593U CN205069593U CN201520815183.2U CN201520815183U CN205069593U CN 205069593 U CN205069593 U CN 205069593U CN 201520815183 U CN201520815183 U CN 201520815183U CN 205069593 U CN205069593 U CN 205069593U
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- chip
- glass layer
- silicon chip
- gpp
- passivation glass
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Abstract
The utility model provides a GPP chip lobe of a leaf structure, including GPP chip, silicon chip or passivation glass layer, mask piece, be fixed with silicon chip or passivation glass layer on the GPP chip, there is the blind hole mask piece bottom, and blind hole structural shapes and silicon chip or passivation glass layer are in full accord, and the mask piece sticiss the cover on silicon chip or passivation glass layer, makes silicon chip or passivation glass layer inlay in the blind hole of mask piece bottom. The utility model discloses an adopt " concave " shape blast mask piece for the mode of the available blast of lobe of a leaf is gone on, can fine protection glass passivation layer avoids the lobe of a leaf course of working, thereby makes processed GPP chip silicon chip or the passivation glass layer not to have an avalanche phenomenon, the chip expose edge surfaces that also can not lead to a simultaneously metallization layer oxidation.
Description
Technical field
The utility model relates to a kind of GPP chip segmented pie structure, belongs to field of chip manufacture technology.
Background technology
The sliver mode that current GPP chip is commonly used is mainly: emery wheel cutting and laser cutting.Emery wheel cutting can only processing linear, circular GPP chip can not be met and even have the sliver demand of camber line edge GPP chip, although laser cutting can carry out sliver to camber line edge GPP chip, but this sliver mode easily causes GPP chip edge silicon chip or the avalanche of passivation glass layer and localized hyperthermia can cause the side metallization of chip edge to occur oxidative phenomena in various degree, not only affect product appearance, the electrical quantity of product is also had a certain impact simultaneously.
Utility model content
For solving the problems of the technologies described above; the utility model provides a kind of GPP chip segmented pie structure; this GPP chip segmented pie structure is by adopting " recessed " shape blast mask sheet; sliver can be undertaken by the mode of blast; can well cover glass passivation layer from the sliver course of processing; thus make the GPP chip silicon chip that processes or passivation glass layer without avalanche phenomenon, the chip edge side metallization oxidation that simultaneously also can not cause.
The utility model is achieved by the following technical programs.
A kind of GPP chip segmented pie structure that the utility model provides, comprises GPP chip, silicon chip or passivation glass layer, mask sheet; Described GPP chip is fixed with silicon chip or passivation glass layer; Have blind hole bottom described mask sheet, blind hole structure shape and silicon chip or passivation glass layer completely the same, mask sheet presses and covers on silicon chip or passivation glass layer, and silicon chip or passivation glass layer are embedded in the blind hole bottom mask sheet.
Described GPP chip, silicon chip or passivation glass layer, mask sheet are circle.
The height of described mask sheet is 1.5 ~ 2 times of silicon chip or passivation glass layer height.
The beneficial effects of the utility model are: by adopting " recessed " shape blast mask sheet; sliver can be undertaken by the mode of blast; can well cover glass passivation layer from the sliver course of processing; thus make the GPP chip silicon chip that processes or passivation glass layer without avalanche phenomenon, the chip edge side metallization oxidation that simultaneously also can not cause.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model;
In figure: 1-GPP chip, 2-silicon chip or passivation glass layer, 3-mask sheet.
Embodiment
Further describe the technical solution of the utility model below, but described in claimed scope is not limited to.
A kind of GPP chip segmented pie structure as shown in Figure 1, comprises GPP chip 1, silicon chip or passivation glass layer 2, mask sheet 3; Described GPP chip 1 is fixed with silicon chip or passivation glass layer 2; Have blind hole bottom described mask sheet 3, blind hole structure shape and silicon chip or passivation glass layer 2 completely the same, mask sheet 3 presses and covers on silicon chip or passivation glass layer 2, and silicon chip or passivation glass layer 2 are embedded in the blind hole bottom mask sheet 3.
Thus, as the selection that the present invention is the most frequently used at present, described GPP chip 1, silicon chip or passivation glass layer 2, mask sheet 3 are circle.
Further, for ensureing the smooth and easy of the sliver course of processing, effectively save material cost again, the height of described mask sheet 3 is 1.5 ~ 2 times of silicon chip or passivation glass layer 2 height simultaneously.
Claims (3)
1. a GPP chip segmented pie structure, comprise GPP chip (1), silicon chip or passivation glass layer (2), mask sheet (3), it is characterized in that: described GPP chip (1) is fixed with silicon chip or passivation glass layer (2); Blind hole is arranged at described mask sheet (3) bottom, blind hole structure shape and silicon chip or passivation glass layer (2) completely the same, mask sheet (3) presses and covers on silicon chip or passivation glass layer (2), and silicon chip or passivation glass layer (2) are embedded in the blind hole of mask sheet (3) bottom.
2. GPP chip segmented pie structure as claimed in claim 1, is characterized in that: described GPP chip (1), silicon chip or passivation glass layer (2), mask sheet (3) are circle.
3. GPP chip segmented pie structure as claimed in claim 1, is characterized in that: the height of described mask sheet (3) is 1.5 ~ 2 times of silicon chip or passivation glass layer (2) height.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201520815183.2U CN205069593U (en) | 2015-10-20 | 2015-10-20 | GPP chip lobe of a leaf structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201520815183.2U CN205069593U (en) | 2015-10-20 | 2015-10-20 | GPP chip lobe of a leaf structure |
Publications (1)
Publication Number | Publication Date |
---|---|
CN205069593U true CN205069593U (en) | 2016-03-02 |
Family
ID=55396112
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201520815183.2U Active CN205069593U (en) | 2015-10-20 | 2015-10-20 | GPP chip lobe of a leaf structure |
Country Status (1)
Country | Link |
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CN (1) | CN205069593U (en) |
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2015
- 2015-10-20 CN CN201520815183.2U patent/CN205069593U/en active Active
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |