CN205029334U - Frequency transformer's suppression circuit that shoves that stimulates magnetism - Google Patents
Frequency transformer's suppression circuit that shoves that stimulates magnetism Download PDFInfo
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- CN205029334U CN205029334U CN201520743288.1U CN201520743288U CN205029334U CN 205029334 U CN205029334 U CN 205029334U CN 201520743288 U CN201520743288 U CN 201520743288U CN 205029334 U CN205029334 U CN 205029334U
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Abstract
The utility model discloses a frequency transformer's suppression circuit that shoves that stimulates magnetism relates to the control field of high -pressure dynamo power supply converter. Should stimulate magnetism and shove suppression circuit and include main circuit and control circuit, the main circuit includes power wire resistor, control switch, voltage sensor, current sensor, power wire resistor's both ends and receive control switch's main contacts on, power wire resistor and control switch constitute the external adjustable impedance of transformer, voltage sensor passes through current sensor and is connected with the transformer, control circuit includes time relay and the analog signal accepting circuit, analog signal comparison circuit, logic level converting circuit, the switching value input/output circuit that link to each other in order, and time relay links to each other with logic level converting circuit, and switching value input/output circuit passes through the cable and links to each other with time relay 2. The utility model discloses temporal the stimulating magnetism of electricity is shoved on effectively reducing the transformer, strengthens the reliability of electric wire netting.
Description
Technical field
The utility model relates to the control field of high-voltage motor supply convertor, and the exiting pour current specifically relating to a kind of Industrial Frequency Transformer suppresses circuit.
Background technology
The input phase shifting transformer of Industrial Frequency Transformer or high-power high voltage frequency converter, powering on combined floodgate moment, because transformer magnetic field is not set up, and high-power transformer internal resistance is general very little, in this case, be equivalent to transformer short-circuit, electrical network occurs larger exiting pour current.Conventional method directly electrical network and transformer is connected by switches such as high-pressure vacuum breakers.
There is following defect in such scheme:
(1) exiting pour current is large especially.High-pressure vacuum breaker closes a floodgate moment, and the exiting pour current of occur persistent oscillation at electrical network end, decaying gradually, exiting pour current amplitude can reach the rated current of 10 times of transformers.
(2) along with the increase of transformer capacity, the internal resistance of transformer reduces thereupon, when combined floodgate powers on, and the increase all corresponding to the time of the amplitude of exiting pour current, the number of oscillation.
(3) exiting pour current causes power input high-tension switch cabinet to trip, and other causing on same electrical network are stopped transport by electric loading.
(4) exiting pour current belongs to harmonic current, brings serious electromagnetic compatibility interference, causes other electricity consumption loaded work pieces of same electrical network abnormal.
Utility model content
The purpose of this utility model is the deficiency in order to overcome above-mentioned background technology, provides a kind of exiting pour current of Industrial Frequency Transformer to suppress circuit, can effectively reduce the exiting pour current of transformer powered on moment, strengthen the reliability of electrical network.
The utility model provides a kind of exiting pour current of Industrial Frequency Transformer to suppress circuit, for transformer L is accessed electrical network Vg, this exiting pour current suppresses circuit to comprise main circuit and control circuit, one end of main circuit is connected with electrical network Vg, the other end is connected with transformer L, it is characterized in that: described main circuit comprises power wire resistor R, control switch K1, voltage sensor PT, current sensor CT, the two ends of power wire resistor R are also received on the main contacts of control switch K1, and power wire resistor R and control switch K1 forms the external adjustable impedance of transformer L jointly; One end of power wire resistor R is connected with electrical network, and the other end is connected with voltage sensor PT, and voltage sensor PT is connected with transformer L by current sensor CT;
Described control circuit comprises analog signal receiving circuit, analog signal comparison circuit, logic level converting circuit, time relay J, On-off signal output circuit, voltage sensor PT, current sensor CT are all connected with analog signal receiving circuit, analog signal receiving circuit is connected with analog signal comparison circuit, analog signal comparison circuit, time relay J are all connected with logic level converting circuit, logic level converting circuit is connected with On-off signal output circuit, and On-off signal output circuit is connected with control switch K1 by cable.
On the basis of technique scheme, described analog signal receiving circuit comprises the first operational amplifier OP1, the second operational amplifier OP2, the output of voltage sensor PT is connected to the in-phase input end of the first operational amplifier OP1 by cable, the voltage signal V that first operational amplifier OP1 receiver voltage transducer PT exports, the voltage signal that the first operational amplifier OP1 exports is V0; The output of current sensor CT is connected to the in-phase input end of the second operational amplifier OP2 by cable, the current signal A that the second operational amplifier OP2 received current transducer CT exports, and the current signal that the second operational amplifier OP2 exports is A0.
On the basis of technique scheme, described analog signal comparison circuit comprises voltage-reference, current reference source, the first comparator CMP1 and the second comparator CMP2, the inverting input of the first comparator CMP1 is connected with voltage-reference, the in-phase input end of the first comparator CMP1 is connected to the output of the first operational amplifier OP1, CMP1 receives the voltage signal V0 that OP1 exports, and the voltage signal that the first comparator CMP1 exports is V1; The inverting input of the second comparator CMP2 is connected with current reference source, and the in-phase input end of the second comparator CMP2 is connected with the output of the second operational amplifier OP2, and CMP2 receives the current signal A0 that OP2 exports, and the current signal that CMP2 exports is A1.
On the basis of technique scheme, the level value of described voltage-reference is rated voltage * 80%.
On the basis of technique scheme, the level value of described current reference source is rated current * 80%.
On the basis of technique scheme, described control switch K1 comprises 3 control interfaces: feedback interface, separating brake interface, combined floodgate interface, and each interface connects 2 cables.
On the basis of technique scheme, described On-off signal output circuit comprises the first optocoupler IN1, the second optocoupler IN2, the 3rd optocoupler IN3, auxiliary relay OC, the input of the first optocoupler IN1 is connected to the starting command of user, and output pin signal is Start; The input of the second optocoupler IN2 is connected to ceasing and desisting order of user, and output pin signal is Stop, and the input of the 3rd optocoupler IN3 is connected to the feedback interface of control switch K1 in main circuit, and output pin signal is State; Auxiliary relay OC is made up of line bag, the first contact OU1, the second contact OU2, the control pin of line bag is connected to logic level converting circuit, first contact OU1 is normally closed point, be connected to the separating brake interface of control switch K1 in main circuit, second contact OU2 is normal battle, is connected to the combined floodgate interface of control switch K1 in main circuit.
On the basis of technique scheme, described logic level converting circuit comprise first with door AND1, second and door AND2, logical circuit LOG, AND1 and AND2 be two gates, function realizes " logical AND ", wherein, AND1 is " three inputs " and door, and AND2 is " dual input " and door; LOG is the logical circuit be made up of triode and diode; Three inputs of AND1 are connected respectively to output, the output of CMP2, the output of time relay J of CMP1, and its signal is respectively V1, A1 and T1, and the signal that AND1 exports is S1; Two inputs of ADN2 are connected respectively to the output of AND1, the output of the second optocoupler IN2, and its signal is respectively S1 and S2, and the signal that AND2 exports is S3; The input of logical circuit LOG comprises State, Stop, Start, is connected respectively to the output of the 3rd optocoupler IN3, the output of the second optocoupler IN2, the output of the first optocoupler IN1, and the control signal that LOG exports is ON/OFF.
On the basis of technique scheme, described time relay J comprises line bag and controls pin, time of delay to arrange pin, output, line bag controls the output that pin is connected to LOG, receive the control signal ON/OFF that LOG exports, the input arranging pin time of delay is the delay time that user is arranged, the output of time relay J is connected with the input of door AND1 with first, and the signal that time relay J exports is high level T1.
On the basis of technique scheme, described cable adopts single core 2.5mm
2copper core polyvinyl chloride insulation sheath braid shielded control cables.
Compared with prior art, advantage of the present utility model is as follows:
(1) the utility model is using power wire resistor R as external impedance, is connected in series in the transformer of user, in Transformer Close moment, as the internal resistance of transformer; When not having external impedance, Transformer Close moment, internal magnetic field is not set up, and exiting pour current is about: Im=Ue/Rdc, Im are exiting pour current, and Ue is switching voltage, and Rdc is the DC impedance of transformer; Because common transformer dc impedance is much smaller than its induction reactance, so exiting pour current just understands oscillatory extinction to rated value after reaching 10 times of rated current, adopt power wire resistor as after external impedance, exiting pour current is about: Im '=Ue/ (Rdc+R), Im ' is for increasing the exiting pour current after external impedance, power wire resistor R is the impedance of external resistance, therefore, theoretically, after adding external impedance, can reduce exiting pour current, the degree of reduction is relevant with the size of external impedance.The utility model is applied in the transformer power up of high-power high voltage frequency converter, uses this circuit to power on to high-voltage high-power transformer, can effectively reduce the exiting pour current of transformer powered on moment, strengthens the reliability of electrical network.
(2) capacity when transformer is larger, and the DC impedance of transformer is less, and according to the theory in (1), exiting pour current amplitude during combined floodgate can be larger, and oscillatory extinction can be longer to the time of rated value.Adopt power wire resistor as external impedance, coordinate the time-delay closing time, utilize the time relay, suitable delay time is provided, allow the exiting pour current of jumbo transformer can decay to rated value in good time.
(3) the utility model utilizes power wire resistor R, coordinates control switch K1, as external impedance, on the transformer during electricity, drops into external impedance; Complete at transformer excitation, after exiting pour current is reduced to rated condition, control switch K1 on power wire resistor R closes, the short circuit two ends of power wire resistor R, electric current is without R, be equivalent to excise external impedance, achieve the adjustment of transformer internal resistance, the exiting pour current of the transformer of user in power up is reduced greatly, can normally run by bringing onto load after the power-up.Because external power wire resistor is in power up, be cascaded with the DC impedance of transformer, reduce exiting pour current, so power input high-tension switch cabinet can not trip due to overcurrent, other that can not cause on same electrical network to be stopped transport inoperable accident by electric loading.
(4) due to electric current that exiting pour current is oscillatory extinction, in the process of oscillatory extinction, stronger EMC (ElectroMagneticCompatibility can be produced, electromagnetic radiation is compatible) interference problem, amplitude, the duration of its electromagnetic radiation intensity and exiting pour current become positively related relation; Adopt power wire resistor as external impedance, reducing exiting pour current when powering on, it also reducing EMC.
Accompanying drawing explanation
Fig. 1 is the structural representation of the exiting pour current suppression circuit of Industrial Frequency Transformer in the utility model embodiment.
Fig. 2 is the practical application scene of the exiting pour current suppression circuit of the Industrial Frequency Transformer that an embodiment of the present utility model provides.
In figure: R is power wire resistor, K1 is the control switch be attempted by R, for dropping into or excision R; PT is voltage sensor, and the voltage signal that PT exports is V; CT is current sensor, and the current signal that CT exports is A; OP1 is the first operational amplifier, and OP2 is the second operational amplifier; CMP1 is the first comparator, and CMP2 is the second comparator; J is the time relay, is made up of line bag and contact; AND1 is first and door, and AND2 is second and door; LOG is the logical circuit be made up of triode and diode; Vg represents electrical network, and K0 represents the switch of user, L indication transformer.
Embodiment
Below in conjunction with drawings and the specific embodiments, the utility model is described in further detail.
Shown in Figure 1, the utility model embodiment provides a kind of exiting pour current of Industrial Frequency Transformer to suppress circuit, and for transformer L is accessed electrical network Vg, this exiting pour current suppresses circuit to comprise main circuit and control circuit, one end of main circuit is connected with electrical network Vg, and the other end is connected with transformer L.Main circuit comprises power wire resistor R, control switch K1, voltage sensor PT, current sensor CT, the two ends of power wire resistor R are also received on the main contacts of control switch K1, and power wire resistor R and control switch K1 forms the external adjustable impedance of transformer L jointly; One end of power wire resistor R is connected with electrical network, and the other end is connected with voltage sensor PT, and voltage sensor PT is connected with transformer L by current sensor CT.
Control circuit comprises analog signal receiving circuit, analog signal comparison circuit, logic level converting circuit, time relay J, On-off signal output circuit, voltage sensor PT, current sensor CT are all connected with analog signal receiving circuit, analog signal receiving circuit is connected with analog signal comparison circuit, analog signal comparison circuit, time relay J are all connected with logic level converting circuit, logic level converting circuit is connected with On-off signal output circuit, and On-off signal output circuit is connected with control switch K1 by 6 cables.
Analog signal receiving circuit comprises the first operational amplifier OP1, the second operational amplifier OP2, the output of voltage sensor PT is connected to the in-phase input end of the first operational amplifier OP1 by cable, the voltage signal V that first operational amplifier OP1 receiver voltage transducer PT exports, the voltage signal that the first operational amplifier OP1 exports is V0; The output of current sensor CT is connected to the in-phase input end of the second operational amplifier OP2 by cable, the current signal A that the second operational amplifier OP2 received current transducer CT exports, and the current signal that the second operational amplifier OP2 exports is A0.
Analog signal comparison circuit comprises voltage-reference, current reference source, the first comparator CMP1 and the second comparator CMP2, the level value of voltage-reference is rated voltage * 80%, the level value of current reference source is rated current * 80%, the inverting input of the first comparator CMP1 is connected with voltage-reference, the in-phase input end of the first comparator CMP1 is connected to the output of the first operational amplifier OP1, CMP1 receives the voltage signal V0 that OP1 exports, and the voltage signal that the first comparator CMP1 exports is V1; The inverting input of the second comparator CMP2 is connected with current reference source, and the in-phase input end of the second comparator CMP2 is connected with the output of the second operational amplifier OP2, and CMP2 receives the current signal A0 that OP2 exports, and the current signal that CMP2 exports is A1.
Control switch K1 comprises 3 control interfaces: feedback interface, separating brake interface, combined floodgate interface, and each interface connects 2 cables.
On-off signal output circuit comprises the first optocoupler IN1, the second optocoupler IN2, the 3rd optocoupler IN3, auxiliary relay OC, and the input of the first optocoupler IN1 is connected to the starting command of user, and output pin signal is Start; The input of the second optocoupler IN2 is connected to ceasing and desisting order of user, and output pin signal is Stop, and the input of the 3rd optocoupler IN3 is connected to the feedback interface of control switch K1 in main circuit, and output pin signal is State; Auxiliary relay OC is made up of line bag, the first contact OU1, the second contact OU2, the control pin of line bag is connected to logic level converting circuit, first contact OU1 is normally closed point, be connected to the separating brake interface of control switch K1 in main circuit, second contact OU2 is normal battle, is connected to the combined floodgate interface of control switch K1 in main circuit.
It is two gates with door AND2, logical circuit LOG, AND1 and AND2 that logic level converting circuit comprises first with door AND1, second, and function realizes " logical AND ", and wherein AND1 is " three inputs " and a door, and AND2 is individual " dual input " and a door; LOG is the logical circuit be made up of triode and diode; Three inputs of AND1 are connected respectively to output, the output of CMP2, the output of time relay J of CMP1, and its signal is respectively V1, A1 and T1, and the signal that AND1 exports is S1; Two inputs of ADN2 are connected respectively to the output of AND1, the output of the second optocoupler IN2, and its signal is respectively S1 and S2, and the signal that AND2 exports is S3; The input of logical circuit LOG comprises State, Stop, Start, is connected respectively to the output of the 3rd optocoupler IN3, the output of the second optocoupler IN2, the output of the first optocoupler IN1, and the control signal that LOG exports is ON/OFF.
Time relay J comprises line bag and controls pin 1, time of delay to arrange pin 2, output, line bag controls the output that pin 1 is connected to LOG, receive the control signal ON/OFF that LOG exports, the input arranging pin 2 time of delay is the delay time that user is arranged, the output of time relay J is connected with the input of door AND1 with first, and the signal that time relay J exports is high level T1.
Cable in the utility model embodiment all adopts KVVP2.5 (single core 2.5mm
2copper core polyvinyl chloride insulation sheath braid shielded control cables) cable.
Operation principle of the present utility model is elaborated as follows:
Voltage on control circuit monitoring transformer and exiting pour current, arrange power wire resistor and connect timing closing time of K switch 1 simultaneously.
Control circuit sends K1 close commands must meet following 3 conditions simultaneously:
(1) transformer voltage is close to rated value,
(2) transformer magnetizing current is close to rated value;
(3) delay time arrives.
Analog signal receiving circuit receives signal V and A of PT and CT primarily of operational amplifier, is V0 and A0 in proportion, delivers in analog signal comparison circuit after decay; Two comparator CMP1 and CMP2 are had in analog signal comparison circuit, CMP1 is used for judging whether V0 reaches 80% rated voltage, its comparative result delivers to the input of the AND1 in logic level converting circuit, CMP2 is used for judging whether A0 reaches 80% rated current, and its comparative result delivers to the input of the AND1 in logic level converting circuit; The signal that time relay J exports delivers to the input of the AND1 in logic level converting circuit; These 3 pins do after " logical AND " process through AND1, judged result is delivered to the pin of AND2, another pin of AND2 receives the stop signal from user, AND2 carries out " logical AND " computing to these two signals, operation result is delivered in the OC of On-off signal output circuit, the output of control OU1 and OU2, OU1 and OU2 respectively controls the disjunction of main circuit K1 by two KVVP2.5 cables and closes; In order to ensure that K1 is working properly, the closed feedback state of K1 is delivered in On-off signal output circuit by two KVVP2.5 cables through IN3, can judge K1 whether regular event by IN3.
Control circuit operation logic is described below:
(1) the output signal V of PT and CT and A is transformed into suitable amplitude V0 and A0 by analog signal receiving circuit; Deliver to respectively on CMP1 and CMP2 of analog signal comparison circuit.
(2) in analog signal comparison circuit, CMP1 judges V0, does not reach 80% rated voltage, V1 output low level, otherwise exports high level; CMP2 judges A0, does not reach 80% rated voltage, A1 output low level, otherwise exports high level.V1 and A1 delivers on the AND1 in logic level converting circuit respectively.
(3) time relay J internal receipt two signals, a delay time being user and arranging, signal is the output signal ON/OFF from LOG in logic level converting circuit, when ON/OFF is high level, time relay J starts, and the time delays arranged according to user closes, and T1 exports high level, delay time does not arrive, T1 output low level; If ON/OFF is low level, T1 is low level always, and time relay J quits work.V1, A1, T1 deliver on the input of AND1 in logic level converting circuit.
(4) in logic level converting circuit, AND1 carries out " logical AND " computing to V1, A1, T1, as long as this three has a signal to be low level, the output signal S1 of AND1 is low level, only have when three is all high level, S1 is just high level, and S1 delivers on the AND2 in logic level converting circuit.
(5) AND2 in logic level converting circuit carries out " logical AND " computing to the S2 that ceases and desist order from the S1 of AND1 and user, as long as both has a signal to be low level, the output signal S3 of AND2 is low level, only have when the two is all high level, S3 is just high level, and S3 delivers on the OC in On-off signal output circuit.
(6) On-off signal output circuit is made up of OC (exporting K1 disjunction order and K1 close commands), IN3, IN1 and IN2.When S3 is low level, the output OU1 of OC keeps normally closed, is delivered on the disjunction command interface of the K1 switch in main circuit by 2 KVVP2.5 cables, makes K1 keep disjunction; And OU2 keeps often opening, delivered on the close commands interface of the K2 switch of main circuit by 2 KVVP2.5 cables, owing to keeping often opening, so K2 can not close, therefore when S3 is low level, K1 remains open; When S3 is high level, the output OU1 of OC disconnects, and the disjunction command interface of K1 switch does not have signal, and OU2 closes, and the close commands interface of K1 switch obtains signal, and then make K1 close, therefore, when S3 is high level, K1 can close.
(7) in order to ensure K1 reliable in action; On-off signal output circuit introduces IN3, its objective is: if having issued K1 close commands, but from IN3, do not detect that it closes; so control circuit will send K1 disjunction order at once, thus protection K1.Its action logic is: IN1, IN2, IN3, after the process of On-off signal output circuit, deliver to the LOG in logic level converting circuit, and LOG circuit carries out logical process according to following principle:
Which kind of situation a () is no matter current is in, once user ceases and desist order, IN2 is effective, and the S2 pin of AND2 is low, and S3 is low level, and the OU1 of OC is effective, and K1 remains open; Export ON/OFF is low level time of delivery (TOD) relay J simultaneously, and time relay J resets.
If b () IN2 is invalid, IN1 is effective, the S2 pin of AND2 is high level, and ON/OFF exports high level to time relay J, and time relay J starts to start, the delay time arranged according to user is waited for, when delay time arrives, the output contact of time relay J closes, and T1 is effective, if now V1, A1 are effective, so S1 is effective; Because now S2 is in high level state, S3 exports high level, and OC is under the control of S3, and OU1 disconnects, and OU2 closes, and K1 is closed under the control of OU2.
If c () OU2 have issued K1 close commands, but from IN3, do not detect that K1 closure state feeds back, then LOG is after logical process, ON/OFF can be placed in low level, and time relay J can quit work, T1 meeting output low level, cause AND1 output low level, AND2 is output low level also, finally causes OU1 to close, OU2 disconnects, and makes K1 disjunction.
Shown in participation Fig. 2, in actual applications, user can arrange a K switch 0, when the transformer of user and electrical network Vg are in off-state, K0 disconnects, time relay J in control circuit is in reset mode, user arranges transformer by control circuit and to power on excitatory parameter, i.e. K1 switching voltage value (70% ~ 90%, acquiescence 80%), K1 switching current value (70% ~ 90%, acquiescence 80%), K1 postpones closing time (0.1s ~ 15s, acquiescence 2s), when user needs transformer to be connected to electrical network, user sends K0 close commands, and control circuit is started working simultaneously, and now K1 is in off-state, when K0 closes, the power wire resistor R be connected with transformer is connected in series in circuit, its effect is equivalent to and increases transformer internal resistance, now electrical network is powered on to transformer excitation by the large internal resistance of equivalence, substantially reduce exiting pour current, through the time of several power frequency cycle, static exciter completes, inner exciting current is stablized, now the output signal A of current sensor CT and the output signal V of voltage sensor PT is once reach the K1 switching voltage value of setting, K1 switching current value, and K1 postpones closing time arrival, in CMP1 and CMP2 of i.e. analog signal comparison circuit, on the AND1 of the logic level converting circuit that its comparison value is delivered to respectively, AND1 exports high level S1 and S2 and delivers on AND2, export high level S3, S3 delivers on the OC circuit in On-off signal output circuit, OU1 is disconnected, OU2 closes, K1 is closed, excision power wire resistor R after K1 is closed, the internal resistance being equivalent to transformer recovers normal, transformer is operated in the direct power supply state of electrical network, bringing onto load can be prepared run.Control circuit is by control K1, when powering on, the internal resistance of power wire resistor and transformer is connected in series, after static exciter completes, by power wire resistor to bypassing, thus equivalence have adjusted the internal resistance of transformer, make it the exiting pour current spy when powering on little, and don't influence zone load running.
Those skilled in the art can carry out various modifications and variations to the utility model embodiment; if these amendments and modification are within the scope of the utility model claim and equivalent technologies thereof, then these revise and modification also within protection range of the present utility model.
The prior art that the content do not described in detail in specification is known to the skilled person.
Claims (10)
1. the exiting pour current of an Industrial Frequency Transformer suppresses circuit, for transformer L is accessed electrical network Vg, this exiting pour current suppresses circuit to comprise main circuit and control circuit, one end of main circuit is connected with electrical network Vg, the other end is connected with transformer L, it is characterized in that: described main circuit comprises power wire resistor R, control switch K1, voltage sensor PT, current sensor CT, the two ends of power wire resistor R are also received on the main contacts of control switch K1, and power wire resistor R and control switch K1 forms the external adjustable impedance of transformer L jointly; One end of power wire resistor R is connected with electrical network, and the other end is connected with voltage sensor PT, and voltage sensor PT is connected with transformer L by current sensor CT;
Described control circuit comprises analog signal receiving circuit, analog signal comparison circuit, logic level converting circuit, time relay J, On-off signal output circuit, voltage sensor PT, current sensor CT are all connected with analog signal receiving circuit, analog signal receiving circuit is connected with analog signal comparison circuit, analog signal comparison circuit, time relay J are all connected with logic level converting circuit, logic level converting circuit is connected with On-off signal output circuit, and On-off signal output circuit is connected with control switch K1 by cable.
2. the exiting pour current of Industrial Frequency Transformer as claimed in claim 1 suppresses circuit, it is characterized in that: described analog signal receiving circuit comprises the first operational amplifier OP1, the second operational amplifier OP2, the output of voltage sensor PT is connected to the in-phase input end of the first operational amplifier OP1 by cable, the voltage signal V that first operational amplifier OP1 receiver voltage transducer PT exports, the voltage signal that the first operational amplifier OP1 exports is V0; The output of current sensor CT is connected to the in-phase input end of the second operational amplifier OP2 by cable, the current signal A that the second operational amplifier OP2 received current transducer CT exports, and the current signal that the second operational amplifier OP2 exports is A0.
3. the exiting pour current of Industrial Frequency Transformer as claimed in claim 2 suppresses circuit, it is characterized in that: described analog signal comparison circuit comprises voltage-reference, current reference source, the first comparator CMP1 and the second comparator CMP2, the inverting input of the first comparator CMP1 is connected with voltage-reference, the in-phase input end of the first comparator CMP1 is connected to the output of the first operational amplifier OP1, CMP1 receives the voltage signal V0 that OP1 exports, and the voltage signal that the first comparator CMP1 exports is V1; The inverting input of the second comparator CMP2 is connected with current reference source, and the in-phase input end of the second comparator CMP2 is connected with the output of the second operational amplifier OP2, and CMP2 receives the current signal A0 that OP2 exports, and the current signal that CMP2 exports is A1.
4. the exiting pour current of Industrial Frequency Transformer as claimed in claim 3 suppresses circuit, it is characterized in that: the level value of described voltage-reference is rated voltage * 80%.
5. the exiting pour current of Industrial Frequency Transformer as claimed in claim 3 suppresses circuit, it is characterized in that: the level value of described current reference source is rated current * 80%.
6. the exiting pour current of Industrial Frequency Transformer as claimed in claim 3 suppresses circuit, and it is characterized in that: described control switch K1 comprises 3 control interfaces: feedback interface, separating brake interface, combined floodgate interface, each interface connects 2 cables.
7. the exiting pour current of Industrial Frequency Transformer as claimed in claim 6 suppresses circuit, it is characterized in that: described On-off signal output circuit comprises the first optocoupler IN1, the second optocoupler IN2, the 3rd optocoupler IN3, auxiliary relay OC, the input of the first optocoupler IN1 is connected to the starting command of user, and output pin signal is Start; The input of the second optocoupler IN2 is connected to ceasing and desisting order of user, and output pin signal is Stop, and the input of the 3rd optocoupler IN3 is connected to the feedback interface of control switch K1 in main circuit, and output pin signal is State; Auxiliary relay OC is made up of line bag, the first contact OU1, the second contact OU2, the control pin of line bag is connected to logic level converting circuit, first contact OU1 is normally closed point, be connected to the separating brake interface of control switch K1 in main circuit, second contact OU2 is normal battle, is connected to the combined floodgate interface of control switch K1 in main circuit.
8. the exiting pour current of Industrial Frequency Transformer as claimed in claim 7 suppresses circuit, it is characterized in that: described logic level converting circuit comprise first with door AND1, second and door AND2, logical circuit LOG, AND1 and AND2 is two gates, function realizes " logical AND ", wherein, AND1 is " three inputs " and door, and AND2 is " dual input " and door; LOG is the logical circuit be made up of triode and diode; Three inputs of AND1 are connected respectively to output, the output of CMP2, the output of time relay J of CMP1, and its signal is respectively V1, A1 and T1, and the signal that AND1 exports is S1; Two inputs of ADN2 are connected respectively to the output of AND1, the output of the second optocoupler IN2, and its signal is respectively S1 and S2, and the signal that AND2 exports is S3; The input of logical circuit LOG comprises State, Stop, Start, is connected respectively to the output of the 3rd optocoupler IN3, the output of the second optocoupler IN2, the output of the first optocoupler IN1, and the control signal that LOG exports is ON/OFF.
9. the exiting pour current of Industrial Frequency Transformer as claimed in claim 8 suppresses circuit, it is characterized in that: described time relay J comprises that line bag controls pin (1), time of delay arranges pin (2), output, line bag controls the output that pin (1) is connected to LOG, receive the control signal ON/OFF that LOG exports, the input arranging pin (2) time of delay is the delay time that user is arranged, the output of time relay J is connected with the input of door AND1 with first, and the signal that time relay J exports is high level T1.
10. the exiting pour current of Industrial Frequency Transformer suppresses circuit as claimed in any one of claims 1-9 wherein, it is characterized in that: described cable adopts single core 2.5mm
2copper core polyvinyl chloride insulation sheath braid shielded control cables.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520743288.1U CN205029334U (en) | 2015-09-23 | 2015-09-23 | Frequency transformer's suppression circuit that shoves that stimulates magnetism |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520743288.1U CN205029334U (en) | 2015-09-23 | 2015-09-23 | Frequency transformer's suppression circuit that shoves that stimulates magnetism |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205029334U true CN205029334U (en) | 2016-02-10 |
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| CN201520743288.1U Expired - Fee Related CN205029334U (en) | 2015-09-23 | 2015-09-23 | Frequency transformer's suppression circuit that shoves that stimulates magnetism |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106053921A (en) * | 2016-08-02 | 2016-10-26 | 中国电力科学研究院 | Step voltage calculation method under symmetrical double-core phase shift transformer load condition |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106053921A (en) * | 2016-08-02 | 2016-10-26 | 中国电力科学研究院 | Step voltage calculation method under symmetrical double-core phase shift transformer load condition |
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