CN205004963U - Controlling device of inverter - Google Patents
Controlling device of inverter Download PDFInfo
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- CN205004963U CN205004963U CN201520664359.9U CN201520664359U CN205004963U CN 205004963 U CN205004963 U CN 205004963U CN 201520664359 U CN201520664359 U CN 201520664359U CN 205004963 U CN205004963 U CN 205004963U
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Abstract
The utility model provides a controlling device of inverter. The utility model relates to a controlling device of inverter, include: sensor, ADC sampling treatment circuit, DSP, CPLD, wherein, the sensor is used for collect motor's operation signal to to move signal transmission for the ADC treatment circuit of sampling, the ADC treatment circuit of sampling for the operation signal conversion who sends the sensor is data signal, sends for CPLD, CPLD for carry out filtering with data signal and handle, and the data signal after will handling sends for DSP, DSP is used for handling the data signal after handling through dc -to -ac converter control algorithm and pulse modulation algorithm, obtains PWM pulse signal to send PWM pulse signal for CPLD, CPLD still is used for sending PWM pulse signal for IGBT drive buffer circuit after carrying out inside protection logical processing to the realization is to the control of dc -to -ac converter. The utility model provides high DSP's processing speed.
Description
Technical field
The utility model relates to technical field of inverter control, particularly relates to a kind of control device for inverter.
Background technology
Traction invertor, is the core in city rail vehicle trailer system, mainly realizes Electric Machine Control, and the various logic in vehicle controls, the functions such as the failure logging in vehicle.Traction invertor needs control device for inverter to control this traction invertor usually, to realize Electric Machine Control, and the logic control in vehicle, failure logging etc.
Existing control device for inverter mainly uses single digital signal processor (DigitalSignalProcessor; being called for short DSP) chip realizes high performance motor control algolithm; complicated pulse modulation algorithm, the function such as virtual protection and troubleshooting.Along with city rail vehicle function gets more and more, requiring that the logic of DSP process gets more and more, occupy the resource that DSP is more, because this reducing the processing speed of DSP, making it the requirement that can not meet Electric Machine Control high-performance treatments.
Utility model content
The utility model provides a kind of control device for inverter, lower to overcome the processing speed of DSP in prior art, can not meet the problem of the requirement of Electric Machine Control high-performance treatments.
The utility model provides a kind of control device for inverter, comprising:
Transducer, analog to digital converter ADC sampling processing circuit, digital signal processor DSP, complex programmable logic device (CPLD);
Wherein, described transducer, is connected with described ADC sampling processing circuit, for gathering the run signal of motor, and described run signal is sent to described ADC sampling processing circuit; Described run signal comprises at least one in analog voltage signal, analog current signal or simulation tach signal;
Described ADC sampling processing circuit, is connected with described CPLD, is converted to digital signal for the run signal sent by described transducer, described digital signal is sent to described CPLD;
Described CPLD, is connected with described DSP, for described digital signal is carried out filtering process, and the digital signal after process is sent to described DSP;
Described DSP, for being processed the digital signal after described process by inverter control algorithm and pulse modulation algorithm, is obtained pulse width modulation (PWM) pulse signal, and described pwm pulse signal is sent to described CPLD;
Described CPLD is also for after carrying out internal protection logical process at described CPLD; described pwm pulse signal is sent to the insulated gate bipolar transistor IGBT driving isolation circuit be connected with inverter; with the conducting and the shutoff that make described IGBT driving isolation circuit control the IGBT in described inverter according to described pwm pulse signal, to realize the control to described inverter.
Alternatively, described CPLD, comprising: a CPLD and the 2nd CPLD;
Wherein, a described CPLD, is connected with described ADC sampling processing circuit and described DSP respectively, for described digital signal is carried out filtering process, and the digital signal after process is sent to described DSP by data/address bus;
Described 2nd CPLD, be connected with described ADC sampling processing circuit, described DSP and described IGBT driving isolation circuit respectively, for after carrying out internal protection logical process, described pwm pulse signal is sent to described IGBT driving isolation circuit by hardware pins;
Described 2nd CPLD also receives the run signal of described transducer transmission for controlling described ADC sampling processing circuit.
Alternatively, also comprise:
Photoelectric switching circuit, is connected with described 2nd CPLD, for described pwm pulse signal is converted to light signal, sends to described IGBT driving isolation circuit by hardware pins.
Alternatively, also comprise:
Telecommunication circuit, is connected with a described CPLD, for downloading debugging routine, and debugs at least one device in a described CPLD, described 2nd CPLD and described DSP; Described telecommunication circuit comprises: ethernet interface, RS-232 communication interface, RS-485 communication interface or controller local area network's CAN communication interface.
Alternatively, also comprise:
Fault display circuit, is connected, for showing fault message with a described CPLD;
Wherein, a described CPLD, also for carrying out troubleshooting according to the state information of described DSP and described 2nd CPLD feedback and drive described fault display circuit display fault message.
Alternatively, also comprise:
Digital in-output circuit, be connected with described 2nd CPLD, for receiving the high-level control signal of outside input, and described high-level control signal is converted to the low level control signal of described 2nd CPLD needs, or, receive the low level control signal that described 2nd CPLD exports, and described low level control signal is converted to high-level control signal output.
Alternatively, also comprise:
Power circuit, for powering to described DSP and described CPLD.
A kind of control device for inverter that the utility model provides, is gathered the run signal of motor, and described run signal is sent to ADC sampling processing circuit by transducer, described run signal comprises analog voltage signal, analog current signal or simulation tach signal, by ADC sampling processing circuit, described run signal is converted to digital signal, and described digital signal is sent to described CPLD, described digital signal is carried out filtering process by described CPLD, and the digital signal after process is sent to DSP, DSP is processed the digital signal after described process by inverter control algorithm and pulse modulation algorithm, obtains pwm pulse signal, and described pwm pulse signal is sent to described CPLD, then CPLD is after carrying out internal protection logical process, described pwm pulse signal is sent to the IGBT driving isolation circuit be connected with inverter, with the conducting and the shutoff that make described IGBT driving isolation circuit control the IGBT in described inverter according to described pwm pulse signal, thus the control achieved inverter, the partial function of DSP has been shared owing to employing CPLD, DSP only need realize inverter control algorithm and pulse modulation algorithm, compare and existingly realize high performance motor control algolithm by single dsp chip, complicated pulse modulation algorithm, the function such as virtual protection and troubleshooting, take the resource that DSP is less, therefore improve the processing speed of DSP, the requirement of Electric Machine Control high-performance treatments can be met.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of the utility model control device for inverter one embodiment;
Fig. 2 is the system configuration schematic diagram of the utility model control device for inverter one embodiment;
Fig. 3 is the structural representation of another embodiment of the utility model control device for inverter;
Fig. 4 is the schematic flow sheet of the utility model inverter control method one embodiment.
Embodiment
For making the object of the utility model embodiment, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the utility model embodiment, technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.
The control device for inverter that the utility model embodiment relates to, the processing speed being intended to solve DSP in prior art is lower, can not meet the technical problem of the requirement of Electric Machine Control high-performance treatments.
With embodiment particularly, the technical solution of the utility model is described in detail below.These specific embodiments can be combined with each other below, may repeat no more for same or analogous concept or process in some embodiment.
Fig. 1 is the structural representation of the utility model control device for inverter one embodiment.Fig. 2 is the system configuration schematic diagram of the utility model one embodiment.As shown in Figure 1, the control device for inverter of the present embodiment, can comprise:
Transducer, analog to digital converter (Analog-to-DigitalConverter, be called for short ADC) sampling processing circuit, digital signal processor DSP, CPLD (ComplexProgrammableLogicDevice, be called for short CPLD);
Wherein, described transducer, is connected with described ADC sampling processing circuit, for gathering the run signal of motor, and described run signal is sent to described ADC sampling processing circuit; Described run signal comprises at least one in analog voltage signal, analog current signal or simulation tach signal;
Described ADC sampling processing circuit, is connected with described CPLD, is converted to digital signal for the run signal sent by described transducer, described digital signal is sent to described CPLD;
Described CPLD, is connected with described DSP, for described digital signal is carried out filtering process, and the digital signal after process is sent to described DSP;
Described DSP, for being processed the digital signal after described process by inverter control algorithm and pulse modulation algorithm, is obtained pwm pulse signal, and described pwm pulse signal is sent to described CPLD;
Described CPLD is also for after carrying out internal protection logical process at described CPLD; described pwm pulse signal is sent to the insulated gate bipolar transistor (InsulatedGateBipolarTransistor be connected with inverter; be called for short IGBT) driving isolation circuit; with the conducting and the shutoff that make described IGBT driving isolation circuit control the IGBT in described inverter according to described pwm pulse signal, to realize the control to described inverter.
Specifically, in the present embodiment, the course of work of control device for inverter is as follows:
As shown in Figure 1 and Figure 2, ADC sampling processing circuit, the analog signal such as voltage, electric current, the rotating speed when motor collected by transducer runs processes, then analog signal is converted to digital signal, and send to CPLD by data/address bus, CPLD carries out filtering process to the digital signal that ADC sampling processing circuit sends, then sends to DSP by data/address bus, among inverter control algorithm.
What DSP with CPLD communicated employing is the inner self-built dual port random access memory of CPLD (RandomAccessMemory is called for short RAM) communication.DSP receives the voltage when motor after CPLD process runs, electric current, the signals such as rotating speed, processed by the inverter control algorithm of complexity and the pulse modulation algorithm of optimization, obtain pwm pulse signal, CPLD is given again by pwm pulse signal, CPLD receives pwm pulse signal by hardware pins, CPLD carries out internal protection logical process, pwm pulse signal after treatment, output to the IGBT driving isolation circuit be connected with inverter, the conducting of the IGBT in control inverter and shutoff, thus the control realized inverter, thus realize Electric Machine Control, various logic in vehicle controls, the functions such as the failure logging in vehicle.This motor can be phase asynchronous in the present embodiment, and in Fig. 2, M is motor.
Above-mentioned internal protection logical process comprises, input overvoltage, under-voltage protection, output overvoltage, under-voltage protection, overload protection, overcurrent and short-circuit protection etc.
In the present embodiment, because data are directly passed to CPLD by ADC sampling processing circuit, DSP is passed to by data/address bus by CPLD, and by CPLD, final pwm pulse signal is sent to IGBT driving isolation circuit, therefore, compared with existing control device for inverter, less DSP hardware pins is taken.
Also have in existing control device for inverter and adopt FPGA to share the function of DSP, but the cost of FPGA is higher, and CPLD cost in the utility model embodiment is lower.
In the utility model, DSP can adopt the DSP of TI company, and CPLD can adopt the CPLD of altera corp MAXII series.
The control device for inverter that the present embodiment provides, is gathered the run signal of motor, and described run signal is sent to ADC sampling processing circuit by transducer, described run signal comprises analog voltage signal, analog current signal or simulation tach signal, by ADC sampling processing circuit, described run signal is converted to digital signal, and described digital signal is sent to described CPLD, described digital signal is carried out filtering process by described CPLD, and the digital signal after process is sent to DSP, DSP is processed the digital signal after described process by inverter control algorithm and pulse modulation algorithm, obtains pwm pulse signal, and described pwm pulse signal is sent to described CPLD, then CPLD is after carrying out internal protection logical process, described pwm pulse signal is sent to the IGBT driving isolation circuit be connected with inverter, with the conducting and the shutoff that make described IGBT driving isolation circuit control the IGBT in described inverter according to described pwm pulse signal, thus the control achieved inverter, the partial function of DSP has been shared owing to employing CPLD, DSP only need realize inverter control algorithm and pulse modulation algorithm, compare and existingly realize high performance motor control algolithm by single dsp chip, complicated pulse modulation algorithm, the function such as virtual protection and troubleshooting, take the resource that DSP is less, therefore improve the processing speed of DSP, the requirement of Electric Machine Control high-performance treatments can be met.
In another embodiment of the utility model method, on the basis of the execution mode shown in Fig. 1, further, as the enforceable mode of one, described CPLD, comprising: a CPLD and the 2nd CPLD;
Wherein, a described CPLD, is connected with described ADC sampling processing circuit and described DSP respectively, for described digital signal is carried out filtering process, and the digital signal after process is sent to described DSP by data/address bus;
Described 2nd CPLD, be connected with described ADC sampling processing circuit, described DSP and described IGBT driving isolation circuit respectively, for after carrying out internal protection logical process, described pwm pulse signal is sent to described IGBT driving isolation circuit by hardware pins;
Described 2nd CPLD also receives the run signal of described transducer transmission for controlling described ADC sampling processing circuit.
Specifically, a CPLD carries out filtering process to the digital signal that ADC sampling processing circuit sends, then sends to DSP by data/address bus, among inverter control algorithm.
What DSP communicated employing with a CPLD is the inner self-built dual port random access memory of CPLD (RandomAccessMemory is called for short RAM) communication.DSP receives the signal such as voltage, electric current, the rotating speed when motor after a CPLD process runs; processed by the inverter control algorithm of complexity and the pulse modulation algorithm of optimization; obtain pwm pulse signal; pwm pulse signal is given the 2nd CPLD again; 2nd CPLD receives pwm pulse signal by hardware pins; 2nd CPLD carries out internal protection logical process; pwm pulse signal after treatment; output to IGBT driving isolation circuit; the conducting of control IGBT and shutoff, thus the control motor realizing variable voltage variable frequency.
Described 2nd CPLD also receives the run signal of described transducer transmission for controlling described ADC sampling processing circuit.
In above-mentioned embodiment; the digital signal using two CPLD to realize ADC sampling processing circuit sends carries out filtering process; and the digital signal after process is sent to DSP; and internal protection logical process is carried out to the pwm pulse signal that DSP generates; pwm pulse signal after treatment; output to IGBT driving isolation circuit, the problem that the hardware pins of a CPLD is not enough can be avoided, and the speed of two CPLD process and efficiency higher.
Fig. 3 is the structural representation of another embodiment of the utility model DC-to-AC converter.As shown in Figure 3, on the basis of the execution mode shown in Fig. 1, the device of the present embodiment, also comprises:
Photoelectric switching circuit, is connected with described 2nd CPLD, for described pwm pulse signal is converted to light signal, sends to described IGBT driving isolation circuit by hardware pins.
Specifically, photoelectric switching circuit, by the pwm pulse signal that the 2nd CPLD exports, now pwm pulse signal is the signal of telecommunication, converts the electrical signal to light signal, by Fiber connection IGBT driving isolation circuit, thus realizes driving IGBT conducting and shutoff.Antijamming capability and the transmittability of use optical fiber transmission signal are stronger.
Alternatively, as the enforceable mode of one, the device of the present embodiment, also comprises:
Telecommunication circuit, is connected with a described CPLD, for downloading debugging routine, and debugs at least one device in a described CPLD, described 2nd CPLD and described DSP; Described telecommunication circuit comprises: ethernet interface, RS-232 communication interface, RS-485 communication interface or controller local area network's (ControllerAreaNetwork is called for short CAN) communication interface.
Specifically, telecommunication circuit, for downloading debugging routine, realizes the function of debugging a described CPLD, described 2nd CPLD, described DSP; One CPLD also needs the process carrying out the communication protocol such as Ethernet, RS-232, RS-485, CAN, makes it possible to communicate with described telecommunication circuit.
This telecommunication circuit, comprises ethernet interface, RS-232 communication interface, RS-485 communication interface or CAN communication interface.
Alternatively, as the enforceable mode of one, the device of the present embodiment, also comprises:
Fault display circuit, is connected, for showing fault message with a described CPLD;
Wherein, a described CPLD, also for carrying out troubleshooting according to the state information of described DSP and described 2nd CPLD feedback and drive described fault display circuit display fault message.
Specifically, a CPLD can feed back the state information of coming according to DSP and the 2nd CPLD and carries out troubleshooting and driving malfunction display circuit (as LED circuit) shows fault message.
Alternatively, as the enforceable mode of one, the device of the present embodiment, also comprises:
Digital in-output circuit, be connected with described 2nd CPLD, for receiving the high-level control signal of outside input, and described high-level control signal is converted to the low level control signal of described 2nd CPLD needs, or, receive the low level control signal that described 2nd CPLD exports, and described low level control signal is converted to high-level control signal output.
Specifically, digital in-output circuit, converts 110V or the 24V signal of input to 5V, then is converted to the 3.3V of the 2nd CPLD needs by level transferring chip.Then according to wagon control logic need carry out choice for use, thus complete pre-provisioning request, i.e. the 2nd CPLD, also carries out vehicle logic control and output for the external digital input variable according to digital in-output circuit.Equally, the 5V signal 3.3V that CPLD exports being converted to control figure imput output circuit is needed.
Alternatively, as the enforceable mode of one, the device of the present embodiment, also comprises:
Power circuit, for powering to described DSP and described CPLD.
Specifically, power circuit, comprises DSP power circuit, CPLD power circuit, and DSP needs 3.3V and 1.8V two kinds of voltages; CPLD needs three kinds of supply power voltages: 1.2V core voltage, 3.3V input and output I/O interface voltage, 2.5V specific function voltage.
In above-mentioned embodiment, convert the electrical signal to light signal by photoelectric switching circuit, antijamming capability and the transmittability of use optical fiber transmission signal are stronger; Fault display circuit can show fault message intuitively.
Fig. 4 is the schematic flow sheet of the utility model inverter control method one embodiment.The method of the present embodiment can be applied in the control device for inverter as described in Fig. 1-Fig. 3 any embodiment.As shown in Figure 4, the method for the present embodiment comprises:
Step 401, described transducer gather the run signal of motor, and described run signal are sent to described ADC sampling processing circuit; Described run signal comprises at least one in analog voltage signal, analog current signal or simulation tach signal;
The run signal that described transducer sends is converted to digital signal by step 402, described ADC sampling processing circuit, and described digital signal is sent to described CPLD;
Described digital signal is carried out filtering process by step 403, described CPLD, and the digital signal after process is sent to described DSP;
Step 404, described DSP are processed the digital signal after described process by inverter control algorithm and pulse modulation algorithm, obtain pwm pulse signal, and described pwm pulse signal is sent to described CPLD;
Step 405, described CPLD are after carrying out internal protection logical process; described pwm pulse signal is sent to the insulated gate bipolar transistor IGBT driving isolation circuit be connected with inverter; with the conducting and the shutoff that make described IGBT driving isolation circuit control the IGBT in described inverter according to described pwm pulse signal, to realize the control to described inverter.
Specifically, as shown in Figure 1, Figure 2 and Figure 4, ADC sampling processing circuit, the analog signal such as voltage, electric current, the rotating speed when motor collected by transducer runs processes, then analog signal is converted to digital signal, and sends to CPLD by data/address bus, CPLD carries out filtering process to the digital signal that ADC sampling processing circuit sends, DSP is sent to again, among inverter control algorithm by data/address bus.
What DSP with CPLD communicated employing is the inner self-built dual port random access memory of CPLD (RandomAccessMemory is called for short RAM) communication.DSP receives the voltage when motor after CPLD process runs, electric current, the signals such as rotating speed, processed by the inverter control algorithm of complexity and the pulse modulation algorithm of optimization, obtain pwm pulse signal, CPLD is given again by pwm pulse signal, CPLD receives pwm pulse signal by hardware pins, CPLD carries out internal protection logical process, pwm pulse signal after treatment, output to the IGBT driving isolation circuit be connected with inverter, the conducting of the IGBT in control inverter and shutoff, thus the control realized inverter, thus realize Electric Machine Control, various logic in vehicle controls, the functions such as the failure logging in vehicle.This motor can be phase asynchronous in the present embodiment, and in Fig. 2, M is motor.
Above-mentioned internal protection logical process comprises, input overvoltage, under-voltage protection, output overvoltage, under-voltage protection, overload protection, overcurrent and short-circuit protection etc.
In the present embodiment, because data are directly passed to CPLD by ADC sampling processing circuit, DSP is passed to by data/address bus by CPLD, and by CPLD, final pwm pulse signal is sent to IGBT driving isolation circuit, therefore, compared with existing inverter control method, less DSP hardware pins is taken.
Also have in existing inverter control method and adopt FPGA to share the function of DSP, but the cost of FPGA is higher, and CPLD cost in the utility model embodiment is lower.
In the utility model, DSP can adopt the DSP of TI company, and CPLD can adopt the CPLD of altera corp MAXII series.
The inverter control method that the present embodiment provides, is gathered the run signal of motor, and described run signal is sent to ADC sampling processing circuit by transducer, described run signal comprises analog voltage signal, analog current signal or simulation tach signal, by ADC sampling processing circuit, described run signal is converted to digital signal, and described digital signal is sent to described CPLD, described digital signal is carried out filtering process by described CPLD, and the digital signal after process is sent to DSP, DSP is processed the digital signal after described process by inverter control algorithm and pulse modulation algorithm, obtains pwm pulse signal, and described pwm pulse signal is sent to described CPLD, then CPLD is after carrying out internal protection logical process, described pwm pulse signal is sent to the IGBT driving isolation circuit be connected with inverter, with the conducting and the shutoff that make described IGBT driving isolation circuit control the IGBT in described inverter according to described pwm pulse signal, thus the control achieved inverter, the partial function of DSP has been shared owing to employing CPLD, DSP only need realize inverter control algorithm and pulse modulation algorithm, compare and existingly realize high performance motor control algolithm by single dsp chip, complicated pulse modulation algorithm, the function such as virtual protection and troubleshooting, take the resource that DSP is less, therefore improve the processing speed of DSP, the requirement of Electric Machine Control high-performance treatments can be met.
Alternatively, the control method of the present embodiment can be applied in control device for inverter, and described device comprises: transducer, the analog to digital converter ADC sampling processing circuit, digital signal processor DSP, a CPLD and the 2nd CPLD that are connected with described transducer; A described CPLD is connected with described DSP and described ADC sampling processing circuit; Described 2nd CPLD is connected with described DSP and described ADC sampling processing circuit; Described digital signal is carried out filtering process by described CPLD, and the digital signal after process is sent to described DSP, comprising:
Described digital signal is carried out filtering process by a described CPLD, and the digital signal after process is sent to described DSP by data/address bus;
Described pwm pulse signal, after carrying out internal protection logical process, is sent to the insulated gate bipolar transistor IGBT driving isolation circuit be connected with inverter, comprises by described CPLD:
Described pwm pulse signal, after carrying out internal protection logical process, is sent to described IGBT driving isolation circuit by hardware pins by described 2nd CPLD.
Alternatively, described method, also comprises:
Described 2nd CPLD controls the run signal that described ADC sampling processing circuit receives the transmission of described transducer.
Alternatively, the control method of the present embodiment can be applied in control device for inverter, and described device comprises: transducer, the analog to digital converter ADC sampling processing circuit, digital signal processor DSP, a CPLD, the 2nd CPLD and the photoelectric switching circuit that are connected with described transducer; A described CPLD is connected with described DSP and described ADC sampling processing circuit; Described 2nd CPLD is connected with described DSP and described photoelectric switching circuit;
Described described pwm pulse signal is sent to described IGBT driving isolation circuit by hardware pins, comprise: the pwm pulse signal that described 2nd CPLD sends is converted to light signal by described photoelectric switching circuit, sends to described IGBT driving isolation circuit by hardware pins.
Alternatively, the control method of the present embodiment can be applied in control device for inverter, and described device comprises: transducer, the analog to digital converter ADC sampling processing circuit, digital signal processor DSP, a CPLD, the 2nd CPLD and the telecommunication circuit that are connected with described transducer; A described CPLD is connected with described DSP, described ADC sampling processing circuit and described telecommunication circuit respectively; Described 2nd CPLD is connected with described DSP and described photoelectric switching circuit; Described telecommunication circuit comprises: ethernet interface, RS-232 communication interface, RS-485 communication interface or controller local area network's CAN communication interface;
Described method, also comprises:
Described telecommunication circuit downloads debugging routine, and debugs at least one device in a described CPLD, described 2nd CPLD and described DSP.
Alternatively, the control method of the present embodiment can be applied in control device for inverter, and described device comprises: transducer, the analog to digital converter ADC sampling processing circuit, digital signal processor DSP, a CPLD, the 2nd CPLD and the fault display circuit that are connected with described transducer; A described CPLD is connected with described DSP, described ADC sampling processing circuit and described fault display circuit respectively; Described 2nd CPLD is connected with described DSP;
Described method, also comprises:
Described fault display circuit display fault message.
Alternatively, described method, also comprises:
A described CPLD carries out troubleshooting according to the state information of described DSP and described 2nd CPLD feedback and drives described fault display circuit display fault message.
Alternatively, the control method of the present embodiment can be applied in control device for inverter, and described device comprises: transducer, the analog to digital converter ADC sampling processing circuit, digital signal processor DSP, a CPLD, the 2nd CPLD and the digital in-output circuit that are connected with described transducer; A described CPLD is connected with described DSP and described ADC sampling processing circuit; Described 2nd CPLD is connected with described DSP and described digital in-output circuit;
Described method, also comprises:
Described digital in-output circuit receives the high-level control signal of outside input, and described high-level control signal is converted to the low level control signal of described 2nd CPLD needs; Or,
Described digital in-output circuit receives the low level control signal that described 2nd CPLD exports, and described low level control signal is converted to high-level control signal output.
In above-mentioned embodiment, can be applied in control device for inverter as shown in Figure 3, specific implementation process, see device embodiment, repeats no more herein.
Last it is noted that above each embodiment is only in order to illustrate the technical solution of the utility model, be not intended to limit; Although be described in detail the utility model with reference to foregoing embodiments, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of each embodiment technical scheme of the utility model.
Claims (7)
1. a control device for inverter, is characterized in that, comprising:
Transducer, analog to digital converter ADC sampling processing circuit, digital signal processor DSP, complex programmable logic device (CPLD);
Wherein, described transducer, is connected with described ADC sampling processing circuit, for gathering the run signal of motor, and described run signal is sent to described ADC sampling processing circuit; Described run signal comprises at least one in analog voltage signal, analog current signal or simulation tach signal;
Described ADC sampling processing circuit, is connected with described CPLD, is converted to digital signal for the run signal sent by described transducer, described digital signal is sent to described CPLD;
Described CPLD, is connected with described DSP, for described digital signal is carried out filtering process, and the digital signal after process is sent to described DSP;
Described DSP, for being processed the digital signal after described process by inverter control algorithm and pulse modulation algorithm, is obtained pulse width modulation (PWM) pulse signal, and described pwm pulse signal is sent to described CPLD;
Described CPLD is also for after carrying out internal protection logical process at described CPLD; described pwm pulse signal is sent to the insulated gate bipolar transistor IGBT driving isolation circuit be connected with inverter; with the conducting and the shutoff that make described IGBT driving isolation circuit control the IGBT in described inverter according to described pwm pulse signal, to realize the control to described inverter.
2. device according to claim 1, is characterized in that, described CPLD, comprising: a CPLD and the 2nd CPLD;
Wherein, a described CPLD, is connected with described ADC sampling processing circuit and described DSP respectively, for described digital signal is carried out filtering process, and the digital signal after process is sent to described DSP by data/address bus;
Described 2nd CPLD, be connected with described ADC sampling processing circuit, described DSP and described IGBT driving isolation circuit respectively, for after carrying out internal protection logical process, described pwm pulse signal is sent to described IGBT driving isolation circuit by hardware pins;
Described 2nd CPLD also receives the run signal of described transducer transmission for controlling described ADC sampling processing circuit.
3. device according to claim 2, is characterized in that, also comprises:
Photoelectric switching circuit, is connected with described 2nd CPLD, for described pwm pulse signal is converted to light signal, sends to described IGBT driving isolation circuit by hardware pins.
4. device according to claim 2, is characterized in that, also comprises:
Telecommunication circuit, is connected with a described CPLD, for downloading debugging routine, and debugs at least one device in a described CPLD, described 2nd CPLD and described DSP; Described telecommunication circuit comprises: ethernet interface, RS-232 communication interface, RS-485 communication interface or controller local area network's CAN communication interface.
5. device according to claim 2, is characterized in that, also comprises:
Fault display circuit, is connected, for showing fault message with a described CPLD;
Wherein, a described CPLD, also for carrying out troubleshooting according to the state information of described DSP and described 2nd CPLD feedback and drive described fault display circuit display fault message.
6. device according to claim 2, is characterized in that, also comprises:
Digital in-output circuit, be connected with described 2nd CPLD, for receiving the high-level control signal of outside input, and described high-level control signal is converted to the low level control signal of described 2nd CPLD needs, or, receive the low level control signal that described 2nd CPLD exports, and described low level control signal is converted to high-level control signal output.
7. the device according to any one of claim 1-6, is characterized in that, also comprises:
Power circuit, for powering to described DSP and described CPLD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520664359.9U CN205004963U (en) | 2015-08-28 | 2015-08-28 | Controlling device of inverter |
Applications Claiming Priority (1)
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| CN201520664359.9U CN205004963U (en) | 2015-08-28 | 2015-08-28 | Controlling device of inverter |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108539711A (en) * | 2018-04-10 | 2018-09-14 | 北京动力源科技股份有限公司 | A kind of wave limiting guard method, device and electric machine controller |
| CN110176873A (en) * | 2019-05-27 | 2019-08-27 | 中国工程物理研究院电子工程研究所 | A kind of micro motor real-time control method and system |
| CN113253110A (en) * | 2021-05-12 | 2021-08-13 | 中国第一汽车股份有限公司 | Motor monitoring method and device, electronic equipment and storage medium |
-
2015
- 2015-08-28 CN CN201520664359.9U patent/CN205004963U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108539711A (en) * | 2018-04-10 | 2018-09-14 | 北京动力源科技股份有限公司 | A kind of wave limiting guard method, device and electric machine controller |
| CN110176873A (en) * | 2019-05-27 | 2019-08-27 | 中国工程物理研究院电子工程研究所 | A kind of micro motor real-time control method and system |
| CN110176873B (en) * | 2019-05-27 | 2020-06-05 | 中国工程物理研究院电子工程研究所 | Micro motor real-time control method and system |
| CN113253110A (en) * | 2021-05-12 | 2021-08-13 | 中国第一汽车股份有限公司 | Motor monitoring method and device, electronic equipment and storage medium |
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Address after: 116052 Liaoning province Dalian City Lushun Economic Development Zone Dalian Hao Yang No. 1 North Street Patentee after: CRRC DALIAN ELECTRIC TRACTION R & D CENTER CO., LTD. Address before: 116052 Liaoning province Dalian City Lushun Economic Development Zone Dalian Hao Yang No. 1 North Street Patentee before: Co., Ltd of Bei Che Dalian Electric Traction R & D Center |