CN204993410U - Serial ports and ethernet conversion equipment based on MQTT thing networking protocol - Google Patents
Serial ports and ethernet conversion equipment based on MQTT thing networking protocol Download PDFInfo
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- CN204993410U CN204993410U CN201520609823.4U CN201520609823U CN204993410U CN 204993410 U CN204993410 U CN 204993410U CN 201520609823 U CN201520609823 U CN 201520609823U CN 204993410 U CN204993410 U CN 204993410U
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Abstract
The utility model relates to a serial ports and ethernet conversion equipment based on MQTT thing networking protocol. The utility model discloses a voltage conversion circuit, single -chip control circuit, SWD debugging interface circuit, W5500 hardware protocol stack circuit, network transformer and RJ45 interface circuit and RS232 serial communication circuit. The utility model discloses the transplanting has a MQTT thing networking protocol, and MQTT server on joinable to the ethernet carries out remote point -to -point reliable communication, the utility model discloses still support the transparent transmission of data under TCP_Server, TCP_Client, UDP and the UDP_Server mode, the utility model has the advantages of small, with low costs and low power dissipation.
Description
Technical field
The invention belongs to communication technical field, relate to a kind of serial ports based on MQTT Internet of Things agreement and Ethernet conversion equipment, be mainly used in RS232 interface equipment connecting Internets such as the flush bonding processor in internet-of-things terminal, transducer, programmable logic controller (PLC), data storages.
Background technology
Technology of Internet of things, as the 21 century emerging communication technology, obtains fast development in recent years in the world.The IT such as IBM, Microsoft industry giant is also proposed oneself technology of Internet of things achievement one after another.Along with the arrival in Internet of Things epoch, country of China and government have been fully recognized that the importance of technology of Internet of things revolution.China's Internet industry development in recent years rapidly, has possessed necessary basis in the Internet of Things industry development in future.But the Internet of Things current situation of China is also in an initiation state, shortage core technology and independent intellectual property right are one of key factors of restriction China Internet of Things development.
In prior art, serial ports and Ethernet conversion equipment research direction mainly concentrate in miniaturization, low-power consumption, low cost.But along with the continuous expansion band of Internet of things system networking scope, the long-distance transmissions of data, the simple and easy access of equipment are more and more subject to people's attention with the high efficiency communicated.
Propose one in Chinese patent CN102387054A and turn Ethernet control device based on STM32 serial ports, this device have employed software Ethernet protocol stack, although this kind of Software Protocol Stack can reduce installation cost, but greatly reduce the stability of communication, and adopt STM32 serial ports to turn this covering device back-level server pattern of Ethernet, do not support client mode, device login remote server cannot carry out transfer of data.This covering device cannot support udp protocol and integrated MQTT Internet of Things agreement, cannot realize towards disconnected high speed data transfer and remote point-to-point reliable communication on a large scale, and present society does not find the serial ports and the Ethernet conversion equipment that can solve the problems referred to above temporarily.
Summary of the invention
For above-mentioned deficiency, the invention provides a kind of serial ports based on MQTT Internet of Things agreement and Ethernet conversion equipment.
The present invention includes voltage conversion circuit, single chip machine controlling circuit, SWD debug i/f circuit, W5500 hardware protocol stack circuit, network transformer and RJ45 interface circuit and RS232 serial communication circuit.
Described voltage conversion circuit comprises a double-legged straight cutting binding post, a PPTC resettable fuse, a current-limiting resistance, a light-emitting diode, an anti-reverse diode, a voltage stabilizing didoe, a power supply voltage stabilizing chip, two electrochemical capacitors, two ceramic disc capacitors.1 pin of both feet straight cutting binding post is connected with 1 pin of PPTC resettable fuse; 1 pin of current-limiting resistance is connected with 2 pin of PPTC resettable fuse, the positive pole of anti-reverse diode, the positive pole of light-emitting diode; The negative pole of 3 pin of power supply voltage stabilizing chip and the negative pole of anti-reverse diode, voltage stabilizing didoe, the positive pole of the first electrochemical capacitor, 1 pin of the first ceramic disc capacitor are connected; 2 pin of power supply voltage stabilizing chip are connected with 1 pin of the positive pole of the second electrochemical capacitor, the second ceramic disc capacitor, export as voltage; Both feet straight cutting binding post 2 pin, light-emitting diode negative pole, voltage stabilizing didoe positive pole, the negative pole of the first electrochemical capacitor, 2 pin of the first ceramic disc capacitor, power supply voltage stabilizing chip 1 pin, the negative pole of the second electrochemical capacitor, 2 pin of the second ceramic disc capacitor are all connected with GND.
Described single chip machine controlling circuit comprises STM32 processor, four Chip-Rs, three ceramic disc capacitors, passive crystal oscillators.20 pin of STM32 processor are connected with 1 pin of the first Chip-R, and 2 pin of the first Chip-R are connected with GND; 44 pin of STM32 processor are connected with 1 pin of the second Chip-R, and 2 pin of the second Chip-R are connected with GND; 1 pin of 5 pin of STM32 processor, 1 pin of the 3rd Chip-R, passive crystal oscillator, 1 pin of the first ceramic disc capacitor connect, 2 pin of 6 pin of STM32 processor, 2 pin of the 3rd Chip-R, passive crystal oscillator, 1 pin of the second ceramic disc capacitor connect, and 2 pin of the first ceramic disc capacitor, 2 pin of the second ceramic disc capacitor are connected with GND; 1 pin of the 4th Chip-R is connected with VCC, and 1 pin of 2 pin of the 4th Chip-R, 7 pin of STM32 processor, the 3rd ceramic disc capacitor connects, and 2 pin of the 3rd ceramic disc capacitor are connected with GND; 9 pin of STM32 processor, 24 pin, 36 pin, 48 pin are connected with VCC; 8 pin of STM32 processor, 23 pin, 35 pin, 47 pin are connected with GND.
Described SWD interface debugging circuit comprises four pin straight cutting binding posts and two Chip-Rs.1 pin of four pin straight cutting binding posts, 1 pin of the first Chip-R, 1 pin of the second Chip-R are connected with VCC; 2 pin, 2 pin of the second Chip-R of four pin straight cutting binding posts are connected with 34 pin of STM32 processor; 3 pin, 2 pin of the first Chip-R of four pin straight cutting binding posts are connected with 37 pin of STM32 processor; 4 pin of four pin straight cutting binding posts are connected with GND.
Described W5500 hardware protocol stack circuit comprises W5500 hardware protocol chip stack, passive crystal oscillator, 18 Chip-Rs and seven ceramic disc capacitors.1 pin of W5500 hardware protocol chip stack is connected with 2 pin of the first Chip-R; 2 pin of W5500 hardware protocol chip stack are connected with 2 pin of the second Chip-R; 1 pin of 1 pin of the first ceramic disc capacitor, 1 pin of the first Chip-R, the second Chip-R, 1 pin of the 3rd Chip-R are connected with VCC; 2 pin of the 3rd Chip-R are connected with 1 pin of the second ceramic disc capacitor; 2 pin of the first ceramic disc capacitor, 2 pin of the second ceramic disc capacitor are connected with GND; 2 pin of 2 pin of the 3rd ceramic disc capacitor, 5 pin of W5500 hardware protocol chip stack, the 4th Chip-R connect; 2 pin of 2 pin of the 5th Chip-R, 6 pin of W5500 hardware protocol chip stack, the 5th ceramic disc capacitor connect; 2 pin of 1 pin of the 4th Chip-R, 1 pin of the 5th Chip-R, the 4th ceramic disc capacitor connect; 1 pin of the 4th ceramic disc capacitor is connected with GND; 1 pin of 30 pin of W5500 hardware protocol chip stack, 1 pin of the 6th Chip-R, the first passive crystal oscillator, 2 pin of the 6th ceramic disc capacitor connect; 2 pin of 31 pin of W5500 hardware protocol chip stack, 2 pin of the 6th Chip-R, the first passive crystal oscillator, 2 pin of the 7th ceramic disc capacitor connect; 1 pin of the 6th ceramic disc capacitor, 1 pin of the 7th ceramic disc capacitor are connected with GND; 10 pin of W5500 hardware protocol chip stack are connected with 2 pin of the 7th Chip-R; 1 pin of the 7th Chip-R is connected with GND; 1 pin of the 8th Chip-R, 1 pin of the 9th Chip-R are connected with VCC; 14 pin of 32 pin of W5500 hardware protocol chip stack, 2 pin of the 8th Chip-R, STM32 processor connect; 19 pin of 36 pin of W5500 hardware protocol chip stack, 2 pin of the 9th Chip-R, STM32 processor connect; 35 pin of W5500 hardware protocol chip stack, 17 pin of STM32 processor connect; 34 pin of W5500 hardware protocol chip stack, 16 pin of STM32 processor connect; 33 pin of W5500 hardware protocol chip stack, 15 pin of STM32 processor connect; 1 pin of 37 pin of W5500 hardware protocol chip stack, 18 pin of STM32 processor, the tenth Chip-R connects; 2 pin of the tenth Chip-R are connected with VCC; 45 pin of W5500 hardware protocol chip stack, 1 pin of the 11 Chip-R connect; 44 pin of W5500 hardware protocol chip stack, 1 pin of the 12 Chip-R connect; 43 pin of W5500 hardware protocol chip stack, 1 pin of the 13 Chip-R connect; 42 pin of W5500 hardware protocol chip stack, 1 pin of the 14 Chip-R connect; 41 pin of W5500 hardware protocol chip stack, 1 pin of the 15 Chip-R connect; 40 pin of W5500 hardware protocol chip stack, 1 pin of the 16 Chip-R connect; 39 pin of W5500 hardware protocol chip stack, 1 pin of the 17 Chip-R connect; 38 pin of W5500 hardware protocol chip stack, 1 pin of the 18 Chip-R connect; 2 pin of the 11 Chip-R, 2 pin of the 12 Chip-R, 2 pin of the 13 Chip-R, 2 pin of the 14 Chip-R, 2 pin of the 15 Chip-R, 2 pin of the 16 Chip-R, 2 pin of the 17 Chip-R, 2 pin of the 18 Chip-R are connected with GND; 28 pin of W5500 hardware protocol chip stack, 21 pin, 17 pin are connected with VCC; 16 pin of W5500 hardware protocol chip stack, 14 pin, 9 pin are connected with GND.
Described network transformer and RJ45 interface circuit comprise network transformer and RJ45 interface chip and two Chip-Rs.1 pin of network transformer and RJ45 interface chip, 2 pin of W5500 hardware protocol chip stack, 2 pin of the second Chip-R are connected; 2 pin of network transformer and RJ45 interface chip, 1 pin of W5500 hardware protocol chip stack, 2 pin of the first Chip-R are connected; Network transformer is connected with 1 pin of the 5th ceramic disc capacitor with 3 pin of RJ45 interface chip; 4 pin of network transformer and RJ45 interface chip, 2 pin of the 3rd Chip-R, 1 pin of the second ceramic disc capacitor are connected; 5 pin of network transformer and RJ45 interface chip, 1 pin of the 4th Chip-R, 1 pin of the 5th Chip-R, 2 pin of the 4th ceramic disc capacitor are connected; Network transformer is connected with 1 pin of the 3rd ceramic disc capacitor with 6 pin of RJ45 interface chip; Network transformer is connected with 1 pin of the first Chip-R with 12 pin of RJ45 interface chip; Network transformer is connected with 1 pin of the second Chip-R with 9 pin of RJ45 interface chip; 2 pin of the first Chip-R, 2 pin of the second Chip-R are connected with GND; Network transformer is connected with 27 pin of W5500 hardware protocol chip stack with 10 pin of RJ45 interface chip; Network transformer is connected with 25 pin of W5500 hardware protocol chip stack with 11 pin of RJ45 interface chip; 13 pin, 14 pin of network transformer and RJ45 interface chip are connected with GND.
Described RS232 serial communication circuit comprises RS232 transponder chip, RS232 serial communication interface and five ceramic disc capacitors.1 pin of RS232 transponder chip is connected with 1 pin of the first ceramic disc capacitor; 3 pin of RS232 transponder chip are connected with 2 pin of the first ceramic disc capacitor; 4 pin of RS232 transponder chip are connected with 1 pin of the second ceramic disc capacitor; 5 pin of RS232 transponder chip are connected with 2 pin of the second ceramic disc capacitor; 11 pin of RS232 transponder chip are connected with 30 pin of STM32 processor; 12 pin of RS232 transponder chip are connected with 31 pin of STM32 processor; 16 pin of RS232 transponder chip are connected with 1 pin of the 3rd ceramic disc capacitor; 2 pin of RS232 transponder chip are connected with 1 pin of the 4th ceramic disc capacitor; 6 pin of RS232 transponder chip are connected with 1 pin of the 5th ceramic disc capacitor; 2 pin of 2 pin of the 3rd ceramic disc capacitor, 15 pin of RS232 transponder chip, the 4th ceramic disc capacitor, 2 pin of the 5th ceramic disc capacitor are connected with GND; 14 pin of RS232 transponder chip are connected with 1 pin of RS232 serial communication interface; 13 pin of RS232 transponder chip are connected with 2 pin of RS232 serial communication interface.
The STM32F103C8T6 model that power supply voltage stabilizing chip in the present invention adopts the low pressure difference linearity LDO chip TPS736 model of Texas Instrument, STM32 processor adopts ST company, W5500 hardware protocol chip stack adopt the W5500 model of WIZNET company, network transformer and RJ45 interface chip adopts the B-TRJ4037FBNL model of Beijing Bo Kong Automation Co., Ltd, RS232 transponder chip adopts Maxim MAX3232 model.
The present invention transplants MQTT Internet of Things agreement.When device is set to MQTT pattern, can be connected with the MQTT server on Ethernet, carries out the news release based on " theme " and reception, between device, point-to-point reliable data transmission can be carried out by the MQTT server on Ethernet.Data transmission quality is divided three classes and can sets, and the first kind is " at the most once ", and news release relies on bottom TCP/IP network completely, and information drop-out or repetition can occur; Equations of The Second Kind is " at least one times ", guarantees that message arrives, but message repeats to occur; 3rd class is " for once ", guarantees that message arrives once.
The present invention can be set to data transparent transmission pattern.Under this pattern, device has TCP_Server, TCP_Client, UDP and UDP_Server tetra-kinds of working methods.TCP network packet or UDP message can wrap between the server on the RS232 interface of single-chip microcomputer and Ethernet and carry out data transparent transmission by device.The mode of operation of device, device IP address, target ip address, device port, target port, device MAC Address, device serial port baud rate can be arranged by software.After optimum configurations, automatically preserve, after power down, device data are not lost.The built-in heartbeat packet mechanism of device, ensures that connection is true and reliable, avoids connection seemingly-dead.
Accompanying drawing explanation
Fig. 1 is structure principle chart of the present invention;
Fig. 2 is voltage conversion circuit figure in Fig. 1;
Fig. 3 is single chip machine controlling circuit figure in Fig. 1;
Fig. 4 is SWD debug i/f circuit figure in Fig. 1;
Fig. 5 is W5500 hardware protocol stacks circuit diagram in Fig. 1;
Fig. 6 is network transformer and RJ45 interface circuit figure in Fig. 1;
Fig. 7 is RS232 serial communication circuit figure in Fig. 1;
Fig. 8 is software flow pattern of the present invention.
Embodiment
As shown in figs. 1 and 3, voltage conversion circuit 1, single chip machine controlling circuit 2, SWD debug i/f circuit 3, W5500 hardware protocol stack circuit 4, network transformer and RJ45 interface circuit 5, RS232 serial communication circuit 6 is comprised based on the serial ports of MQTT Internet of Things agreement and Ethernet conversion equipment.
As shown in Figure 2, voltage conversion circuit comprises a double-legged straight cutting binding post J1, PPTC resettable fuse F1, current-limiting resistance R1, a light-emitting diode D2, anti-reverse diode D1, a voltage stabilizing didoe D3, a power supply voltage stabilizing chip IC 1, two electrochemical capacitors, two ceramic disc capacitors.1 pin of both feet straight cutting binding post J1 is connected with 1 pin of PPTC resettable fuse F1; 1 pin of current-limiting resistance R1 is connected with 2 pin of PPTC resettable fuse F1, the positive pole of anti-reverse diode D1, the positive pole of light-emitting diode D2; The negative pole of 3 pin of power supply voltage stabilizing chip IC 1 and the negative pole of anti-reverse diode D1, voltage stabilizing didoe D3, the positive pole of the first electrochemical capacitor C3,1 pin of the first ceramic disc capacitor C1 are connected; 2 pin of power supply voltage stabilizing chip IC 1 are connected with 1 pin of the positive pole of the second electrochemical capacitor C4, the second ceramic disc capacitor C2, export as voltage VCC; 2 pin of both feet straight cutting binding post J1, the negative pole of light-emitting diode D2, the positive pole of voltage stabilizing didoe D3, the negative pole of the first electrochemical capacitor C3,2 pin of the first ceramic disc capacitor C1,1 pin of power supply voltage stabilizing chip IC 1, the negative pole of the second electrochemical capacitor C4,2 pin of the second ceramic disc capacitor C2 are all connected with GND.
As shown in Figure 3, single chip machine controlling circuit comprises STM32 processor IC2, four Chip-Rs, three ceramic disc capacitors, passive crystal oscillator Y1.20 pin of STM32 processor IC2 are connected with 1 pin of the first Chip-R R2, and 2 pin of the first Chip-R R2 are connected with GND; 44 pin of STM32 processor IC2 are connected with 1 pin of the second Chip-R R3, and 2 pin of the second Chip-R R3 are connected with GND; 1 pin of 5 pin of STM32 processor IC2,1 pin of the 3rd Chip-R R4, passive crystal oscillator Y1,1 pin of the first ceramic disc capacitor C5 connect, 2 pin of 6 pin of STM32 processor IC2,2 pin of the 3rd Chip-R R4, passive crystal oscillator Y1,1 pin of the second ceramic disc capacitor C6 connect, and 2 pin of the first ceramic disc capacitor C5,2 pin of the second ceramic disc capacitor C6 are connected with GND; 1 pin of the 4th Chip-R R5 is connected with VCC, and 1 pin of 2 pin of the 4th Chip-R R5,7 pin of STM32 processor IC2, the 3rd ceramic disc capacitor C7 connects, and 2 pin of the 3rd ceramic disc capacitor C7 are connected with GND; 9 pin of STM32 processor IC2,24 pin, 36 pin, 48 pin are connected with VCC; 8 pin of STM32 processor IC2,23 pin, 35 pin, 47 pin are connected with GND.
As shown in Figure 4, SWD interface debugging circuit comprises four pin straight cutting binding post J2 and two Chip-R.1 pin of four pin straight cutting binding post J2,1 pin of the first Chip-R R6,1 pin of the second Chip-R R7 are connected with VCC; 2 pin of four pin straight cutting binding post J2,2 pin of the second Chip-R R7 are connected with 34 pin of STM32 processor IC2; 3 pin of four pin straight cutting binding post J2,2 pin of the first Chip-R R6 are connected with 37 pin of STM32 processor IC2; 4 pin of four pin straight cutting binding post J2 are connected with GND.
As shown in Figure 5, W5500 hardware protocol stack circuit comprises W5500 hardware protocol stacks chip IC 3, passive crystal oscillator Y2,18 Chip-Rs and seven ceramic disc capacitors.1 pin of W5500 hardware protocol stacks chip IC 3 is connected with 2 pin of the first Chip-R R10; 2 pin of W5500 hardware protocol stacks chip IC 3 are connected with 2 pin of the second Chip-R R11; 1 pin of the first ceramic disc capacitor C8,1 pin of the first Chip-R R10,1 pin of the second Chip-R R11,1 pin of the 3rd Chip-R R12 are connected with VCC; 2 pin of the 3rd Chip-R R12 are connected with 1 pin of the second ceramic disc capacitor C9; 2 pin of the first ceramic disc capacitor C8,2 pin of the second ceramic disc capacitor C9 are connected with GND; 2 pin of 2 pin of the 3rd ceramic disc capacitor C10,5 pin of W5500 hardware protocol stacks chip IC 3, the 4th Chip-R R14 connect; 2 pin of 2 pin of the 5th Chip-R R15,6 pin of W5500 hardware protocol stacks chip IC 3, the 5th ceramic disc capacitor C12 connect; 2 pin of 1 pin of the 4th Chip-R R13,1 pin of the 5th Chip-R R15, the 4th ceramic disc capacitor C11 connect; 1 pin of the 4th ceramic disc capacitor C11 is connected with GND; 1 pin of 30 pin of W5500 hardware protocol stacks chip IC 3,1 pin of the 6th Chip-R R24, the first passive crystal oscillator Y2,2 pin of the 6th ceramic disc capacitor C13 connect; 2 pin of 31 pin of W5500 hardware protocol stacks chip IC 3,2 pin of the 6th Chip-R R24, the first passive crystal oscillator Y2,2 pin of the 7th ceramic disc capacitor C14 connect; 1 pin of the 6th ceramic disc capacitor C13,1 pin of the 7th ceramic disc capacitor C14 are connected with GND; 10 pin of W5500 hardware protocol stacks chip IC 3 are connected with 2 pin of the 7th Chip-R R25; 1 pin of the 7th Chip-R R25 is connected with GND; 1 pin of the 8th Chip-R R8,1 pin of the 9th Chip-R R9 are connected with VCC; 14 pin of 32 pin of W5500 hardware protocol stacks chip IC 3,2 pin of the 8th Chip-R R8, STM32 processor IC2 connect; 19 pin of 36 pin of W5500 hardware protocol stacks chip IC 3,2 pin of the 9th Chip-R R9, STM32 processor IC2 connect; 35 pin of W5500 hardware protocol stacks chip IC 3,17 pin of STM32 processor IC2 connect; 34 pin of W5500 hardware protocol stacks chip IC 3,16 pin of STM32 processor IC2 connect; 33 pin of W5500 hardware protocol stacks chip IC 3,15 pin of STM32 processor IC2 connect; 1 pin of 37 pin of W5500 hardware protocol stacks chip IC 3,18 pin of STM32 processor IC2, the tenth Chip-R R13 connects; 2 pin of the tenth Chip-R R13 are connected with VCC; 45 pin of W5500 hardware protocol stacks chip IC 3,1 pin of the 11 Chip-R R16 connect; 44 pin of W5500 hardware protocol stacks chip IC 3IC3,1 pin of the 12 Chip-R R17 connect; 43 pin of W5500 hardware protocol stacks chip IC 3,1 pin of the 13 Chip-R R18 connect; 42 pin of W5500 hardware protocol stacks chip IC 3,1 pin of the 14 Chip-R R19 connect; 41 pin of W5500 hardware protocol stacks chip IC 3,1 pin of the 15 Chip-R R20 connect; 40 pin of W5500 hardware protocol stacks chip IC 3,1 pin of the 16 Chip-R R21 connect 39 pin of W5500 hardware protocol stacks chip IC 3,1 pin of the 17 Chip-R R22 connects; 38 pin of W5500 hardware protocol stacks chip IC 3,1 pin of the 18 Chip-R R23 connect; 2 pin of the 11 Chip-R R16,2 pin of the 12 Chip-R R17,2 pin of the 13 Chip-R R18,2 pin of the 14 Chip-R R19,2 pin of the 15 Chip-R R20,2 pin of the 16 Chip-R R21,2 pin of the 17 Chip-R R22,2 pin of the 18 Chip-R R23 are connected with GND; 28 pin of W5500 hardware protocol stacks chip IC 3,21 pin, 17 pin are connected with VCC; 16 pin of W5500 hardware protocol stacks chip IC 3,14 pin, 9 pin are connected with GND.
As shown in Figure 6, described network transformer and RJ45 interface circuit comprise network transformer and RJ45 interface chip IC4 and two Chip-R.1 pin of network transformer and RJ45 interface chip IC4,2 pin of W5500 hardware protocol stacks chip IC 3,2 pin of the second Chip-R R11 are connected; 2 pin of network transformer and RJ45 interface chip IC4,1 pin of W5500 hardware protocol stacks chip IC 3,2 pin of the first Chip-R R10 are connected; Network transformer is connected with 1 pin of the 5th ceramic disc capacitor C12 with 3 pin of RJ45 interface chip IC4; 4 pin of network transformer and RJ45 interface chip IC4,2 pin of the 3rd Chip-R R12,1 pin of the second ceramic disc capacitor C9 are connected; 5 pin of network transformer and RJ45 interface chip IC4,1 pin of the 4th Chip-R R14,1 pin of the 5th Chip-R R15,2 pin of the 4th ceramic disc capacitor C11 are connected; Network transformer is connected with 1 pin of the 3rd ceramic disc capacitor C10 with 6 pin of RJ45 interface chip IC4; Network transformer is connected with 1 pin of the first Chip-R R26 with 12 pin of RJ45 interface chip IC4; Network transformer is connected with 1 pin of the second Chip-R R27 with 9 pin of RJ45 interface chip IC4; 2 pin of the first Chip-R R26,2 pin of the second Chip-R R27 are connected with GND; Network transformer is connected with 27 pin of W5500 hardware protocol stacks chip IC 3 with 10 pin of RJ45 interface chip IC4; Network transformer is connected with 25 pin of W5500 hardware protocol stacks chip IC 3 with 11 pin of RJ45 interface chip IC4; 13 pin, 14 pin of network transformer and RJ45 interface chip IC4 are connected with GND.
As shown in Figure 7, RS232 serial communication circuit comprises RS232 transponder chip IC5, RS232 serial communication interface J3 and five ceramic disc capacitor.1 pin of RS232 transponder chip IC5 is connected with 1 pin of the first ceramic disc capacitor C16; 3 pin of RS232 transponder chip IC5 are connected with 2 pin of the first ceramic disc capacitor C16; 4 pin of RS232 transponder chip IC5 are connected with 1 pin of the second ceramic disc capacitor C18; 5 pin of RS232 transponder chip IC5 are connected with 2 pin of the second ceramic disc capacitor C18; 11 pin of RS232 transponder chip IC5 are connected with 30 pin of STM32 processor IC2; 12 pin of RS232 transponder chip IC5 are connected with 31 pin of STM32 processor IC2; 16 pin of RS232 transponder chip IC5 are connected with 1 pin of the 3rd ceramic disc capacitor C15; 2 pin of RS232 transponder chip IC5 are connected with 1 pin of the 4th ceramic disc capacitor C17; 6 pin of RS232 transponder chip IC5 are connected with 1 pin of the 5th ceramic disc capacitor C19; 2 pin of 2 pin of the 3rd ceramic disc capacitor, 15 pin of RS232 transponder chip, the 4th ceramic disc capacitor, 2 pin of the 5th ceramic disc capacitor C19 are connected with GND; 14 pin of RS232 transponder chip IC5 are connected with 1 pin of RS232 serial communication interface J3; 13 pin of RS232 transponder chip IC5 are connected with 2 pin of RS232 serial communication interface J3.
Power supply voltage stabilizing chip IC 1 adopts the STM32F103C8T6 model of the low pressure difference linearity LDO chip TPS736 model of Texas Instrument, STM32 processor IC2 employing ST company, W5500 hardware protocol stacks chip IC 3 adopts the MAX3232 model that the W5500 model of WIZNET company, network transformer and RJ45 interface chip IC4 adopt the B-TRJ4037FBNL model of Beijing Bo Kong Automation Co., Ltd, RS232 transponder chip IC5 adopts Maxim.
As shown in Figure 8, the operational mode of first judgment means after program brings into operation, if configuration mode is enable, then device enters configuration mode to the software flow of this device.Under this pattern, device accepts the configuration execution that serial ports sends over, and can be configured by configuration-direct to parameters such as TCP or the UDP transmission mode of device, device IP, device port, Target IP, target port, device MAC Address, transparent transmission or MQTT pattern, serial port baud rate.Configure rear automatic preservation.If device enters operational mode, then start judgment means and whether be configured to transparent transmission pattern.Under transparent transmission pattern, device is connected to ethernet server according to the Target IP of configuration parameter and target port and TCP or UDP transmission mode, starts the transparent transmission of data after successful connection.If device is configured to MQTT protocol mode, device is connected to MQTT server according to the Target IP of configuration parameter and target port, after successful connection, carries out reliable communication by issuing subject and topic of subscription and MQTT server and other devices.
Software employs SWD interface in debug process.MQTT server software employs " RSMB " of IBM Corporation.In RS232 serial communication debug process, PC device employs " sscom32 " software and communicates with device.Network service debugging employs " TCP & UDP testing tool " software.Device is connected with PC device by router.
Under MQTT pattern, after device is successfully connected with PC, by distribution subscription theme mutual between " sscom32 " software and " RSMB " software, carry out data communication.Under transparent transmission pattern, after device is successfully connected with PC, carried out the transparent transmission of data by " sscom32 " software and " TCP & UDP testing tool " software.To realize completely and system works is stablized through testing apparatus function repeatedly.
The major parameter of each built-up circuit of this device is as follows:
Serial port baud rate can be arranged from 300bps to 256000bps;
Mode of operation can select TCP_Server, TCP_Client, UDP, UDP_Server mode of operation;
Mode of operation relevant parameter is arranged by serial ports or network;
Compatible 3.3V and 5.0V of Transistor-Transistor Logic level;
Unique heartbeat packet mechanism, ensures to connect true and reliable, stops to connect seemingly-dead;
Prohibit packet broadcast under UDP pattern, strengthen antijamming capability.
Claims (2)
1. the serial ports based on MQTT Internet of Things agreement and Ethernet conversion equipment, comprise voltage conversion circuit, single chip machine controlling circuit, SWD debug i/f circuit, W5500 hardware protocol stack circuit, network transformer and RJ45 interface circuit and RS232 serial communication circuit, it is characterized in that:
Described voltage conversion circuit comprises a double-legged straight cutting binding post, a PPTC resettable fuse, a current-limiting resistance, a light-emitting diode, an anti-reverse diode, a voltage stabilizing didoe, a power supply voltage stabilizing chip, two electrochemical capacitors, two ceramic disc capacitors; 1 pin of both feet straight cutting binding post is connected with 1 pin of PPTC resettable fuse; 1 pin of current-limiting resistance is connected with 2 pin of PPTC resettable fuse, the positive pole of anti-reverse diode, the positive pole of light-emitting diode; The negative pole of 3 pin of power supply voltage stabilizing chip and the negative pole of anti-reverse diode, voltage stabilizing didoe, the positive pole of the first electrochemical capacitor, 1 pin of the first ceramic disc capacitor are connected; 2 pin of power supply voltage stabilizing chip are connected with 1 pin of the positive pole of the second electrochemical capacitor, the second ceramic disc capacitor, export as voltage; Both feet straight cutting binding post 2 pin, light-emitting diode negative pole, voltage stabilizing didoe positive pole, the negative pole of the first electrochemical capacitor, 2 pin of the first ceramic disc capacitor, power supply voltage stabilizing chip 1 pin, the negative pole of the second electrochemical capacitor, 2 pin of the second ceramic disc capacitor are all connected with GND;
Described single chip machine controlling circuit comprises STM32 processor, four Chip-Rs, three ceramic disc capacitors, passive crystal oscillators; 20 pin of STM32 processor are connected with 1 pin of the first Chip-R, and 2 pin of the first Chip-R are connected with GND; 44 pin of STM32 processor are connected with 1 pin of the second Chip-R, and 2 pin of the second Chip-R are connected with GND; 1 pin of 5 pin of STM32 processor, 1 pin of the 3rd Chip-R, passive crystal oscillator, 1 pin of the first ceramic disc capacitor connect, 2 pin of 6 pin of STM32 processor, 2 pin of the 3rd Chip-R, passive crystal oscillator, 1 pin of the second ceramic disc capacitor connect, and 2 pin of the first ceramic disc capacitor, 2 pin of the second ceramic disc capacitor are connected with GND; 1 pin of the 4th Chip-R is connected with VCC, and 1 pin of 2 pin of the 4th Chip-R, 7 pin of STM32 processor, the 3rd ceramic disc capacitor connects, and 2 pin of the 3rd ceramic disc capacitor are connected with GND; 9 pin of STM32 processor, 24 pin, 36 pin, 48 pin are connected with VCC; 8 pin of STM32 processor, 23 pin, 35 pin, 47 pin are connected with GND;
Described SWD interface debugging circuit comprises four pin straight cutting binding posts and two Chip-Rs; 1 pin of four pin straight cutting binding posts, 1 pin of the first Chip-R, 1 pin of the second Chip-R are connected with VCC; 2 pin, 2 pin of the second Chip-R of four pin straight cutting binding posts are connected with 34 pin of STM32 processor; 3 pin, 2 pin of the first Chip-R of four pin straight cutting binding posts are connected with 37 pin of STM32 processor; 4 pin of four pin straight cutting binding posts are connected with GND;
Described W5500 hardware protocol stack circuit comprises W5500 hardware protocol chip stack, passive crystal oscillator, 18 Chip-Rs and seven ceramic disc capacitors; 1 pin of W5500 hardware protocol chip stack is connected with 2 pin of the first Chip-R; 2 pin of W5500 hardware protocol chip stack are connected with 2 pin of the second Chip-R; 1 pin of 1 pin of the first ceramic disc capacitor, 1 pin of the first Chip-R, the second Chip-R, 1 pin of the 3rd Chip-R are connected with VCC; 2 pin of the 3rd Chip-R are connected with 1 pin of the second ceramic disc capacitor; 2 pin of the first ceramic disc capacitor, 2 pin of the second ceramic disc capacitor are connected with GND; 2 pin of 2 pin of the 3rd ceramic disc capacitor, 5 pin of W5500 hardware protocol chip stack, the 4th Chip-R connect; 2 pin of 2 pin of the 5th Chip-R, 6 pin of W5500 hardware protocol chip stack, the 5th ceramic disc capacitor connect; 2 pin of 1 pin of the 4th Chip-R, 1 pin of the 5th Chip-R, the 4th ceramic disc capacitor connect; 1 pin of the 4th ceramic disc capacitor is connected with GND; 1 pin of 30 pin of W5500 hardware protocol chip stack, 1 pin of the 6th Chip-R, the first passive crystal oscillator, 2 pin of the 6th ceramic disc capacitor connect; 2 pin of 31 pin of W5500 hardware protocol chip stack, 2 pin of the 6th Chip-R, the first passive crystal oscillator, 2 pin of the 7th ceramic disc capacitor connect; 1 pin of the 6th ceramic disc capacitor, 1 pin of the 7th ceramic disc capacitor are connected with GND; 10 pin of W5500 hardware protocol chip stack are connected with 2 pin of the 7th Chip-R; 1 pin of the 7th Chip-R is connected with GND; 1 pin of the 8th Chip-R, 1 pin of the 9th Chip-R are connected with VCC; 14 pin of 32 pin of W5500 hardware protocol chip stack, 2 pin of the 8th Chip-R, STM32 processor connect; 19 pin of 36 pin of W5500 hardware protocol chip stack, 2 pin of the 9th Chip-R, STM32 processor connect; 35 pin of W5500 hardware protocol chip stack, 17 pin of STM32 processor connect; 34 pin of W5500 hardware protocol chip stack, 16 pin of STM32 processor connect; 33 pin of W5500 hardware protocol chip stack, 15 pin of STM32 processor connect; 1 pin of 37 pin of W5500 hardware protocol chip stack, 18 pin of STM32 processor, the tenth Chip-R connects; 2 pin of the tenth Chip-R are connected with VCC; 45 pin of W5500 hardware protocol chip stack, 1 pin of the 11 Chip-R connect; 44 pin of W5500 hardware protocol chip stack, 1 pin of the 12 Chip-R connect; 43 pin of W5500 hardware protocol chip stack, 1 pin of the 13 Chip-R connect; 42 pin of W5500 hardware protocol chip stack, 1 pin of the 14 Chip-R connect; 41 pin of W5500 hardware protocol chip stack, 1 pin of the 15 Chip-R connect; 40 pin of W5500 hardware protocol chip stack, 1 pin of the 16 Chip-R connect; 39 pin of W5500 hardware protocol chip stack, 1 pin of the 17 Chip-R connect; 38 pin of W5500 hardware protocol chip stack, 1 pin of the 18 Chip-R connect; 2 pin of the 11 Chip-R, 2 pin of the 12 Chip-R, 2 pin of the 13 Chip-R, 2 pin of the 14 Chip-R, 2 pin of the 15 Chip-R, 2 pin of the 16 Chip-R, 2 pin of the 17 Chip-R, 2 pin of the 18 Chip-R are connected with GND; 28 pin of W5500 hardware protocol chip stack, 21 pin, 17 pin are connected with VCC; 16 pin of W5500 hardware protocol chip stack, 14 pin, 9 pin are connected with GND;
Described network transformer and RJ45 interface circuit comprise network transformer and RJ45 interface chip and two Chip-Rs; 1 pin of network transformer and RJ45 interface chip, 2 pin of W5500 hardware protocol chip stack, 2 pin of the second Chip-R are connected; 2 pin of network transformer and RJ45 interface chip, 1 pin of W5500 hardware protocol chip stack, 2 pin of the first Chip-R are connected; Network transformer is connected with 1 pin of the 5th ceramic disc capacitor with 3 pin of RJ45 interface chip; 4 pin of network transformer and RJ45 interface chip, 2 pin of the 3rd Chip-R, 1 pin of the second ceramic disc capacitor are connected; 5 pin of network transformer and RJ45 interface chip, 1 pin of the 4th Chip-R, 1 pin of the 5th Chip-R, 2 pin of the 4th ceramic disc capacitor are connected; Network transformer is connected with 1 pin of the 3rd ceramic disc capacitor with 6 pin of RJ45 interface chip; Network transformer is connected with 1 pin of the first Chip-R with 12 pin of RJ45 interface chip; Network transformer is connected with 1 pin of the second Chip-R with 9 pin of RJ45 interface chip; 2 pin of the first Chip-R, 2 pin of the second Chip-R are connected with GND; Network transformer is connected with 27 pin of W5500 hardware protocol chip stack with 10 pin of RJ45 interface chip; Network transformer is connected with 25 pin of W5500 hardware protocol chip stack with 11 pin of RJ45 interface chip; 13 pin, 14 pin of network transformer and RJ45 interface chip are connected with GND;
Described RS232 serial communication circuit comprises RS232 transponder chip, RS232 serial communication interface and five ceramic disc capacitors; 1 pin of RS232 transponder chip is connected with 1 pin of the first ceramic disc capacitor; 3 pin of RS232 transponder chip are connected with 2 pin of the first ceramic disc capacitor; 4 pin of RS232 transponder chip are connected with 1 pin of the second ceramic disc capacitor; 5 pin of RS232 transponder chip are connected with 2 pin of the second ceramic disc capacitor; 11 pin of RS232 transponder chip are connected with 30 pin of STM32 processor; 12 pin of RS232 transponder chip are connected with 31 pin of STM32 processor; 16 pin of RS232 transponder chip are connected with 1 pin of the 3rd ceramic disc capacitor; 2 pin of RS232 transponder chip are connected with 1 pin of the 4th ceramic disc capacitor; 6 pin of RS232 transponder chip are connected with 1 pin of the 5th ceramic disc capacitor; 2 pin of 2 pin of the 3rd ceramic disc capacitor, 15 pin of RS232 transponder chip, the 4th ceramic disc capacitor, 2 pin of the 5th ceramic disc capacitor are connected with GND; 14 pin of RS232 transponder chip are connected with 1 pin of RS232 serial communication interface; 13 pin of RS232 transponder chip are connected with 2 pin of RS232 serial communication interface.
2. a kind of serial ports based on MQTT Internet of Things agreement according to claim 1 and Ethernet conversion equipment, is characterized in that: the STM32F103C8T6 model that described power supply voltage stabilizing chip adopts the low pressure difference linearity LDO chip TPS736 model of Texas Instrument, STM32 processor adopts ST company, W5500 hardware protocol chip stack adopt the W5500 model of WIZNET company, network transformer and RJ45 interface chip adopts the B-TRJ4037FBNL model of Beijing Bo Kong Automation Co., Ltd, RS232 transponder chip adopts Maxim MAX3232 model.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109327424A (en) * | 2017-08-01 | 2019-02-12 | 徐州天荣医疗通讯设备有限公司 | Included buffer area MQTT protocol implementing method based on small memory single-chip microcontroller |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109327424A (en) * | 2017-08-01 | 2019-02-12 | 徐州天荣医疗通讯设备有限公司 | Included buffer area MQTT protocol implementing method based on small memory single-chip microcontroller |
| CN109327424B (en) * | 2017-08-01 | 2021-06-04 | 徐州天荣医疗通讯设备有限公司 | MQTT protocol implementation method with buffer area based on small-memory single chip microcomputer |
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