CN204967778U - Low -power consumption chip hardware reset circuit that charges - Google Patents
Low -power consumption chip hardware reset circuit that charges Download PDFInfo
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- CN204967778U CN204967778U CN201520562386.5U CN201520562386U CN204967778U CN 204967778 U CN204967778 U CN 204967778U CN 201520562386 U CN201520562386 U CN 201520562386U CN 204967778 U CN204967778 U CN 204967778U
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Abstract
The utility model discloses a low -power consumption chip hardware reset circuit that charges, including the TP4057 chip, the GHRG foot and the CHA signal port of TP4057 chip are connected, CHA signal port is the exit point of two circuit, article two, one in circuit is connected with vcc1 through resistance R1, and another circuit is established ties in proper order to be had inductance C1 and resistance R2 then be connected with vcc2, pass through resistance R4 connection RESET signal port by another circuit branch road between the inductance C1 that establishes ties and the resistance R2 line, the GND end is connected to the GND foot and the VCC foot of TP4057 chip. The utility model discloses a when adopting TP4057 charging chip to charge in the circuit, the status display IO's that charges level fluctuation realizes the hardware reset of chip, need not the watchdog chip, also need not the button that resets, utilizes the mouth that charges to reset, has practiced thrift the cost, has reduced the consumption.
Description
Technical field
The utility model belongs to electronic circuit field, is specifically related to a kind of low-power chip charger hardware reset circuit.
Background technology
All adopt watchdog chip to carry out monitoring program whether normally to run in current electronic circuit technology, and use watchdog chip can increase hardware cost, simultaneously, watchdog chip is used to need to allow chip timing wake-up feed dog, be unfavorable for that those have the equipment of strict demand to power consumption, generally, adopt watchdog technique hardware cost high, power consumption is large.
Utility model content
The utility model object thing overcomes the deficiencies in the prior art, provides a kind of holistic cost low, the low-power chip charger hardware reset circuit that power consumption is little.
The technical solution of the utility model is: low-power chip charger hardware reset circuit, comprise TP4057 chip, the GHRG pin of described TP4057 chip is connected with CHA signal port, described CHA signal port is the exit point of two circuit branch, in described two circuit branch, a branch road is connected by resistance R1 and Vcc1, another branch road is in series with inductance C1 successively with resistance R2 and then be connected with Vcc2, the branch road that the inductance C1 of described series connection is connected with resistance R2 circuit to be linked in sequence resistance R4 and RESET signal port by another circuit branch again, the GND pin of described TP4057 chip is connected GND earth terminal with VCC pin.
Further, the BAT pin of described TP4057 chip is connected with RAT signal port.
Further, the PROG of described TP4057 chip was called resistance R3 and was connected with GND earth terminal.
Further, the STDBY pin of described TP4057 chip is connected with CHAOVER signal port.
The beneficial effects of the utility model: when the utility model adopts and adopts TP4057 charging chip to charge in circuit, the level change of charged state display IO realizes the hardware reset of chip, without the need to watchdog chip, also without the need to reset key, utilize charge port to reset, save cost, reduce power consumption.
Accompanying drawing explanation
Fig. 1 is the utility model low-power chip charger hardware reset circuit schematic block circuit diagram.
Fig. 2 is the schematic block circuit diagram that the utility model low-power chip charger hardware reset circuit is connected with Fig. 1.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described further
As depicted in figs. 1 and 2, CHA port wherein in Fig. 1 is connected with the CHA port in Fig. 2, a kind of low-power chip charger hardware reset circuit, comprise TP4057 chip, the GHRG pin of described TP4057 chip is connected with CHA signal port, described CHA signal port is the exit point of two circuit branch, in described two circuit branch, a branch road is connected by resistance R1 and Vcc1, another branch road is in series with inductance C1 successively with resistance R2 and then be connected with Vcc2, the branch road that the inductance C1 of described series connection is connected with resistance R2 circuit to be linked in sequence resistance R4 and RESET signal port by another circuit branch again, the GND pin of described TP4057 chip is connected GND earth terminal with VCC pin.
Further, in other pins of described TP4057 chip, the BAT pin of described TP4057 chip is connected with RAT signal port., the PROG pin of described TP4057 chip is held by resistance R3 and GND and is connected.The STDBY pin of described TP4057 chip is connected with CHAOVER signal port.
Particularly, described TP4057 is lithium cell charging chip TP4057 chip circuit principle, when VCC does not access power circuit, when namely not inserting charging head, the CHRG pin of described TP4057 chip is high-impedance state, now, the voltage on the C1 both sides in Fig. 2 is all high level, when reaching poised state, described RESET signal port is high level, and now single-chip microcomputer is working properly, when after insertion charging head, namely after VCC does not access power circuit access power supply, described CHRG leads ends becomes low level, C1 two ends level imbalance in described Fig. 2, enter charged state, RESET signal port first becomes low level, after described C1 charging complete, become high level again again, like this, RESET signal port has just had a low level pulse, then monolithic processor resetting is caused, thus achieve when utilizing charging chip to charge, the level change of charged state display IO realizes the hardware reset of chip, reduce cost, also for because of program fleet and battery is built-in the situation of power-off restoration cannot provide reset function.
The announcement of book and instruction according to the above description, the utility model those skilled in the art can also change above-mentioned execution mode and revise.Therefore, the utility model is not limited to embodiment disclosed and described above, also should fall in the protection range of claim of the present utility model some modifications and changes of utility model.In addition, although employ some specific terms in this specification, these terms just for convenience of description, do not form any restriction to the utility model.
Claims (4)
1. low-power chip charger hardware reset circuit, it is characterized in that, comprise TP4057 chip, the GHRG pin of described TP4057 chip is connected with CHA signal port, described CHA signal port is the exit point of two circuit branch, in described two circuit branch, a branch road is connected by resistance R1 and Vcc1, another branch road is in series with inductance C1 successively with resistance R2 and then be connected with Vcc2, the branch road that the inductance C1 of described series connection is connected with resistance R2 circuit to be linked in sequence resistance R4 and RESET signal port by another circuit branch again, the GND pin of described TP4057 chip is connected GND earth terminal with VCC pin.
2. low-power chip charger hardware reset circuit as claimed in claim 1, it is characterized in that, the BAT pin of described TP4057 chip is connected with BAT signal port.
3. low-power chip charger hardware reset circuit as claimed in claim 1, is characterized in that, the PROG pin of described TP4057 chip is connected with GND earth terminal by resistance R3.
4. low-power chip charger hardware reset circuit as claimed in claim 1, it is characterized in that, the STDBY pin of described TP4057 chip is connected with CHAOVER signal port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520562386.5U CN204967778U (en) | 2015-07-30 | 2015-07-30 | Low -power consumption chip hardware reset circuit that charges |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520562386.5U CN204967778U (en) | 2015-07-30 | 2015-07-30 | Low -power consumption chip hardware reset circuit that charges |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204967778U true CN204967778U (en) | 2016-01-13 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520562386.5U Expired - Fee Related CN204967778U (en) | 2015-07-30 | 2015-07-30 | Low -power consumption chip hardware reset circuit that charges |
Country Status (1)
| Country | Link |
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| CN (1) | CN204967778U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106108848A (en) * | 2016-06-24 | 2016-11-16 | 金进科技（深圳）有限公司 | A kind of intelligent radio wearable device and charger thereof |
-
2015
- 2015-07-30 CN CN201520562386.5U patent/CN204967778U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106108848A (en) * | 2016-06-24 | 2016-11-16 | 金进科技（深圳）有限公司 | A kind of intelligent radio wearable device and charger thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160113 Termination date: 20210730 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |