CN204966012U - GOA unit, gate drive circuit and display device - Google Patents
GOA unit, gate drive circuit and display device Download PDFInfo
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- CN204966012U CN204966012U CN201520745901.3U CN201520745901U CN204966012U CN 204966012 U CN204966012 U CN 204966012U CN 201520745901 U CN201520745901 U CN 201520745901U CN 204966012 U CN204966012 U CN 204966012U
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Abstract
The utility model relates to a GOA unit, gate drive circuit and display device. The GOA unit includes drive module, drive module is used for following first clock signal output of GOA unit, the GOA unit still includes drop -down module, drop -down module is connected with drive module to and connect with at least one low -voltage end, it is used for during GOA unit output closed signals, the low voltage signal who provides at least one low -voltage end imports drive module's control end, so that drive module is in the closed condition, so that drive module is in the closed condition under the control of this low -voltage end. Above -mentioned GOA unit can avoid the mistake of grid line to open, makes the pixel can do not not charged, shows wrong image, just so overcomes the what is called and " draws " the phenomenon different.
Description
Technical field
The utility model relates to display technique field, particularly, relates to a kind of GOA unit, gate driver circuit and display device.
Background technology
In a display device, gate driver circuit provides start signal, and multirow pixel is opened successively, line by line, realizes display.Usually, gate driver circuit comprises multi-stage shift register, and every grade of shift register is corresponding with one-row pixels; When one-row pixels is opened, the shift register generation drive singal that this row pixel is corresponding, is input in the grid line be connected with this row pixel, thus drives this row pixel to open.
At present, in order to realize the lightening of display device, increasing gate driver circuit adopts GOA technology (namely GateonArray is prepared in grid driving chip on array base palte), in the gate driver circuit adopting GOA technology, its shift register is referred to as GOA unit.
In existing display device, every grade of GOA unit exports shutdown signal after driving the one-row pixels of its correspondence to open, and is in suspension (Flooding) state; In the case, due to signal cross-talk, the signal that the GOA unit being in suspended state is easily coupled into opens by mistake and opens, thus causes the one-row pixels corresponding with this GOA unit to be charged, thus the image of display mistake, i.e. so-called " drawing different " phenomenon.
Summary of the invention
The utility model is intended at least to solve one of technical matters existed in prior art, propose a kind of GOA unit, gate driver circuit and display device, it can avoid opening by mistake of grid line to open, and pixel can not be charged, the image of display mistake, so just overcomes what is called and " draws " phenomenon different.
A kind of GOA unit is provided for realizing the purpose of this utility model, it comprises driver module, described driver module is used for the output terminal of the first clock signal from described GOA unit to export, described GOA unit also comprises drop-down module, described drop-down module is connected with driver module, and be connected with at least one low-voltage end, it is for when described GOA unit exports shutdown signal, the low voltage signal that at least one low-voltage end provides is input to the control end of driver module, under the control of this low-voltage end, is in closed condition to make described driver module.
Wherein, described drop-down module comprises the first submodule, the second submodule and the 3rd submodule; The described first end of the first submodule is connected with the control end of driver module, and the second end is connected with a low-voltage end, and the 3rd end is connected with the second submodule and the 3rd submodule; The first end of described second submodule connects input signal end, and the second end connects second clock signal, and the 3rd end is connected with the first submodule; The first end of the 3rd submodule is connected with a low-voltage end, and the second end is connected with the control end of driver module, and the 3rd end is connected with the first submodule.
Wherein, described drop-down unit also comprises the 4th submodule; The first end of described 4th submodule is connected with the output terminal of described GOA unit, and the second end is connected with a low-voltage end, and the 3rd end is connected with the second submodule and the 3rd submodule.
Wherein, described first submodule comprises the 4th transistor; The control pole of described 4th transistor belongs to the 3rd end of the first submodule, and it is connected with the second submodule, the 3rd submodule; Source electrode belongs to the second end of the first submodule, and it is connected with a low-voltage end; Drain electrode belongs to the first end of the first submodule, and it is connected with the control end of driver module.
Wherein, described 4th submodule comprises the 5th transistor; 3rd end of the control of described 5th transistor very the 4th submodule, it is connected with the second submodule, the 3rd submodule; Source electrode is the second end of the 4th submodule, and it is connected with a low-voltage end; Drain electrode is the first end of the 4th submodule, and it is connected with the output terminal of described GOA unit.
Wherein, described second submodule comprises the first transistor and transistor seconds; Second end of very described second submodule of control of described the first transistor, it is connected with second clock signal; Source electrode is the first end of described second submodule, and it is connected with input signal end; Drain and to be connected with the control pole of transistor seconds and source electrode; The drain electrode of described transistor seconds is the 3rd end of described second submodule, and it is connected with the first submodule; Described input signal end is high voltage end or second clock signal.
Wherein, described 3rd submodule comprises third transistor; Second end of very described 3rd submodule of control of described third transistor, it is connected with the control end of driver module; Source electrode is the first end of described 3rd submodule, and it is connected with a low-voltage end; Drain electrode is the 3rd end of described 3rd submodule, and it is connected with the first submodule.
Wherein, described first submodule comprises the 4th transistor; Described second submodule comprises the first transistor and transistor seconds; Described 3rd submodule comprises third transistor;
The control pole of described the first transistor is connected with second clock signal, and source electrode is connected with input signal end, drains to be connected with the control pole of transistor seconds and source electrode;
The drain electrode of described transistor seconds is connected with the control pole of the 4th transistor;
The control pole of described third transistor is connected with the control end of driver module, and source electrode is connected with a low-voltage end, and drain electrode is connected with the control pole of the 4th transistor;
The source electrode of described 4th transistor is connected with a low-voltage end, and drain electrode is connected with the control end of driver module; Described input signal end is high voltage end or second clock signal.
Wherein, the low-voltage end be connected with the source electrode of described third transistor and the low-voltage end be connected with the source electrode of the 4th transistor are same voltage end.
Wherein, described drop-down module also comprises the 4th submodule, and described 4th submodule comprises the 5th transistor; The control pole of described 5th transistor is connected with the second submodule, the 3rd submodule; Source electrode is connected with a low-voltage end; Drain electrode is connected with the output terminal of described GOA unit.
Wherein, the low-voltage end be connected with the source electrode of described third transistor, the low-voltage end be connected with the source electrode of the 4th transistor and the low-voltage end be connected with the source electrode of the 5th transistor are same voltage end.
Wherein, described GOA unit also comprises pull-up module, and the output terminal of described pull-up module is connected with driver module, and for inputting pull-up signal to described driver module, described pull-up signal makes described driver module open.
Wherein, described driver module comprises driving transistors;
The control end of the control of described driving transistors very driver module, it is connected with the output terminal of described pull-up module; The source electrode of described driving transistors is connected with the first clock signal, and drain electrode is connected with the output terminal of described GOA unit.
Wherein, described GOA unit also comprises reseting module, and described reseting module is connected with driver module, for the output terminal input low voltage signal to described driver module and described GOA unit, described driver module is closed, and the signal described GOA unit exported is drop-down.
Wherein, described pull-up module comprises the 6th transistor and the first electric capacity;
The control pole of described 6th transistor is connected with pull-up signal with source electrode, and drain electrode is connected with the control pole of driving transistors;
Between the drain electrode that the first end of described first electric capacity is connected to described 6th transistor and the control pole of driving transistors, the second end is connected with the output terminal of described GOA unit.
Wherein, described reseting module comprises the 8th transistor and the 9th transistor;
The control pole of described 8th transistor is connected with reset signal end, and source electrode is connected with a low-voltage end, and drain electrode is connected with the control end of driver module;
The control pole of described 9th transistor is connected with reset signal end, and source electrode is connected with a low-voltage end, and drain electrode is connected with the output terminal of described GOA unit.
Wherein, the voltage that described input signal end exports equals the cut-in voltage of gate driver circuit.
As another technical scheme, the utility model also provides a kind of gate driver circuit, and it comprises the above-mentioned GOA unit that the utility model provides.
As another technical scheme, the utility model also provides a kind of display device, and it comprises the above-mentioned gate driver circuit that the utility model provides.
The utility model has following beneficial effect:
The GOA unit that the utility model provides, when it exports shutdown signal, the control end of described driver module is communicated with at least one low-voltage end by drop-down module, like this, described low-voltage end is to the control end input low voltage signal of driver module, driver module can be made to remain closedown in this process, thus, driver module can be avoided by the unblanking be coupled into because of signal cross-talk, in the case, GOA unit can maintain the state exporting shutdown signal all the time, and can not output start signal mistakenly as described in the prior art, and then, avoid opening by mistake of grid line to open, pixel can not be charged, the image of display mistake, so just overcome what is called and " draw " phenomenon different.
The gate driver circuit that the utility model provides, its GOA unit adopting the utility model to provide, can avoid opening by mistake of grid line to open, pixel can not be charged, and the image of display mistake, so just overcomes what is called and " draw " phenomenon different.
The display device that the utility model provides, its gate driver circuit adopting the utility model to provide, can avoid opening by mistake of grid line to open, pixel can not be charged, and the image of display mistake, so just overcomes what is called and " draw " phenomenon different.
Accompanying drawing explanation
Accompanying drawing is used to provide further understanding of the present utility model, and forms a part for instructions, is used from explanation the utility model, but does not form restriction of the present utility model with embodiment one below.In the accompanying drawings:
The schematic diagram of the GOA unit that Fig. 1 provides for the utility model embodiment;
A kind of circuit diagram that Fig. 2 is GOA unit shown in Fig. 1;
Fig. 3 is the sequential chart of signal each in circuit diagram shown in Fig. 2;
The another kind of circuit diagram that Fig. 4 is GOA unit shown in Fig. 1;
The asynchronous schematic diagram of low-voltage end that the source electrode that Fig. 5 is the 4th transistor is connected with the source electrode of third transistor;
Fig. 6 is the asynchronous schematic diagram of low-voltage end that the 4th transistor is connected with the source electrode of third transistor with the source electrode of the 5th transistor.
Wherein, Reference numeral:
1: driver module; 2: drop-down module; 3: pull-up module; 4: reseting module; 21: the first submodules; 22: the second submodules; 23: the three submodules; 24: the four submodules.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in detail.Should be understood that, embodiment described herein, only for instruction and explanation of the utility model, is not limited to the utility model.
The utility model provides a kind of embodiment of GOA unit.The schematic diagram of the GOA unit that Fig. 1 provides for the utility model embodiment.As shown in Figure 1, in the present embodiment, described GOA unit comprises driver module 1 and drop-down module 2; Wherein, described driver module 1 is for exporting the output terminal OUTPUT of the first clock signal clk from described GOA unit; Described drop-down module 2 is connected with driver module 1, and be connected with low-voltage end VSS, it is for when described GOA unit exports shutdown signal, the low voltage signal that described low-voltage end VSS provides is input to the control end of driver module 1, under the control of described low-voltage end VSS, is in closed condition to make described driver module 1.
In the present embodiment, when described GOA unit exports shutdown signal, the low voltage signal that low-voltage end VSS provides is input to the control end of described driver module 1 by drop-down module 2, driver module 1 will be made like this to keep in this process closing, thus, driver module 1 can be avoided by the unblanking be coupled into because of signal cross-talk, in the case, GOA unit can maintain the state exporting shutdown signal all the time, and can not output start signal mistakenly as described in the prior art, and then, avoid opening by mistake of grid line to open, pixel can not be charged, the image of display mistake, so just overcome what is called and " draw " phenomenon different.
Particularly, described drop-down module 2 comprises the first submodule 21, second submodule 22 and the 3rd submodule 23; The first end of described first submodule 21 is connected with the control end of driver module 1, and the second end is connected with low-voltage end VSS, and the 3rd end is connected with the second submodule 22 and the 3rd submodule 23; The first end of described second submodule 22 connects input signal end, and the second end connects second clock signal CLKB, and the 3rd end is connected with the first submodule 21; The first end of the 3rd submodule 23 is connected with low-voltage end VSS, and the second end is connected with the control end of driver module 1, and the 3rd end is connected with the first submodule 21.
Optionally, input signal end can be high voltage end VGH or second clock signal CLKB.
Particularly, described GOA unit also comprises pull-up module 3, the output terminal of described pull-up module 3 is connected with driver module 1, for inputting pull-up signal to described driver module 1, the current potential of pull-up node PU (node between pull-up module 3 and driver module 1) is drawn high by described pull-up signal, thus described driver module 1 is opened.
Optionally, if described GOA unit is positioned at the first row of gate driver circuit, then described pull-up signal is STV signal, the start signal namely shown; If described GOA unit is positioned at the second row or any a line afterwards of gate driver circuit, then described pull-up signal is the signal that the output terminal OUTPUT of lastrow GOA unit exports.
Described GOA unit also comprises reseting module 4, described reseting module 4 is connected with driver module 1, input low voltage signal for the output terminal OUTPUT to described driver module 1 and described GOA unit, described driver module 1 is closed, and the signal described GOA unit exported is drop-down.
A kind of circuit diagram that Fig. 2 is GOA unit shown in Fig. 1, Fig. 3 is the sequential chart of signal each in circuit diagram shown in Fig. 2.Below in conjunction with the circuit structure of Fig. 2 and Fig. 3 to GOA unit in the utility model embodiment, and the principle of work of described GOA unit is described and illustrates.It should be noted that, in fig. 2, each thin film transistor (TFT) is N-type pipe.
As shown in Figure 2, described first submodule 21 comprises the 4th transistor M4.Particularly, the control pole of described 4th transistor M4 belongs to the 3rd end of the first submodule 21, and it is connected with the second submodule 22, the 3rd submodule 23; Source electrode belongs to the second end of the first submodule 21, and it is connected with low-voltage end VSS; Drain electrode belongs to the first end of the first submodule 21, and it is connected with the control end of driver module 1.Described second submodule 22 comprises the first transistor M1 and transistor seconds M2.Second end of very described second submodule 22 of control of described the first transistor M1, it is connected with second clock signal CLKB; Source electrode is the first end of described second submodule 22, and it is connected with input signal end (i.e. high voltage end VGH); Drain and to be connected with the control pole of transistor seconds M2 and source electrode.The drain electrode of described transistor seconds M2 is the 3rd end of described second submodule 22, and it is connected with the first submodule 21.Described 3rd submodule 23 comprises third transistor M3; Second end of very described 3rd submodule 23 of control of described third transistor M3, it is connected with the control end of driver module 1; Source electrode is the first end of described 3rd submodule 23, and it is connected with low-voltage end VSS; Drain electrode is the 3rd end of described 3rd submodule 23, and it is connected with the first submodule 21.
Described driver module 1 comprises driving transistors M7.The control end of the very described driver module 1 of control of described driving transistors M7, it is connected with the output terminal of described pull-up module 3, and source electrode is connected with the first clock signal clk, and drain electrode is connected with the output terminal OUTPUT of described GOA unit.
Described pull-up module 3 comprises the 6th transistor M6 and the first electric capacity C1.The control pole of described 6th transistor M6 is connected with pull-up signal with source electrode, and drain electrode is connected with the control pole of driving transistors M7; Between the drain electrode that the first end of described first electric capacity C1 is connected to described 6th transistor M6 and the control pole of driving transistors M7, the second end is connected with the output terminal OUTPUT of described GOA unit.
Described reseting module 4 comprises the 8th transistor M8 and the 9th transistor M9.The control pole of described 8th transistor M8 is connected with reset signal end Reset, and source electrode is connected with low-voltage end VSS, and drain electrode is connected with the control pole of driving transistors M7; The control pole of described 9th transistor M9 is connected with reset signal end Reset, and source electrode is connected with low-voltage end VSS, and drain electrode is connected with the output terminal OUTPUT of described GOA unit.
With regard to the GOA unit that the utility model embodiment provides, in the first stage, second clock signal CLKB is low level, and the first transistor M1 and transistor seconds M2 is closed; Reset signal Reset is low level, and the 8th transistor M8 and the 9th transistor M9 is closed; Pull-up signal (in this case STV signal, represent that this GOA unit is positioned at the first row of gate driver circuit) be high level, the current potential of pull-up node PU is drawn high, in the case, the first end of the first electric capacity C1 is charged, and driving transistors M7 opens, and then, first clock signal clk is exported from output terminal OUTPUT by driving transistors M7, and is input to the second end of the first electric capacity; Meanwhile, third transistor M3 is unlocked, and then the control pole of the 4th transistor M4 is connected with low-voltage end VSS, makes it close in this first stage.
In subordinate phase, STV signal becomes low level, 6th transistor M6 is closed, makes pull-up node PU keep high level like this, and be in suspended state, and the first clock signal clk becomes high level from low level, the output terminal OUTPUT of GOA unit is made to export high level, meanwhile, to the second end charging of the first electric capacity C1, first electric capacity C1 is booted, the current potential of pull-up node PU is raised further.
In the phase III, reset signal Reset becomes high level from low level, 8th transistor M8 and the 9th transistor M9 is opened, thus pull-up node PU is connected with low-voltage end VSS, the output terminal OUTPUT of GOA unit is also connected with low-voltage end VSS, is appreciated that in the case, driving transistors M7 closes, and GOA unit exports shutdown signal.
In fourth stage, second clock signal CLKB is high level, the first transistor M1 and transistor seconds M2 is opened, thus make the current potential of the control pole of the 4th transistor M4 be high level, 4th transistor M4 is opened, in the case, low-voltage end VSS is connected with the control pole of driving transistors M7 through the 4th transistor M4, thus in this stage, driving transistors M7 can maintain closed condition, and the signal that can not be coupled in this GOA unit opens by mistake and opens, make the start signal of described GOA unit output error, cause one-row pixels opening by mistake, the image of display mistake.
By reference to the accompanying drawings the structure of GOA unit and the principle of work of its each cycle period are illustrated and are described above, according to above-mentioned known, when GOA unit exports shutdown signal, the GOA unit that present embodiment provides can be avoided GOA unit to be opened by mistake opening, the signal of output error, makes display device show mistake.
In the present embodiment, the circuit structure of GOA unit is not limited to shown in Fig. 2, and particularly, as shown in Figure 4, described drop-down unit 2 also comprises the 4th submodule 24; The described first end of the 4th submodule 24 is connected with the output terminal OUTPUT of described GOA unit, and the second end is connected with low-voltage end VSS, and the 3rd end is connected with the second submodule 22 and the 3rd submodule 23.Particularly, described 4th submodule 24 can comprise the 5th transistor M5.3rd end of the control of described 5th transistor M5 very the 4th submodule 24, the drain electrode of transistor seconds M2 in itself and the second submodule 22, and in the 3rd submodule 23, the drain electrode of third transistor M3 connects; Source electrode is the second end of the 4th submodule 24, and it is connected with low-voltage end VSS; Drain electrode is the first end of the 4th submodule 24, and it is connected with the output terminal OUTPUT of described GOA unit.Arranging like this can when GOA unit exports shutdown signal, second end of the first electric capacity C1 is connected with low-voltage end VSS with output terminal OUTPUT, the signal that further guarantee exports from the output terminal OUTPUT of GOA unit is shutdown signal, and improvement is to a greater degree coupled into the signal of this GOA unit to the harmful effect of GOA unit.
In addition, in the present embodiment, drop-down module 2 can also be connected with multiple low-voltage end, and such as, as shown in Figure 5, the source electrode of described third transistor M3 is connected with the first low-voltage end VSS1, and the source electrode of described 4th transistor is connected with the second low-voltage end VSS2; And, as shown in Figure 6, the source electrode of third transistor M3 is connected with the first low-voltage end VSS1,4th transistor M4 is connected with the second low-voltage end VSS2 with the source electrode of the 5th transistor M5, certainly, for embodiment illustrated in fig. 6, the low-voltage end that described transistor seconds M4 is connected with the 5th transistor M5 also can for different low-voltage ends.When described GOA unit exports shutdown signal, the low-voltage end that the source electrode of described 4th transistor M4 connects is to the control pole input low voltage signal of driving transistors M7.
Optionally, third transistor M3, the 4th transistor M4, the low-voltage end that the 5th transistor M5 connects is identical low-voltage end, to reduce the quantity needing the power port arranged.
Further, the low-voltage end that described drop-down module 2 connects can also for different low-voltage ends from the low-voltage end that reseting module 4 connects, and the low voltage signal only needing the low-voltage end connected both it to export can make described driving transistors M7 close.
Optionally, the low-voltage end that described drop-down module 2 connects is identical with the voltage of the low-voltage end that reseting module 4 connects, to reduce the quantity needing the power port arranged.
Correspondingly, the voltage that preferred described input signal end exports equals the cut-in voltage of gate driver circuit, and the voltage that such as high voltage end VGH exports equals the cut-in voltage of gate driver circuit; So directly use existing high voltage in gate driver circuit, the quantity of power port can be reduced, and simplify circuit structure.
In addition, it should be noted that, in the present embodiment, the signal waveform of described second clock signal CLKB is not limited to shown in Fig. 3, in practice, it need when pull-up node PU be high level, and the voltage meeting the control pole of the 4th transistor M4 is low level (for the embodiment that drop-down module 2 comprises the 5th transistor M5, also need to meet the voltage of the control pole of the 5th transistor M5 is pulled to low level).
Optionally, second clock signal CLKB and the first clock signal clk waveform anti-phase.
The GOA unit that present embodiment provides, when it exports shutdown signal, the control end of described driver module 1 is communicated with low-voltage end VSS by drop-down module 2, like this, low-voltage end VSS is to the control end input low voltage signal of driver module 1, driver module 1 can be made to remain closedown in this process, thus, driver module 1 can be avoided by the unblanking be coupled into because of signal cross-talk, in the case, GOA unit can maintain the state exporting shutdown signal all the time, and can not output start signal mistakenly as described in the prior art, and then, avoid opening by mistake of grid line to open, pixel can not be charged, the image of display mistake, so just overcome what is called and " draw " phenomenon different.
The utility model also provides a kind of embodiment of gate driver circuit.In the present embodiment, described gate driver circuit comprises the GOA unit that the above-mentioned embodiment of the utility model provides.
The gate driver circuit that the utility model embodiment provides, its GOA unit adopting the above-mentioned embodiment of the utility model to provide, can avoid opening by mistake of grid line to open, pixel can not be charged, the image of display mistake, so just overcomes what is called and " draws " phenomenon different.
The utility model also provides a kind of embodiment of display device.In the present embodiment, described display device comprises the gate driver circuit that the above-mentioned embodiment of the utility model provides.
The display device that the utility model embodiment provides, its gate driver circuit adopting the above-mentioned embodiment of the utility model to provide, can avoid opening by mistake of grid line to open, pixel can not be charged, the image of display mistake, so just overcomes what is called and " draws " phenomenon different.
Be understandable that, the illustrative embodiments that above embodiment is only used to principle of the present utility model is described and adopts, but the utility model is not limited thereto.For those skilled in the art, when not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection domain of the present utility model.
Claims (19)
1. a GOA unit, comprise driver module, described driver module is used for the output terminal of the first clock signal from described GOA unit to export, it is characterized in that, described GOA unit also comprises drop-down module, and described drop-down module is connected with driver module, and be connected with at least one low-voltage end, the low voltage signal that at least one low-voltage end provides, for when described GOA unit exports shutdown signal, is input to the control end of driver module, is in closed condition to make described driver module by it.
2. GOA unit according to claim 1, is characterized in that, described drop-down module comprises the first submodule, the second submodule and the 3rd submodule;
The described first end of the first submodule is connected with the control end of driver module, and the second end is connected with a low-voltage end, and the 3rd end is connected with the second submodule and the 3rd submodule;
The first end of described second submodule connects input signal end, and the second end connects second clock signal, and the 3rd end is connected with the first submodule;
The first end of the 3rd submodule is connected with a low-voltage end, and the second end is connected with the control end of driver module, and the 3rd end is connected with the first submodule.
3. GOA unit according to claim 2, is characterized in that, described drop-down unit also comprises the 4th submodule;
The first end of described 4th submodule is connected with the output terminal of described GOA unit, and the second end is connected with a low-voltage end, and the 3rd end is connected with the second submodule and the 3rd submodule.
4. the GOA unit according to Claims 2 or 3, is characterized in that, described first submodule comprises the 4th transistor;
3rd end of the control of described 4th transistor very the first submodule, it is connected with the second submodule, the 3rd submodule; Source electrode is the second end of the first submodule, and it is connected with a low-voltage end; Drain electrode is the first end of the first submodule, and it is connected with the control end of driver module.
5. GOA unit according to claim 3, is characterized in that, described 4th submodule comprises the 5th transistor;
3rd end of the control of described 5th transistor very the 4th submodule, it is connected with the second submodule, the 3rd submodule; Source electrode is the second end of the 4th submodule, and it is connected with a low-voltage end; Drain electrode is the first end of the 4th submodule, and it is connected with the output terminal of described GOA unit.
6. GOA unit according to claim 2, is characterized in that, described second submodule comprises the first transistor and transistor seconds;
Second end of very described second submodule of control of described the first transistor, it is connected with second clock signal; Source electrode is the first end of described second submodule, and it is connected with input signal end; Drain and to be connected with the control pole of transistor seconds and source electrode;
The drain electrode of described transistor seconds is the 3rd end of described second submodule, and it is connected with the first submodule;
Described input signal end is high voltage end or second clock signal.
7. GOA unit according to claim 2, is characterized in that, described 3rd submodule comprises third transistor;
Second end of very described 3rd submodule of control of described third transistor, it is connected with the control end of driver module; Source electrode is the first end of described 3rd submodule, and it is connected with a low-voltage end; Drain electrode is the 3rd end of described 3rd submodule, and it is connected with the first submodule.
8. GOA unit according to claim 2, is characterized in that, described first submodule comprises the 4th transistor; Described second submodule comprises the first transistor and transistor seconds; Described 3rd submodule comprises third transistor;
The control pole of described the first transistor is connected with second clock signal, and source electrode is connected with input signal end, drains to be connected with the control pole of transistor seconds and source electrode;
The drain electrode of described transistor seconds is connected with the control pole of the 4th transistor;
The control pole of described third transistor is connected with the control end of driver module, and source electrode is connected with a low-voltage end, and drain electrode is connected with the control pole of the 4th transistor;
The source electrode of described 4th transistor is connected with a low-voltage end, and drain electrode is connected with the control end of driver module;
Described input signal end is high voltage end or second clock signal.
9. GOA unit according to claim 8, is characterized in that, the low-voltage end be connected with the source electrode of described third transistor and the low-voltage end be connected with the source electrode of the 4th transistor are same voltage end.
10. GOA unit according to claim 8 or claim 9, it is characterized in that, described drop-down module also comprises the 4th submodule, and described 4th submodule comprises the 5th transistor;
The control pole of described 5th transistor is connected with the second submodule, the 3rd submodule; Source electrode is connected with a low-voltage end; Drain electrode is connected with the output terminal of described GOA unit.
11. GOA unit according to claim 10, it is characterized in that, the low-voltage end be connected with the source electrode of described third transistor, the low-voltage end be connected with the source electrode of the 4th transistor and the low-voltage end be connected with the source electrode of the 5th transistor are same voltage end.
12. GOA unit according to claim 1, it is characterized in that, described GOA unit also comprises pull-up module, and the output terminal of described pull-up module is connected with driver module, for inputting pull-up signal to described driver module, described pull-up signal makes described driver module open.
13. GOA unit according to claim 12, is characterized in that, described driver module comprises driving transistors;
The control end of the control of described driving transistors very driver module, it is connected with the output terminal of described pull-up module; The source electrode of described driving transistors is connected with the first clock signal, and drain electrode is connected with the output terminal of described GOA unit.
14. GOA unit according to claim 12 or 13, it is characterized in that, described GOA unit also comprises reseting module, described reseting module is connected with driver module, for the output terminal input low voltage signal to described driver module and described GOA unit, described driver module is closed, and the signal described GOA unit exported is drop-down.
15. GOA unit according to claim 13, is characterized in that, described pull-up module comprises the 6th transistor and the first electric capacity;
The control pole of described 6th transistor is connected with pull-up signal with source electrode, and drain electrode is connected with the control pole of driving transistors;
Between the drain electrode that the first end of described first electric capacity is connected to described 6th transistor and the control pole of driving transistors, the second end is connected with the output terminal of described GOA unit.
16. GOA unit according to claim 14, is characterized in that, described reseting module comprises the 8th transistor and the 9th transistor;
The control pole of described 8th transistor is connected with reset signal end, and source electrode is connected with a low-voltage end, and drain electrode is connected with the control end of driver module;
The control pole of described 9th transistor is connected with reset signal end, and source electrode is connected with a low-voltage end, and drain electrode is connected with the output terminal of described GOA unit.
17. GOA unit according to claim 6 or 8, is characterized in that, the voltage that described input signal end exports equals the cut-in voltage of gate driver circuit.
18. 1 kinds of gate driver circuits, is characterized in that, comprise the GOA unit described in claim 1 ~ 17 any one.
19. 1 kinds of display device, is characterized in that, comprise gate driver circuit according to claim 18.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520745901.3U CN204966012U (en) | 2015-09-23 | 2015-09-23 | GOA unit, gate drive circuit and display device |
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| CN201520745901.3U CN204966012U (en) | 2015-09-23 | 2015-09-23 | GOA unit, gate drive circuit and display device |
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| CN204966012U true CN204966012U (en) | 2016-01-13 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105096811A (en) * | 2015-09-23 | 2015-11-25 | 京东方科技集团股份有限公司 | Gate on array (GOA) unit, gate driving circuit and display device |
| US11127336B2 (en) | 2015-09-23 | 2021-09-21 | Boe Technology Group Co., Ltd. | Gate on array (GOA) unit, gate driver circuit and display device |
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2015
- 2015-09-23 CN CN201520745901.3U patent/CN204966012U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105096811A (en) * | 2015-09-23 | 2015-11-25 | 京东方科技集团股份有限公司 | Gate on array (GOA) unit, gate driving circuit and display device |
| WO2017049853A1 (en) * | 2015-09-23 | 2017-03-30 | 京东方科技集团股份有限公司 | Goa unit, gate driving circuit and display device |
| CN105096811B (en) * | 2015-09-23 | 2017-12-08 | 京东方科技集团股份有限公司 | GOA unit, gate driving circuit and display device |
| US11127336B2 (en) | 2015-09-23 | 2021-09-21 | Boe Technology Group Co., Ltd. | Gate on array (GOA) unit, gate driver circuit and display device |
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