CN204886680U - Second harmonic current compensation ware - Google Patents

Abstract

The utility model provides a second harmonic current compensation ware. The second harmonic compensator comprises main power circuit and control circuit, and wherein, main power circuit comprises synchronous Rectifier buck converter, input voltage sampling circuit, output voltage sampling circuit and electric current sampling circuit, and control circuit includes single power circuit 1 ware, first adder, power circuit 2, divider, multiplier, power circuit 3. Second harmonic current compensation ware has fine second harmonic current compensation effect, just compensates the effect and not influenced by the operating mode.

Description

A kind of second harmonic current compensator

Technical field

The present invention relates to a kind of second harmonic current compensator, this compensator can be used for the second harmonic current that absorbs in pfc converter output current or provide second harmonic current in input current of inverter, belongs to Technics of Power Electronic Conversion and control technology field.

Background technology

Single-phase power factor correcting (PFC) converter and single-phase inverter are widely used in middle low power occasion, wherein Single-phase PFC converter connects the electrical energy changer exchanged between input source and DC load, and single-phase inverter is then the important interface connecting direct current input source and AC load or AC network.

For Single-phase PFC converter, its Instantaneous input power is pulsed with two times of input voltage frequencies, owing to exporting as straight voltage, thus there is the pulsating current of two times of output voltage frequency in its output current, i.e. so-called second harmonic current; And concerning single-phase inverter, its instantaneous output is pulsed with two times of output voltage frequency, owing to being input as straight voltage, thus also there is second harmonic current in its input current.Second harmonic current produces adverse influence by the service behaviour of DC load or direct current input source.If use Single-phase PFC converter driving LED, then the second harmonic current in pfc converter output current will cause LED stroboscopic, and then damage human eye.If the input source of single-phase inverter is photovoltaic cell, then the second harmonic current in input current of inverter is vibrated causing the power output of photovoltaic cell near maximum power point, reduces the efficiency of MPPT, and then reduces the utilance of solar energy.If the input source of single-phase inverter is fuel cell or storage battery, then the second harmonic current in input current of inverter will reduce the energy conversion efficiency of battery, increase the caloric value of battery and shorten useful life of battery.Therefore, in order to reduce the adverse effect that second harmonic current produces DC load such as LED, and improve the utilization ratio of other direct current input source such as photovoltaic cell, fuel cell, storage battery, need the second harmonic current suppressing or even eliminate in Single-phase PFC converter and single-phase inverter.

For single stage type Single-phase PFC converter and single-phase inverter, the electric capacity increasing DC load side or direct current input source side is conducive to reducing second harmonic current; For two-stage type Single-phase PFC converter and single-phase inverter, second harmonic current can also be reduced by the method increasing intermediate bus bar electric capacity.But, because required capacitance is usually comparatively large, generally need the electrochemical capacitor selecting energy storage density higher.But only having several thousand hours the useful life of electrochemical capacitor, and shorten with the rising of temperature, is restriction transducer reliability and the main element in useful life.

In order to suppress and eliminate second harmonic current, can also on DC load side, direct current input source side or intermediate dc bus a second harmonic current compensator in parallel, utilize it to the second harmonic current absorbed in pfc converter output current or the second harmonic current provided in input current of inverter.Although also need a storage capacitor in second harmonic current compensator, but the mains ripple at these storage capacitor two ends can suitably increase, thus significantly can reduce the capacity of storage capacitor, and then longer thin-film capacitor replaces electrochemical capacitor as storage capacitor useful life, improve reliability and the useful life of converter thus.

According to power grade and the input and output voltage size of pfc converter and inverter, second harmonic current compensator can select different circuit topologies.In order to obtain good second harmonic current compensation effect, the control method of compensator is most important.KreinP etc. use full-bridge inverter as second harmonic current compensator in " Minimumenergyandcapacitancerequirementsforsingle-phasein vertersandrectifiersusingarippleport [J] .IEEETransactionsonPowerElectronics; 2012; 27 (11): 4690 – 4698. ", during the second harmonic current provided completely when compensator in input current of inverter of having derived, export the transient expression formula of storage capacitor voltage, and using this benchmark as storage capacitor voltage.Like this, as long as control this voltage reference of storage capacitor voltage-tracing can obtain good second harmonic current compensation effect.But, the amplitude of this voltage reference is relevant to the amount of capacity of the power output of inverter and storage capacitor, the phase place of voltage reference need meet strict quantitative relation with the phase place of inverter output voltage, thus this voltage reference is obtained comparatively complicated, need the power output calculating inverter in real time, and phase-locked control is carried out to storage capacitor voltage.Meanwhile, the amount of capacity of storage capacitor can change with ambient temperature and the withstand voltage of electric capacity two ends, and thus the change of operating mode can affect the compensation effect of second harmonic current.WangR and WangF etc. use the two-way Buck/boost converter working in DCM pattern as second harmonic current compensator in " Ahighpowerdensitysingle-phasePWMrectifierwithactiverippl eenergystorage [J] .IEEETransactionsonPowerElectronics; 2011; 26 (5): 1430 – 1443. ", and the duty ratio of switching tube of having derived is with the Changing Pattern of second harmonic current benchmark.Like this, the duty ratio of direct control switch pipe by the rule change obtained of deriving, the mean value of the input current of compensator in a switch periods can be made to follow the tracks of second harmonic current benchmark.But, the Changing Pattern of switching tube duty ratio is relevant with the inductance value of output inductor in compensator, and the inductance value of inductance can change with ambient temperature and load current change, thus, the compensation effect of second harmonic current can be subject to the impact of ambient temperature and load.In addition, compensator works in DCM pattern, in switching tube the peak value of electric current and effective value all higher, the conduction loss of compensator is larger.Adopt similar control method, CaoX and ZhongQ etc. use the two-way Buck-boost converter working in DCM pattern as second harmonic current compensator in " Rippleeliminatortosmoothdc-busvoltageandreducethetotalca pacitancerequired [J] .IEEETransactionsonIndustrialElectronics; 2015; 62 (4): 2224 – 2235. ", also obtain good second harmonic current compensation effect.But the compensation effect of second harmonic current is subject to the impact of ambient temperature and load equally.Because load-side and storage capacitor side are non-DIRECT ENERGY transmission, thus the loss of compensator also can slightly increase.

Therefore, need the Second-harmonic compensation device finding a kind of new no electrolytic capacitor, make this compensator have good second harmonic current compensation effect, and compensation effect is not by the impact of operating mode.In order to reduce the impact of compensator on pfc converter or inverter overall efficiency, the loss of compensator also should be little as far as possible.

Summary of the invention

The object of the invention is to propose a kind of no electrolytic capacitor second harmonic current compensator adopting one circle control, this compensator can be used for the second harmonic current that absorbs in pfc converter output current or provide second harmonic current in input current of inverter.

Another object of the present invention is to provide a kind of modified model monocycle control method.

A kind of second harmonic current compensator, this compensator is made up of main power circuit and control circuit thereof, wherein, main power circuit comprises synchronous rectification Buck converter, input voltage sample circuit, output voltage sampling circuit and current sampling circuit, described synchronous rectification Buck converter by being responsible for, auxiliary pipe, filter inductance and storage capacitor form, it is characterized in that:

Control circuit comprises single cycle controller, first adder, second adder, divider, multiplier and voltage regulator; Described single cycle controller comprises integrator, inverter, comparator and trigger;

Input voltage sample circuit in main power circuit is connected with voltage regulator with the divider in control circuit respectively with output voltage sampling circuit, current sampling circuit in main power circuit is connected with the first adder in control circuit, and the drive singal of the supervisor that single cycle controller exports and auxiliary pipe is connected with the grid of auxiliary pipe with being responsible in synchronous rectification Buck converter respectively.

Further design of the present invention is:

First adder is by amplifier 1#, resistance R ₁, R ₂, R ₃and R ₄composition, wherein, R ₁one end be connected to the inverting input of amplifier 1#, other end ground connection; R ₂one end be connected to the in-phase input end of amplifier 1#, the other end is connected to the current sampling circuit in main power circuit; R ₃one end be connected to the in-phase input end of amplifier 1#, the other end is connected to sample-offset voltage i set in control circuit _sbais; R ₄be connected across between the inverting input of amplifier 1# and output; The output of first adder is one circle control variable, is connected to the input of integrator in single cycle controller.

Second adder by amplifier 4#, resistance R ₉, R ₁₀, R ₁₁, R ₁₂and R ₁₃composition, wherein, R ₉one end be connected to the in-phase input end of amplifier 4#, the other end is connected to the output of voltage regulator; R ₁₀one end be connected to the in-phase input end of amplifier 4#, the other end is connected to the required second harmonic current benchmark i absorbing or provide of the compensator set in control circuit _sHC; R ₁₁one end be connected to the in-phase input end of amplifier 4#, the other end is connected to the output of multiplier Mul2; R ₁₂one end be connected to the inverting input of amplifier 4#, other end ground connection; R ₁₃be connected across between the inverting input of amplifier 4# and output; The output of second adder is the benchmark of one circle control variable, is connected to the input of comparator in single cycle controller.

Divider by amplifier 2#, multiplier Mul1 and Mul3 and resistance R ₅and R ₆composition, wherein, an input of Mul1 is connected with the output of amplifier 2#, and another input is connected to the input voltage sample circuit in main power circuit, output and R ₆be connected in series, R ₆the other end be connected to the inverting input of amplifier 2#, R ₅one end be connected to the inverting input of amplifier 2#, the other end is connected to-1V benchmark, an input of Mul3 is connected to the output of amplifier 2#, another input is connected to the output voltage sampling circuit in main power circuit, output signal (duty ratio calculated in real time) accesses an input of multiplier Mul2, and another input of Mul2 is connected to the R in first adder ₃, output reference bias voltage i _rbaisbe connected to the resistance R of second adder ₁₁.

Voltage regulator by amplifier 3#, resistance R ₇and R ₈and electric capacity C ₁composition, wherein R ₇one end be connected to the inverting input of amplifier 3#, the other end is connected to the output voltage sampling circuit in main power circuit, resistance R ₈with electric capacity C ₁be connected to after series connection between the inverting input of amplifier 3# and output, the reference signal v of the output voltage set in the in-phase input end of amplifier 3# and control circuit _refbe connected, the output of voltage regulator is connected to the resistance R of second adder ₉.(the output voltage reference signal v set in control circuit _reffor the mean value reference signal of output voltage or the maximum reference signal of output voltage)

Storage capacitor adopts thin-film capacitor, and there is larger mains ripple at its two ends.The value V of storage capacitor _cswith the maximum V of storage capacitor voltage _{cs_max}, storage capacitor voltage pulsation size △ v _cs, the required second harmonic current absorbed or provide of compensator frequency f _2ndand required absorption or the pulsating power P that provides _sHCrelevant (f _2ndand P _sHCgiven in advance), and meet following relational expression:

${\mathrm{\Δv}}_{Cs}=V_{Cs\_max}-\sqrt{V_{Cs\_\max }^2-\frac{2P_{SHC}}{{\mathrm{\πf}}_{2nd}{C}_s}}$

Get and determine V _{cs_max}with △ v _cs, then by given f _2ndand P _sHCsubstitute into above formula, the value of storage capacitor can be obtained.Note, $V_{Cs\_max}^2>2P_{SHC}/{\mathrm{\πf}}_{2nd}{C}_s.$

The design of filter inductance is different from conventional design, except the pulsation size that need limit inductive current, also needs the follow-up control considering second harmonic current.The lower limit value L of filter inductance _sdetermined by filter inductance current pulsation size, its expression formula is

$L_s\≥\frac{1}{20{\mathrm{\%P}}_{SHL}{f}_s}{v}_{Cs}\left(t\right)\[v_{bus}-v_{Cs}\left(t\right)\]$

The upper limit value of filter inductance is determined by the follow-up control of second harmonic current, and its expression formula is

$L_s\≤min\{\frac{v_{bus}-v_{Cs}\left(t\right)}{i_{Ls\_SHC}^{\′}\left(t\right)},-\frac{v_{Cs}\left(t\right)}{i_{Ls\_SHC}^{\′}\left(t\right)}\}$

V in formula _busthe input voltage of compensator, v _csstorage capacitor electric capacity, f _sfor the switching frequency of compensator, P _sHCthe pulsating power absorbing needed for compensator or provide, i _{ls_SHC}the second harmonic current component in filter inductance, i' _{ls_SHC}t () is i _{ls_SHC}the derived function of (t).

Described synchronous rectification Buck converter works in CCM pattern, is made up of supervisor, auxiliary pipe, filter inductance and storage capacitor, and wherein, supervisor is connected to input voltage positive pole and the filter inductance L of compensator _sbetween, auxiliary pipe is connected between the source electrode of supervisor and the negative pole of input voltage, storage capacitor C _sbe connected to filter inductance L _sand between the negative pole of input voltage; Described input voltage sample circuit is parallel between the input both positive and negative polarity of compensator; Described output voltage sampling circuit is parallel to storage capacitor two ends; Described current sampling circuit is series in supervisor's current circuit.

What described voltage regulator adopted is proportional-integral controller, duopole type compensating network at two zero point or proportional-integral controller cascade bandreject filtering type compensating network.Its effect is by the output voltage sampled signal of compensator compared with output voltage benchmark, and the error signal comparing generation is amplified, and exports second adder to.Output voltage benchmark both can be the mean value benchmark of output voltage, can also be the maximum benchmark of output voltage.Compared to the mean value controlling output voltage, the maximum controlling output voltage can improve the DIRECT ENERGY of input and output side when compensator underloading works and transmit proportion, the underloading loss of compensator can be reduced, but now need to add peak detection circuit in control circuit.This peak detection circuit comprises detection resistance R _p, Detection capacitance C _pwith diode D _p, wherein, R _pand C _pbe connected in parallel, its one end is connected to resistance R ₇, the other end is connected to ground; Diode D _panode be connected to output voltage sampling circuit in main power circuit, negative electrode is connected to resistance R ₇.

Be applicable to the modified model monocycle control method of second harmonic current compensator, comprise the steps:

The rising edge of clock in a, response single cycle controller, the supervisor in synchronous rectification Buck converter is open-minded, and auxiliary pipe turns off;

Current sampling circuit sampling supervisor current signal in b, main power circuit, and configure a constant sample-offset voltage, make sum of the two perseverance in full-load range be greater than 0, and using sum of the two as one circle control variable;

The duty ratio of the real-time calculation compensation device supervisor of c, divider, is multiplied it with above-mentioned constant sample-offset voltage by multiplier, obtains a reference offset voltage;

D, utilize second adder the output of the second harmonic current benchmark absorbed needed for compensator or provide, voltage regulator and described reference offset voltage to be added, obtain the benchmark of one circle control variable;

Integrator in e, single cycle controller carries out integration to described one circle control variable, when integrated value is equal with the benchmark of described one circle control variable, the output state flip of comparator in single cycle controller, trigger reset, the supervisor of synchronous rectification Buck converter turns off, auxiliary pipe is open-minded, until next clock arrives in single cycle controller, compensator repeats above-mentioned steps work.

Because the integrated value of above-mentioned sample-offset voltage in a switch periods is equal with reference offset voltage, and the output of voltage regulator is approximately 0, therefore the integrated value of supervisor's electric current in a switch periods, be namely responsible for the second harmonic current that the mean value of electric current in a switch periods equals to absorb needed for compensator or provide.Like this, adopt modified model monocycle control method proposed by the invention, compensator can be made to have good second harmonic current compensation effect.

The second harmonic current compensator of the present invention's design, can be connected in parallel on DC load side, direct current input source side or intermediate dc bus, be used for the second harmonic current that absorbs in pfc converter output current or second harmonic current in input current of inverter is provided.

Compared with prior art, its main feature is as follows in the present invention:

1. compensator proposed by the invention works in CCM pattern, in switching tube the peak value of electric current and effective value lower, the conduction loss of compensator is less;

2. the second harmonic current compensator of the present invention's design adopts no electrolytic capacitor design, and this compensator has good second harmonic current compensation effect, and operating mode is very little on compensation effect impact.

3. modified model monocycle control method proposed by the invention can overcome existing basic monocycle control method and cause because not restraining inductive current disturbance when compensator works in discharge mode compensator cannot the defect of steady operation, and compensator all reliablely and stablely can be worked under charge mode and discharge mode.

Accompanying drawing explanation

Accompanying drawing 1 is the schematic diagram of synchronous rectification Buck converter in the present invention.

Accompanying drawing 2 is divided into accompanying drawing 2-1,2-2,2-3 and 2-4, is the equivalent circuit diagram of synchronous rectification Buck converter under different working modes.

Accompanying drawing 2-1 is that synchronous rectification Buck converter works in charge mode, equivalent circuit diagram when supervisor opens, auxiliary pipe turns off;

Accompanying drawing 2-2 is that synchronous rectification Buck converter works in charge mode, equivalent circuit diagram when supervisor turns off, auxiliary pipe is opened;

Accompanying drawing 2-3 is that synchronous rectification Buck converter works in discharge mode, equivalent circuit diagram when supervisor opens, auxiliary pipe turns off;

Accompanying drawing 2-4 is that synchronous rectification Buck converter works in discharge mode, equivalent circuit diagram when supervisor turns off, auxiliary pipe is opened.

Solid line in accompanying drawing 2-1,2-2,2-3 and 2-4 has electric current to flow through under representing this operation mode, and under dotted line represents this operation mode, no current flows through.

Accompanying drawing 3 is divided into accompanying drawing 3-1,3-2, is when adopting basic monocycle control method to control, the key operation waveforms of second harmonic current compensator under different working modes.

Accompanying drawing 3-1 is when adopting basic monocycle control method to control, the key operation waveforms of second harmonic current compensator under charge mode;

Accompanying drawing 3-2 is when adopting basic monocycle control method to control, the key operation waveforms of second harmonic current compensator under discharge mode.

Solid line in accompanying drawing 3-1,3-2 is the steady operation waveform of compensator, and dotted line is the work wave add disturbance in inductive current after.

Accompanying drawing 4 is divided into accompanying drawing 4-1,4-2, is when adopting modified model monocycle control method proposed by the invention to control, the key operation waveforms of second harmonic current compensator under different working modes.

Accompanying drawing 4-1 is when adopting modified model monocycle control method to control, the key operation waveforms of second harmonic current compensator under charge mode;

Accompanying drawing 4-2 is when adopting modified model monocycle control method to control, the key operation waveforms of second harmonic current compensator under discharge mode.

Solid line in accompanying drawing 4-1,4-2 is the steady operation waveform of compensator, and dotted line is the work wave add disturbance in inductive current after.

Accompanying drawing 5 is schematic diagrams of control circuit in second harmonic current compensator, and wherein the output voltage of storage capacitor adopts mean value to control.

When accompanying drawing 6 is output voltage employing mean value control, storage capacitor voltage work wave under different loads.

When accompanying drawing 7 is output voltage employing Maximum constraints, storage capacitor voltage work wave under different loads.

Accompanying drawing 8 is another kind of schematic diagrams of control circuit in this second harmonic current compensator, and wherein the output voltage of storage capacitor adopts Maximum constraint.

Accompanying drawing 9 is circuit theory diagrams of design example.

Accompanying drawing 10-1,10-2,10-3 and 10-4 are simulation waveforms during second harmonic current compensator steady operation, and what wherein output voltage adopted is that mean value controls.

Accompanying drawing 10-1 be compensator when work in 10% year, second harmonic current benchmark i _sHC, compensator actual absorption or the second harmonic current i that provides _{qa1_SHC}, margin of error err and storage capacitor voltage v _cssimulation waveform;

Accompanying drawing 10-2 be compensator when work in 10% year, the simulation waveform of reflection one circle control circuit working feature;

Accompanying drawing 10-3 be compensator when fully loaded work, second harmonic current benchmark i _sHC, compensator actual absorption or the second harmonic current i that provides _{qa1_SHC}, margin of error err and storage capacitor voltage v _cssimulation waveform;

Accompanying drawing 10-4 be compensator when fully loaded work, the simulation waveform of reflection one circle control circuit working feature.

Accompanying drawing 11-1,11-2,11-3 and 11-4 are simulation waveforms during second harmonic current compensator steady operation, and what wherein output voltage adopted is Maximum constraint.

Accompanying drawing 11-1 be compensator when work in 10% year, second harmonic current benchmark i _sHC, compensator actual absorption or the second harmonic current i that provides _{qa1_SHC}, margin of error err and storage capacitor voltage v _cssimulation waveform;

Accompanying drawing 11-2 be compensator when work in 10% year, the simulation waveform of reflection one circle control circuit working feature;

Accompanying drawing 11-3 be compensator when fully loaded work, second harmonic current benchmark i _sHC, compensator actual absorption or the second harmonic current i that provides _{qa1_SHC}, margin of error err and storage capacitor voltage v _cssimulation waveform;

Accompanying drawing 11-4 be compensator when fully loaded work, the simulation waveform of reflection one circle control circuit working feature.

Accompanying drawing 12-1,12-2,12-3 and 12-4 are the application examples of second harmonic current compensator.

Accompanying drawing 12-1 is the direct current input side that compensator is parallel to single stage type single-phase inverter;

Accompanying drawing 12-2 is the intermediate dc bus two ends that compensator is parallel to two-stage type single-phase inverter;

Accompanying drawing 12-3 is the DC output side that compensator is parallel to single stage type Single-phase PFC converter;

Accompanying drawing 12-4 is the intermediate dc bus two ends that compensator is parallel to two-stage type Single-phase PFC converter.

Primary symbols title in above-mentioned accompanying drawing: Q _a1the supervisor of compensator, Q _a2the auxiliary pipe of compensator, L _sfor filter inductance, C _sfor storage capacitor, v _busand v _csthe input and output voltage of compensator respectively, v _{cs_min}, v _{cs_ave}and v _{cs_max}the minimum value of output voltage, mean value and maximum respectively, △ v _csthe pulsation size of storage capacitor voltage, v _{bus_fb}and v _{cs_fb}the sampled signal of input and output voltage respectively, i _qa1and i _qa2the electric current of supervisor and auxiliary pipe respectively, i _{qa1_fb}the sampled signal of supervisor's electric current, i _{qa1_SHC}be the second harmonic current component in supervisor's electric current, clk is the clock signal in single cycle controller, i _intfor the output voltage of inverter in single cycle controller, i _sbaisand i _rbaisbe respectively sample-offset voltage and reference offset voltage, i _reffor the benchmark of one circle control variable in existing basic monocycle control method, i' _reffor the benchmark of one circle control variable in the modified model monocycle control method that the present invention proposes, v _{ref_ave}and v _{ref_max}be respectively mean value benchmark and the maximum benchmark of output voltage, i _sHCthe second harmonic current benchmark absorbing needed for compensator or provide, i _erri _sHCand i _{qa1_SHC}residual quantity, R ₁, R ₂, R ₃and R ₄the resistance of composition adder (1), R ₅and R ₆the resistance of composition divider, R ₇, R ₈the resistance of composition voltage regulator, C ₁the electric capacity of composition voltage regulator, R ₉, R ₁₀, R ₁₁, R ₁₂and R ₁₃the resistance of composition adder (2), R ₁₄and R ₁₅the resistance of composition inverter, R _intthe input resistance of integrator, C _intthe feedback capacity of integrator, R _ppeakvalue's checking resistance, C _ppeakvalue's checking electric capacity, R _sv1and R _sv2input voltage sampling resistor, R _sv3and R _sv4output voltage sampling resistor, R _siit is the sampling resistor of supervisor's electric current.

Embodiment

Embodiment one:

Fig. 1 illustrates the main power circuit topology of no electrolytic capacitor second harmonic current compensator proposed by the invention.It adopts the Buck converter of synchronous rectification, by switching tube Q _a1, Q _a2, filter inductance L _swith storage capacitor C _scomposition.Wherein, switching tube Q _a1be supervisor, be connected to input voltage positive pole and the filter inductance L of compensator _sbetween; Switching tube Q _a2be auxiliary pipe, be connected to Q _a1source electrode and the negative pole of input voltage between; Storage capacitor C _sbe connected to filter inductance L _swith between the negative pole of input voltage, its electric capacity kind is long-life thin-film capacitor.According to the Changing Pattern of storage capacitor both end voltage, the mode of operation of compensator can be divided into charge mode and discharge mode.When compensator works in charge mode, the voltage at storage capacitor two ends raises; When compensator works in discharge mode, the voltage drop at storage capacitor two ends.

When accompanying drawing 2-1 and 2-2 gives charge mode work, the equivalent circuit diagram of compensator under different operating mode.As supervisor Q _a1open-minded, auxiliary pipe Q _a2during shutoff, i _qa1>0, inductive current forward linearly increases; As supervisor Q _a1turn off, auxiliary pipe Q _a2during conducting, inductive current is by auxiliary pipe Q _a2afterflow, forward linearly reduces.

When accompanying drawing 2-3 and 2-4 gives discharge mode work, the equivalent circuit diagram of compensator under different operating mode.As supervisor Q _a1open-minded, auxiliary pipe Q _a2during shutoff, i _qa1<0, inductive current negative sense linearly reduces; As supervisor Q _a1turn off, auxiliary pipe Q _a2during conducting, storage capacitor is to inductance L _scharging, inductive current negative sense linearly increases.

Embodiment two: (existing control method compares with control method of the present invention)

Fig. 3-1,3-2 gives key operation waveforms when compensator adopts existing basic monocycle control method, and in Fig. 3-1,3-2, solid line is the work wave under steady-state working condition, and dotted line is in inductive current, add work wave after disturbance.As shown in Figure 3, during charge mode (accompanying drawing 3-1), compensator, can steady operation to inductive current disturbance convergence.This is because when inductive current forward increases (or reduction), i _qa1forward increases (or reduction) thereupon, i _{qa1_fb}integrated value i _int(or delayed) will be shifted to an earlier date and reach benchmark i _ref, make to be responsible for Q _a1duty ratio reduce (or increase), auxiliary pipe Q _a2duty ratio increase (or reduce).Because inductive current is by auxiliary pipe Q _a2time of afterflow increase (or reduce), thus inductive current will reduce (or increase).After several switch periods, inductive current will be restored to stable state.And during discharge mode (accompanying drawing 3-2), compensator is dispersed inductive current disturbance, can not steady operation.This is because when inductive current negative sense increases (or reduction), i _qa1negative sense increases (or reduction) thereupon, i _{qa1_fb}integrated value i _int(or delayed) will be shifted to an earlier date and reach benchmark i _ref, make to be responsible for Q _a1duty ratio reduce (or increase), auxiliary pipe Q _a2duty ratio increase (or reduce), cause storage capacitor to inductance L _scharging interval increase (or reduce), thus inductive current is increased (or reduction) further, form a positive feedback process, until storage capacitor voltage drop is to 0, compensator reenters charge mode.

In order to enable compensator steady operation when discharge mode, the present invention proposes follow-on monocycle control method, this method is not directly to be responsible for the sampled signal i of electric current _{qa1_fb}as one circle control variable, but be responsible for the sampled signal i of electric current _{qa1_fb}middle superposition sample-offset voltage i _sbaisafter, then with (i _{qa1_fb}+ i _sbais) as one circle control variable.Note, sample-offset voltage i _sbais(i should be made _{qa1_fb}+ i _sbais) in full-load range, perseverance is greater than 0.Like this, when compensator works in discharge mode, if inductive current negative sense increases (or reduction), then (i _{qa1_fb}+ i _sbais) forward is reduced (or increase), make to be responsible for Q _a1duty ratio increase (or reduce), auxiliary pipe Q _a2duty ratio reduce (or increase), cause storage capacitor to inductance L _sthe time of charging reduces (or increase), thus inductive current is reduced (or increasing).After several switch periods, inductive current will be restored to stable state.

Accompanying drawing 4-1,4-2 give key operation waveforms when compensator adopts modified model monocycle control method of the present invention, and in figure, solid line is the work wave under steady-state working condition, and dotted line is in inductive current, add work wave after disturbance.As shown in Figure 4, adopt modified model monocycle control method proposed by the invention, compensator all can steady operation under charge mode and discharge mode.As can be seen here, the creative and practical value of the modified model monocycle control method proposed.

With reference to the accompanying drawings 3 and accompanying drawing 4, i _{qa1_fb}(i _{qa1_fb}+ i _sbais) integrated value in a switch periods should meet respectively

$\frac{1}{T_s}{\&Integral;}_0^{d_y{T}_s}{i}_{Qa1\_fb}=i_{ref}---\left(1\right)$

$\frac{1}{T_s}{\&Integral;}_0^{d_y{T}_s}(i_{Qa1\_fb}+i_{sbais})=i_{ref}^{\&prime;}---\left(2\right)$

Wherein, i _refthe second harmonic current i absorbing needed for compensator or provide _sHCwith the output v of voltage regulator _gvsum.Due to v during steady operation _e≈ 0, thus has

i _ref＝i _SHC+v _e≈i _SHC(3)

Can be obtained by formula (1) ~ (3)

$\frac{1}{T_s}{\&Integral;}_0^{d_y{T}_s}{i}_{Qa1\_fb}\&ap;i_{SHC}---\left(4\right)$

$i_{ref}^{\&prime;}=i_{ref}+\frac{1}{T_s}{\&Integral;}_0^{d_y{T}_s}{i}_{sbais}=i_{ref}+d_y{i}_{sbais}=i_{ref}+i_{rbais}---\left(5\right)$

From formula (4), adopt follow-on monocycle control method, the mean value of compensator supervisor's electric current in a switch periods equals the required second harmonic current absorbing or provide, and thus compensator has good second harmonic current compensation effect.

From formula (5), compared to basic monocycle control method, the reference offset voltage i needing superposition one and compensator duty ratio relevant with sample-offset voltage in the one circle control variable benchmark of modified model monocycle control method _rbais.

For the synchronous rectifier Buck converter shown in accompanying drawing 1, duty ratio d _yfor

$d_y=\frac{v_{Cs}}{v_{bus}}---\left(6\right)$

Therefore reference offset voltage i _rbaisfor

$i_{rbais}=\frac{v_{Cs}}{v_{bus}}{i}_{sbais}---\left(7\right)$

Embodiment three:

Figure 5 provides the control circuit schematic diagram of modified model monocycle control method of the present invention.From accompanying drawing 5, this control circuit comprises single cycle controller, first adder, second adder, divider, multiplier and voltage regulator, and concrete connected mode is: first adder by amplifier 1#, resistance R ₁, R ₂, R ₃and R ₄composition, wherein, R ₁one end be connected to the inverting input of amplifier 1#, other end ground connection; R ₂one end be connected to the in-phase input end of amplifier 1#, the other end is connected to the current sampling circuit in main power circuit; R ₃one end be connected to the in-phase input end of amplifier 1#, the other end is connected to sample-offset voltage i _sbais; R ₄be connected across between the inverting input of amplifier 1# and output; The output of first adder is one circle control variable, is connected to the input of integrator in single cycle controller; Divider by amplifier 2#, multiplier Mul1 and Mul3 and resistance R ₅and R ₆composition, wherein, an input of Mul1 is connected with the output of amplifier 2#, and another input is connected to the input voltage sample circuit in main power circuit, output and R ₆be connected in series, R ₆the other end be connected to the inverting input of amplifier 2#, R ₅one end be connected to the inverting input of amplifier 2#, other end Lian Jie Zhi – 1V benchmark, an input of Mul3 is connected to the output of amplifier 2#, another input is connected to the output voltage sampling circuit in main power circuit, the duty ratio that output calculates in real time is to an input of multiplier Mul2, and another input of Mul2 is connected to the R in first adder ₃, output reference bias voltage i _rbaisbe connected to R ₁₁; Voltage regulator by amplifier 3#, resistance R ₇and R ₈and electric capacity C ₁composition, wherein R ₇one end be connected to the inverting input of amplifier 3#, the other end is connected to the output voltage sampling circuit in main power circuit, resistance R ₈with electric capacity C ₁be connected to after series connection between the inverting input of amplifier 3# and output, the in-phase input end of amplifier 3# and the benchmark v of output voltage _refbe connected, the output of voltage regulator is connected to R ₉; Second adder by amplifier 4#, resistance R ₉, R ₁₀, R ₁₁, R ₁₂and R ₁₃composition, wherein, R ₉one end be connected to the in-phase input end of amplifier 4#, the other end is connected to the output of voltage regulator; R ₁₀one end be connected to the in-phase input end of amplifier 4#, the other end is connected to the required second harmonic current benchmark i absorbing or provide of compensator _sHC; R ₁₁one end be connected to the in-phase input end of amplifier 4#, the other end is connected to the output of multiplier Mul2; R ₁₂one end be connected to the inverting input of amplifier 4#, other end ground connection; R ₁₃be connected across between the inverting input of amplifier 4# and output; The output of second adder is the benchmark of one circle control variable, is connected to the input of comparator in single cycle controller; Single cycle controller exports the drive singal of synchronous rectification Buck converter supervisor and auxiliary pipe, is connected to the grid of supervisor and auxiliary pipe, and control is responsible for and the opening and shutoff of auxiliary pipe.

In figure 5, the voltage reference being connected to voltage regulator in-phase input end is the mean value benchmark of output voltage, and therefore, by closed-loop adjustment, the mean value of compensator output voltage remains unchanged in full-load range, as shown in Figure 6.But it should be noted that the maximum of storage capacitor voltage must lower than the input voltage of compensator in order to ensure that synchronous rectification Buck converter normally works.And when output voltage average value one timing, along with power output raises, storage capacitor mains ripple becomes large, the maximum of output voltage uprises.When fully loaded work, the maximum of compensator output voltage reaches the highest, and thus, the mean value of compensator output voltage need design according to full-loading condition.But on the other hand, under identical output voltage average value condition, during underloading work, storage capacitor mains ripple is less, the constrained input voltage phase difference of compensator is comparatively large, make the DIRECT ENERGY of input and output side transmit proportion and decline, and then when causing compensator underloading to work, loss is larger.

If directly control the maximum of output voltage, then the mean value of compensator output voltage can reduce and self adaptation raising with power output, the DIRECT ENERGY that can improve compensator input and output side during underloading work like this transmits proportion, thus reduces the loss of compensator.

Embodiment four:

When accompanying drawing 7 gives output voltage employing Maximum constraint, storage capacitor voltage work wave under different loads, storage capacitor voltage waveform when figure chain lines is underloading work, storage capacitor voltage waveform when solid line is fully loaded work.From accompanying drawing 7, in full-load range, the maximum of output voltage remains unchanged, and the mean value of output voltage raises along with load reduction.

When fig. 8 provides employing output voltage Maximum constraint, the control circuit schematic diagram of modified model monocycle control method.Compared with accompanying drawing 5, its main distinction is that this control circuit also comprises a peak detection circuit.This circuit comprises diode D _p, detect resistance R _pwith Detection capacitance C _p, its input is connected to the output voltage sampling circuit in main power circuit, and output is connected to the resistance R in voltage regulator ₇, in accompanying drawing 8, the connected mode of control circuit each several part is identical with accompanying drawing 5.

Embodiment five:

Figure 9 shows the circuit theory diagrams of design example of the present invention, in figure, main power circuit also comprises by R compared with accompanying drawing 1 _sv1and R _sv2the input voltage sample circuit of composition, by R _sv3and R _sv4the output voltage sampling circuit of composition and the sampling resistor R of supervisor's electric current _si, wherein, series resistance R _sv1and R _sv2be connected to the input of synchronous rectification Buck converter, series resistance R _sv3and R _sv4be connected to the output of synchronous rectification Buck converter, resistance R _sibe series between compensator input negative pole and auxiliary pipe source electrode.The input voltage sampled signal that input voltage sample circuit obtains is connected to the input of Mul1 in divider, and the output voltage sampled signal that output voltage sampling circuit obtains is connected to input and the diode D of Mul3 in divider respectively _panode, supervisor current sampling resistor R _sithe supervisor's current sampling signal obtained is connected to R in first adder _2;in figure, the connected mode of control circuit is identical with accompanying drawing 8.

Storage capacitor C in accompanying drawing 9 _smethod for designing as follows:

Storage capacitor C _sadopt thin-film capacitor, there is larger capacitance voltage pulsation at its two ends.C _scapacitance and the maximum V of storage capacitor voltage _{cs_max}, storage capacitor voltage pulsation size △ v _cs, second harmonic current frequency f _2ndand required absorption or the pulsating power P that provides _sHCbetween (f _2ndand P _sHCgiven in advance) meet following relation

${\mathrm{\&Delta;v}}_{Cs}=V_{Cs\_max}-\sqrt{V_{Cs\_\max }^2-\frac{2P_{SHC}}{{\mathrm{\&pi;f}}_{2nd}{C}_s}}---\left(8\right)$

Get maximum and the pulsation size of storage capacitor voltage when being surely fully loaded with work, storage capacitor C can be calculated according to formula (8) _scapacitance.Note,

Filter inductance L in accompanying drawing 9 _smethod for designing as follows:

Filter inductance L _sin second harmonic current component i _{ls_SHC}and i _sHCbetween meet:

$i_{Ls\_SHC}\left(t\right)=\frac{v_{bus}}{v_{Cs}\left(t\right)}{i}_{SHC}\left(t\right)---\left(9\right)$

I in formula _sHC(t) and v _cst the expression formula of () is respectively

$i_{SHC}\left(t\right)=-\frac{P_{SHC}}{v_{bus}}\cos \left(2{\mathrm{\&pi;f}}_{2nd}t\right)---\left(10\right)$

$v_{Cs}\left(t\right)=\sqrt{V_{Cs\_\max }^2-\frac{P_{2nd}}{{\mathrm{\&pi;f}}_{2nd}{C}_s}(1+\sin (2{\mathrm{\&pi;f}}_{2nd}t\left)\right)}---\left(11\right)$

Filter inductance L _svalue lower limit be:

$L_s\&GreaterEqual;\frac{1}{20{\mathrm{\%P}}_{SHL}{f}_s}{v}_{Cs}\left(t\right)\&lsqb;v_{bus}-v_{Cs}\left(t\right)\&rsqb;---\left(12\right)$

Filter inductance L _sthe value upper limit be:

$L_s\&le;min\{\frac{v_{bus}-v_{Cs}\left(t\right)}{i_{Ls\_SHC}^{\&prime;}\left(t\right)},-\frac{v_{Cs}\left(t\right)}{i_{Ls\_SHC}^{\&prime;}\left(t\right)}\}---\left(13\right)$

I' in formula _{ls_SHC}t () is i _{ls_SHC}t the derived function of (), can be obtained by formula (9) and formula (10), i _{ls_SHC}t the expression formula of () is

$i_{Ls\_SHC}\left(t\right)=-\frac{P_{SHC}\cos \left(2{\mathrm{\&pi;f}}_{2nd}t\right)}{V_{Cs\_\max }^2-\frac{P_{2nd}}{{\mathrm{\&pi;f}}_{2nd}{C}_s}(1+\sin (2{\mathrm{\&pi;f}}_{2nd}t\left)\right)}---\left(14\right)$

The input resistance R of integrator in accompanying drawing 9 _intwith feedback capacity C _intmethod for designing as follows:

R _intand C _intproduct should meet:

$R_{in}{C}_{in}=\frac{1}{f_s}---\left(15\right)$

F in formula _sfor the switching frequency of compensator.Generally get C _int=100pF, like this, gets and determines f _sr can be determined _intvalue.

In accompanying drawing 9, the design principle of voltage regulator is as follows:

Voltage regulator should frequency f corresponding to second harmonic current _2ndplace has alap gain, with the second harmonic current component in filtering output voltage sampled signal, thus ensures that compensator has good second harmonic current inhibition.General desirable C ₁=1 μ F, R ₇=10k Ω, R ₈=1k Ω.

In accompanying drawing 9, the gain of adder (1) is 1, gets R during design ₁=R ₂=R ₃=R ₄=R, in formula, R generally gets 1k ~ 10k.

In accompanying drawing 9, the gain of divider is 1, gets R during design ₅=R ₆=R.

In accompanying drawing 9, the gain of adder (2) is 1, gets R during design ₉=R ₁₀=R ₁₁=R ₁₂=R, R ₁₃=2R.

In accompanying drawing 9, the gain of inverter is 1, gets R during design ₁₄=R ₁₅=R.

Detection resistance R in accompanying drawing 9 in peak detection circuit _pwith Detection capacitance C _pdesign principle be: R _pc _p> (3 ~ 5)/f _2nd, f _2ndfor the frequency of second harmonic current.

The major parameter of the instantiation given by accompanying drawing 9 is as follows:

● input voltage v _bus=400V

● the maximum V of output voltage _{cs_max}=380V

● filter inductance L _s=2mH

● storage capacitor C _s=100 μ F

● the switching frequency f of second harmonic current compensator _s=100kHz

● required absorption or the pulsating power P provided _sHC=1kVA

● the frequency f of second harmonic current _2nd=100Hz

● the circuit parameter of composition adder (1) is: R ₁=R ₂=R ₃=R ₄=1k Ω

● unless the circuit parameter of composition device is: R ₅=R ₆=1k Ω

● the circuit parameter of composition voltage regulator is: R ₇=10k Ω, R ₈=1k Ω, C ₁=1 μ F

● the circuit parameter of composition adder (2) is: R ₉=R ₁₀=R ₁₁=R ₁₂=1k Ω, R ₁₃=2k Ω

● the circuit parameter of composition integrator is: R _int=100k Ω, C _int=100pF

● the circuit parameter of composition inverter is: R ₁₄=R ₁₅=1k Ω

The circuit parameter of composition peak detector is: R _p=51k Ω, C _p=10 μ F

Test case one:

Accompanying drawing 10 gives second harmonic current design of Compensator example (respective figure 9) of the present invention

Steady operation time simulation waveform, wherein output voltage adopt be mean value control.Accompanying drawing 10-1 and accompanying drawing 10-2 is the simulation waveform of compensator when work in 10% year, and accompanying drawing 10-3 and 10-4 is the simulation waveform of compensator when fully loaded work.As can be seen from accompanying drawing 10-1 and 10-3, when output voltage adopts mean value to control, the mean value of storage capacitor voltage does not change with load variations, and the input current of compensator can follow the tracks of the required second harmonic current absorbing or provide well.As can be seen from accompanying drawing 10-2 and accompanying drawing 10-4, compensator all can steady operation under charge mode and discharge mode, shows that the follow-on monocycle control method of the present invention has feasibility and validity thus.

Test case two:

Accompanying drawing 11 gives the simulation waveform during steady operation of second harmonic current design of Compensator example (respective figure 9) of the present invention, and what wherein output voltage adopted is Maximum constraint.Accompanying drawing 11-1 and accompanying drawing 11-2 is the simulation waveform of compensator when work in 10% year, and accompanying drawing 11-3 and 11-4 is the simulation waveform of compensator when fully loaded work.As can be seen from accompanying drawing 11-1 and 11-3, when output voltage adopts Maximum constraint, the maximum of storage capacitor voltage does not change with load variations, and the input current of compensator can follow the tracks of the required second harmonic current absorbing or provide well.As can be seen from accompanying drawing 11-2 and accompanying drawing 11-4 equally, compensator all can steady operation under charge mode and discharge mode, shows that follow-on monocycle control method has feasibility and validity thus.

Application example:

Accompanying drawing 12 gives the application example of second harmonic current compensator proposed by the invention.It both can be parallel to the direct current input side (accompanying drawing 12-1) of single stage type single-phase inverter or the intermediate dc bus two ends (accompanying drawing 12-2) of two-stage type single-phase inverter, was used to provide the second harmonic current in input current of inverter; The DC output side (accompanying drawing 12-3) of single stage type Single-phase PFC converter or the intermediate dc bus two ends (accompanying drawing 12-4) of two-stage type Single-phase PFC converter can also be parallel to, be used for absorbing the second harmonic current in pfc converter output current.

As seen from the above description, the no electrolytic capacitor second harmonic current compensator tool that the present invention proposes has the following advantages:

1. no electrolytic capacitor in compensator;

2. compensator works in CCM pattern, in switching tube the peak value of electric current and effective value lower, the conduction loss of compensator is less;

3. compensator adopts follow-on monocycle control method to control, overcome basic monocycle control method and cause the defect of compensator instability because not restraining inductive current disturbance at discharge mode, can ensure that compensator all reliablely and stablely works under charge mode and discharge mode;

Compensator has good second harmonic current compensation effect, and operating mode is very little on compensation effect impact.

Claims (9)

1. a second harmonic current compensator, this compensator is made up of main power circuit and control circuit thereof, wherein, main power circuit comprises synchronous rectification Buck converter, input voltage sample circuit, output voltage sampling circuit and current sampling circuit, described synchronous rectification Buck converter by being responsible for, auxiliary pipe, filter inductance and storage capacitor form, it is characterized in that:

Control circuit comprises single cycle controller, first adder, second adder, divider, multiplier and voltage regulator; Described single cycle controller comprises integrator, inverter, comparator and trigger;

Input voltage sample circuit in main power circuit is connected with voltage regulator with the divider in control circuit respectively with output voltage sampling circuit, current sampling circuit in main power circuit is connected with the first adder in control circuit, and the drive singal of the supervisor that single cycle controller exports and auxiliary pipe is connected with the grid of auxiliary pipe with being responsible in synchronous rectification Buck converter respectively.

2. second harmonic current compensator according to claim 1, is characterized in that:

First adder is by amplifier 1#, resistance R ₁, R ₂, R ₃and R ₄composition, wherein, R ₁one end be connected to the inverting input of amplifier 1#, other end ground connection; R ₂one end be connected to the in-phase input end of amplifier 1#, the other end is connected to the current sampling circuit in main power circuit; R ₃one end be connected to the in-phase input end of amplifier 1#, the other end is connected to sample-offset voltage i set in control circuit _sbais; R ₄be connected across between the inverting input of amplifier 1# and output; The output of first adder is one circle control variable, is connected to the input of integrator in single cycle controller.

3. second harmonic current compensator according to claim 1 or 2, is characterized in that:

Second adder by amplifier 4#, resistance R ₉, R ₁₀, R ₁₁, R ₁₂and R ₁₃composition, wherein, R ₉one end be connected to the in-phase input end of amplifier 4#, the other end is connected to the output of voltage regulator; R ₁₀one end be connected to the in-phase input end of amplifier 4#, the other end is connected to the required second harmonic current benchmark i absorbing or provide of the compensator set in control circuit _sHC; R ₁₁one end be connected to the in-phase input end of amplifier 4#, the other end is connected to the output of multiplier Mul2; R ₁₂one end be connected to the inverting input of amplifier 4#, other end ground connection; R ₁₃be connected across between the inverting input of amplifier 4# and output; The output of second adder is the benchmark of one circle control variable, is connected to the input of comparator in single cycle controller.

4. second harmonic current compensator according to claim 3, is characterized in that: divider by amplifier 2#, multiplier Mul1 and Mul3 and resistance R ₅and R ₆composition, wherein, an input of Mul1 is connected with the output of amplifier 2#, and another input is connected to the input voltage sample circuit in main power circuit, output and R ₆be connected in series, R ₆the other end be connected to the inverting input of amplifier 2#, R ₅one end be connected to the inverting input of amplifier 2#, the other end is connected to-1V benchmark, an input of Mul3 is connected to the output of amplifier 2#, another input is connected to the output voltage sampling circuit in main power circuit, an input of output signal access multiplier Mul2, another input of Mul2 is connected to the R in first adder ₃, output reference bias voltage i _rbaisbe connected to the resistance R of second adder ₁₁.

5. second harmonic current compensator according to claim 3, is characterized in that:

Voltage regulator by amplifier 3#, resistance R ₇and R ₈and electric capacity C ₁composition, wherein R ₇one end be connected to the inverting input of amplifier 3#, the other end is connected to the output voltage sampling circuit in main power circuit, resistance R ₈with electric capacity C ₁be connected to after series connection between the inverting input of amplifier 3# and output, the reference signal v of the output voltage set in the in-phase input end of amplifier 3# and control circuit _refbe connected, the output of voltage regulator is connected to the resistance R of second adder ₉; The output voltage reference signal v set in control circuit _reffor the mean value reference signal of output voltage or the maximum reference signal of output voltage, when maximum reference signal for output voltage, need to add peak detection circuit in control circuit, this peak detection circuit comprises and detects resistance R _p, Detection capacitance C _pwith diode D _p, wherein, R _pand C _pbe connected in parallel, its one end is connected to resistance R ₇, the other end is connected to ground; Diode D _panode be connected to output voltage sampling circuit in main power circuit, negative electrode is connected to resistance R ₇.

6. second harmonic current compensator according to claim 1, is characterized in that:

Storage capacitor adopts thin-film capacitor, the value V of storage capacitor _cswith the maximum V of storage capacitor voltage _{cs_max}, storage capacitor voltage pulsation size △ v _cs, the required second harmonic current absorbed or provide of compensator frequency f _2ndand required absorption or the pulsating power P that provides _sHCrelevant, and meet following relational expression:

Get and determine V _{cs_max}with △ v _cs, then by given f _2ndand P _sHCsubstitute into above formula, the value of storage capacitor can be obtained,

7. second harmonic current compensator according to claim 6, is characterized in that:

The lower limit value L of filter inductance _sdetermined by filter inductance current pulsation size, its expression formula is

The upper limit value of filter inductance is determined by the follow-up control of second harmonic current, and its expression formula is

V in formula _busthe input voltage of compensator, v _csstorage capacitor electric capacity, f _sfor the switching frequency of compensator, P _sHCthe pulsating power absorbing needed for compensator or provide, i _{ls_SHC}the second harmonic current component in filter inductance, i' _{ls_SHC}t () is i _{ls_SHC}the derived function of (t).

8. second harmonic current compensator according to claim 1, it is characterized in that: described synchronous rectification Buck converter works in CCM pattern, be made up of supervisor, auxiliary pipe, filter inductance and storage capacitor, wherein, supervisor is connected to input voltage positive pole and the filter inductance L of compensator _sbetween, auxiliary pipe is connected between the source electrode of supervisor and the negative pole of input voltage, storage capacitor C _sbe connected to filter inductance L _sand between the negative pole of input voltage; Described input voltage sample circuit is parallel between the input both positive and negative polarity of compensator; Described output voltage sampling circuit is parallel to storage capacitor two ends; Described current sampling circuit is series in supervisor's current circuit.

9. second harmonic current compensator according to claim 1, is characterized in that: what described voltage regulator adopted is proportional-integral controller, can also adopt the compensating network of duopole type at two zero point or proportional-integral controller cascade bandreject filtering type.