CN204835502U - Converter main relay fail safe circuit - Google Patents

Converter main relay fail safe circuit Download PDF

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Publication number
CN204835502U
CN204835502U CN201520527512.3U CN201520527512U CN204835502U CN 204835502 U CN204835502 U CN 204835502U CN 201520527512 U CN201520527512 U CN 201520527512U CN 204835502 U CN204835502 U CN 204835502U
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pin
optocoupler
resistor
connector
diode
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CN201520527512.3U
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裘正宇
厉茜
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Taian Technology (Wuxi) Co Ltd
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Taian Technology (Wuxi) Co Ltd
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Abstract

本实用新型公开了一种变频器主继电器失效保护电路,包括连接器和光耦,连接器设置在启动电阻两端,连接器的1脚串联第一电阻后连接光耦的1脚,2脚悬空,3脚连接光耦的2脚;第一电容、第二电阻以及二极管连接在光耦的1脚和2脚之间,光耦的3脚接地,第二电容连接在光耦的4脚和地之间,第三电阻连接在光耦的4脚和+24V之间,光耦的4脚串联第四电阻后连接双二极管的3脚,第五电阻连接在双二极管的3脚和地之间,双二极管的1脚接+3.3V,双二极管的2脚接数字地,双二极管的3脚串联第六电阻后连接CPU。本实用新型通过检测启动电阻两端电压,阻止大电流通过启动电阻,保护了启动电阻不会烧毁,并且不会引起误动作,灵敏度高,保护迅速。

The utility model discloses a failure protection circuit for a main relay of a frequency converter, which comprises a connector and an optocoupler. The connector is arranged at both ends of a start-up resistor. Pin 1 of the connector is connected in series with the first resistor to connect pin 1 of the optocoupler, and pin 2 is suspended in the air. , pin 3 is connected to pin 2 of the optocoupler; the first capacitor, the second resistor and the diode are connected between pin 1 and pin 2 of the optocoupler, pin 3 of the optocoupler is grounded, and the second capacitor is connected between pin 4 and pin 2 of the optocoupler Between ground, the third resistor is connected between pin 4 of the optocoupler and +24V, pin 4 of the optocoupler is connected in series with the fourth resistor and pin 3 of the dual diode is connected, and the fifth resistor is connected between pin 3 of the dual diode and the ground In between, pin 1 of the dual diode is connected to +3.3V, pin 2 of the dual diode is connected to the digital ground, pin 3 of the dual diode is connected in series with the sixth resistor and then connected to the CPU. The utility model prevents a large current from passing through the starting resistor by detecting the voltage at both ends of the starting resistor, protects the starting resistor from being burned, and does not cause malfunction, and has high sensitivity and rapid protection.

Description

变频器主继电器失效保护电路Inverter main relay failure protection circuit

技术领域technical field

本实用新型涉及变频器领域,具体涉及一种变频器主继电器失效保护电路。The utility model relates to the field of frequency converters, in particular to a failure protection circuit for a main relay of a frequency converter.

背景技术Background technique

变频器所使用的继电器并联在启动电阻两端,在工作时,继电器若发生故障脱扣,会烧毁启动电阻。现有技术多采用主继电器辅助触点吸合检测电路来检测主继电器之工作状态,控制线路通断,从而对启动电阻进行保护。但主继电器辅助触点吸合检测电路易引起误动作,且灵敏度较低。The relay used by the frequency converter is connected in parallel at both ends of the starting resistor. During operation, if the relay fails and trips, the starting resistor will be burned. In the prior art, the auxiliary contact detection circuit of the main relay is mostly used to detect the working state of the main relay, and control the circuit on and off, so as to protect the starting resistor. However, the main relay auxiliary contact pull-in detection circuit is easy to cause misoperation, and the sensitivity is low.

实用新型内容Utility model content

针对上述问题,本实用新型提供了一种变频器主继电器失效保护电路,通过检测启动电阻两端电压,起到防止烧坏启动电阻的功能。In view of the above problems, the utility model provides a failure protection circuit for the main relay of the frequency converter, which can prevent the starting resistor from burning out by detecting the voltage at both ends of the starting resistor.

本实用新型的技术方案如下:The technical scheme of the utility model is as follows:

一种变频器主继电器失效保护电路,包括连接器和光耦,所述连接器设置在启动电阻两端,所述连接器的1脚串联第一电阻后连接光耦的1脚,所述连接器的2脚悬空,所述连接器的3脚连接光耦的2脚,第一电容、第二电阻以及二极管连接在所述光耦的1脚和2脚之间,所述光耦的3脚接地,第二电容连接在所述光耦的4脚和地之间,第三电阻连接在所述光耦的4脚和+24V之间,所述光耦的4脚串联第四电阻后连接双二极管的3脚,第五电阻连接在所述双二极管的3脚和地之间,所述双二极管的1脚接+3.3V,所述双二极管的2脚接数字地,所述双二极管的3脚串联第六电阻后连接CPU。A failure protection circuit for a main relay of an inverter, including a connector and an optocoupler, the connector is arranged at both ends of a starting resistor, and pin 1 of the connector is connected to pin 1 of the optocoupler after being connected in series with a first resistor, and the connector pin 2 of the optocoupler is suspended, pin 3 of the connector is connected to pin 2 of the optocoupler, the first capacitor, the second resistor and the diode are connected between pin 1 and pin 2 of the optocoupler, and pin 3 of the optocoupler ground, the second capacitor is connected between pin 4 of the optocoupler and the ground, the third resistor is connected between pin 4 of the optocoupler and +24V, and pin 4 of the optocoupler is connected in series with the fourth resistor Pin 3 of the dual diode, the fifth resistor is connected between pin 3 of the dual diode and ground, pin 1 of the dual diode is connected to +3.3V, pin 2 of the dual diode is connected to digital ground, and the dual diode The 3rd pin is connected to the CPU after connecting the sixth resistor in series.

本实用新型的有益技术效果是:The beneficial technical effect of the utility model is:

本实用新型通过检测启动电阻两端电压,阻止大电流通过启动电阻,从而防止烧坏启动电阻。相比现有主继电器辅助触点吸合检测电路,本实用新型能直接检测主继电器之工作状态,不会引起误动作,灵敏度高,保护迅速。The utility model prevents a large current from passing through the starting resistor by detecting the voltage at both ends of the starting resistor, thereby preventing the starting resistor from being burned out. Compared with the existing main relay auxiliary contact pull-in detection circuit, the utility model can directly detect the working state of the main relay without causing malfunction, has high sensitivity and quick protection.

附图说明Description of drawings

图1是本实用新型的电路原理图。Fig. 1 is the schematic circuit diagram of the utility model.

具体实施方式Detailed ways

下面结合附图对本实用新型的具体实施方式做进一步说明。Below in conjunction with accompanying drawing, the specific embodiment of the present utility model is described further.

如图1所示,本实用新型包括连接器CN1和光耦PC1。连接器CN1设置在启动电阻R两端。连接器CN1的1脚串联电阻R1后连接光耦PC1的1脚,连接器CN1的2脚悬空,连接器CN1的3脚连接光耦PC1的2脚。电容C1、第二电阻R2以及二极管D1连接在光耦PC1的1脚和2脚之间,光耦PC1的3脚接地,电容C2连接在光耦PC1的4脚和地GND之间,电阻R3连接在光耦PC1的4脚和+24V之间,光耦PC1的4脚串联电阻R4后连接双二极管D2的3脚。电阻R5连接在双二极管D2的3脚和地GND之间。双二极管D2的1脚接+3.3V,双二极管D2的2脚接数字地DGND,双二极管D2的3脚串联电阻R6后连接CPU。As shown in Figure 1, the utility model includes a connector CN1 and an optocoupler PC1. The connector CN1 is arranged on both ends of the starting resistor R. Pin 1 of connector CN1 is connected in series with resistor R1 to pin 1 of optocoupler PC1, pin 2 of connector CN1 is suspended, and pin 3 of connector CN1 is connected to pin 2 of optocoupler PC1. Capacitor C1, second resistor R2 and diode D1 are connected between pin 1 and pin 2 of optocoupler PC1, pin 3 of optocoupler PC1 is grounded, capacitor C2 is connected between pin 4 of optocoupler PC1 and ground GND, resistor R3 Connect between pin 4 of optocoupler PC1 and +24V, pin 4 of optocoupler PC1 is connected in series with resistor R4 to pin 3 of dual diode D2. The resistor R5 is connected between pin 3 of the double diode D2 and the ground GND. Pin 1 of the dual diode D2 is connected to +3.3V, pin 2 of the dual diode D2 is connected to the digital ground DGND, and pin 3 of the dual diode D2 is connected to the CPU in series with a resistor R6.

以上所述的元器件均为市售商品,实施例中的元器件型号可参见下表:The components and parts described above are all commercially available products, and the components and parts models in the embodiments can be found in the following table:

图1中主要元器件表:The main components list in Figure 1:

序号serial number 元器件代号Component code 元器件类型Component type 元器件参数或型号Component parameters or models 11 CN1CN1 连接器Connector 22 PC1PC1 光耦optocoupler PC817PC817 33 R1R1 电阻resistance 3K,3W,5%3K, 3W, 5% 44 R2R2 电阻resistance 10K,1/10W,1%10K, 1/10W, 1% 55 R3R3 电阻resistance 22K,1/10W,1%22K, 1/10W, 1% 66 R4R4 电阻resistance 27K,1/10W,1%27K, 1/10W, 1% 77 R5R5 电阻resistance 3.9K,1/4W,1%3.9K, 1/4W, 1% 88 R6R6 电阻resistance 10K,1/10W,1%10K, 1/10W, 1% 99 C1C1 电容capacitance 47uF,100V47uF,100V 1010 C2C2 电容capacitance 220pF,50V220pF,50V 1111 D1D1 二极管diode RLS4148RLS4148 1212 D2D2 双二极管double diode DAN217UDAN217U

本实用新型的工作过程如下:The working process of the present utility model is as follows:

启动电阻R(一般约几欧姆)接入连接器CN1,启动电阻R与继电器并联。正常工作状态下,继电器吸合,启动电阻R被短路,连接器CN1之1脚、2脚电压为0V,光耦PC1不导通,光耦PC1之4脚为高阻态,则本实用新型电路输出至CPU为高电平。当继电器故障跳脱,启动电阻R两端产生压降,透过电阻R1、电容C1缓冲电路,当光耦PC1输入引脚之电压电流满足导通条件时,光耦PC1之4脚电压下拉至GND(0V),则本实用新型电路输出至CPU为低电平,此时CPU遮断SPWM信号输出,关断IGBT,面板跳故障显示。本实用新型阻止大电流通过启动电阻R,即保护了启动电阻R不会烧毁。The starting resistor R (generally about a few ohms) is connected to the connector CN1, and the starting resistor R is connected in parallel with the relay. Under normal working conditions, the relay pulls in, the starting resistor R is short-circuited, the voltage of pin 1 and pin 2 of the connector CN1 is 0V, the optocoupler PC1 is not conducting, and the pin 4 of the optocoupler PC1 is in a high-impedance state, then the utility model The output of the circuit to the CPU is a high level. When the relay trips due to a fault, a voltage drop occurs at both ends of the starting resistor R. Through the buffer circuit of resistor R1 and capacitor C1, when the voltage and current of the input pin of optocoupler PC1 meet the conduction condition, the voltage of pin 4 of optocoupler PC1 is pulled down to GND (0V), then the output of the utility model circuit to the CPU is a low level, at this moment, the CPU blocks the SPWM signal output, turns off the IGBT, and the panel jumps to display a fault. The utility model prevents a large current from passing through the starting resistor R, that is, protects the starting resistor R from being burned.

本实用新型的设计方案要点:Key points of the design scheme of the present utility model:

1、启动电阻R串联在主回路直流母线上,为高压电路,采用了光耦PC1隔离,保护了二次侧低压电路。1. The starting resistor R is connected in series with the DC bus of the main circuit, which is a high-voltage circuit, and the optocoupler PC1 is used to isolate it, which protects the low-voltage circuit on the secondary side.

2、光耦PC1输入引脚反向并联二极管D1,用来吸收反向电压,防止光耦PC1被反压击穿。2. Anti-parallel diode D1 is connected to the input pin of optocoupler PC1 to absorb reverse voltage and prevent optocoupler PC1 from being broken down by back pressure.

3、限流电阻R1采用3W封装,满足功率要求。3. The current limiting resistor R1 is packaged in 3W to meet the power requirements.

4、进入CPU之电压透过二极管D2钳位,使电压在-0.6V~3.3+0.6V之间,保护CPU。4. The voltage entering the CPU is clamped by diode D2, so that the voltage is between -0.6V~3.3+0.6V to protect the CPU.

5、本实用新型电路制作在电源板PCB上,占用空间很小,减小变频器整体体积。5. The circuit of the utility model is made on the power board PCB, which occupies a small space and reduces the overall volume of the frequency converter.

以上所述的仅是本实用新型的优选实施方式,本实用新型不限于以上实施例。可以理解,本领域技术人员在不脱离本实用新型的精神和构思的前提下直接导出或联想到的其他改进和变化,均应认为包含在本实用新型的保护范围之内。The above are only preferred implementations of the utility model, and the utility model is not limited to the above examples. It can be understood that other improvements and changes directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present utility model shall be considered to be included in the protection scope of the present utility model.

Claims (1)

1.一种变频器主继电器失效保护电路,其特征在于:包括连接器(CN1)和光耦(PC1),所述连接器(CN1)设置在启动电阻两端,所述连接器(CN1)的1脚串联第一电阻(R1)后连接光耦(PC1)的1脚,所述连接器(CN1)的2脚悬空,所述连接器(CN1)的3脚连接光耦(PC1)的2脚,第一电容(C1)、第二电阻(R2)以及二极管(D1)连接在所述光耦(PC1)的1脚和2脚之间,所述光耦(PC1)的3脚接地,第二电容(C2)连接在所述光耦(PC1)的4脚和地之间,第三电阻(R3)连接在所述光耦(PC1)的4脚和+24V之间,所述光耦(PC1)的4脚串联第四电阻(R4)后连接双二极管(D2)的3脚,第五电阻(R5)连接在所述双二极管(D2)的3脚和地之间,所述双二极管(D2)的1脚接+3.3V,所述双二极管(D2)的2脚接数字地,所述双二极管(D2)的3脚串联第六电阻(R6)后连接CPU。1. A inverter main relay failure protection circuit, characterized in that it includes a connector (CN1) and an optocoupler (PC1), the connector (CN1) is arranged at both ends of the starting resistor, and the connector (CN1) Pin 1 of the first resistor (R1) is connected in series with pin 1 of the optocoupler (PC1), pin 2 of the connector (CN1) is suspended, and pin 3 of the connector (CN1) is connected to pin 2 of the optocoupler (PC1). pin, the first capacitor (C1), the second resistor (R2) and the diode (D1) are connected between pin 1 and pin 2 of the optocoupler (PC1), and pin 3 of the optocoupler (PC1) is grounded, The second capacitor (C2) is connected between the 4 pins of the optocoupler (PC1) and the ground, the third resistor (R3) is connected between the 4 pins of the optocoupler (PC1) and +24V, the optocoupler The 4 pins of the coupler (PC1) are connected in series with the fourth resistor (R4) to the 3 pins of the double diode (D2), and the fifth resistor (R5) is connected between the 3 pins of the double diode (D2) and the ground, the Pin 1 of the dual diode (D2) is connected to +3.3V, pin 2 of the dual diode (D2) is connected to digital ground, and pin 3 of the dual diode (D2) is connected in series with the sixth resistor (R6) to the CPU.
CN201520527512.3U 2015-07-20 2015-07-20 Converter main relay fail safe circuit Expired - Lifetime CN204835502U (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105591365A (en) * 2016-02-25 2016-05-18 珠海格力节能环保制冷技术研究中心有限公司 Frequency converter main circuit relay failure protection method
CN108923388A (en) * 2018-08-17 2018-11-30 东菱技术有限公司 A kind of fault detection circuit powering on buffer cell and method
CN109390915A (en) * 2017-08-04 2019-02-26 浙江正泰电器股份有限公司 Method of controlling security, equipment and its system of system with pre-charge circuit
CN110797844A (en) * 2019-10-25 2020-02-14 珠海格力电器股份有限公司 Magnetic levitation centrifuge, storage medium, high-power inverter and control method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105591365A (en) * 2016-02-25 2016-05-18 珠海格力节能环保制冷技术研究中心有限公司 Frequency converter main circuit relay failure protection method
CN109390915A (en) * 2017-08-04 2019-02-26 浙江正泰电器股份有限公司 Method of controlling security, equipment and its system of system with pre-charge circuit
CN108923388A (en) * 2018-08-17 2018-11-30 东菱技术有限公司 A kind of fault detection circuit powering on buffer cell and method
CN110797844A (en) * 2019-10-25 2020-02-14 珠海格力电器股份有限公司 Magnetic levitation centrifuge, storage medium, high-power inverter and control method thereof
CN110797844B (en) * 2019-10-25 2025-04-25 珠海格力电器股份有限公司 Magnetic suspension centrifuge, storage medium, high-power frequency converter and control method thereof

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