CN204809222U - Integrated morphology and pixel circuit with thermistor array - Google Patents
Integrated morphology and pixel circuit with thermistor array Download PDFInfo
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- CN204809222U CN204809222U CN201520184416.3U CN201520184416U CN204809222U CN 204809222 U CN204809222 U CN 204809222U CN 201520184416 U CN201520184416 U CN 201520184416U CN 204809222 U CN204809222 U CN 204809222U
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Abstract
The utility model relates to an infrared sensing field of non - refrigeration class, exactly, provide one kind based on MEMS technique the coming overall arrangement thermistor and provide corresponding integrated morphology of preferred in the focal plane array sensing device, an integrated pixel circuit that has the thermistor array has also been disclosed in the lump, an array that includes a plurality of thermistor has been found, every thermistor includes four corners, the every nook and cranny forms an incision, be provided with shared terminal in this thermistor's the array, be formed with first electrically conductive arm among the thermistor, the 2nd thermistor is formed with the electrically conductive arm of second, first electrically conductive arm is connected with the electrically conductive arm of second, by the present technical scheme, reduced to crosstalk between the adjacent thermistor and parasitic capacitance and parasitic resistance, can greatly improve the integrated level or the fillratio of pixel, array angle analysis from the pixel constitution, whole area matches that the prior art reduction can be at least more than 20%, and the technology manufacturing of being convenient for.
Description
Technical field
The utility model relates generally to the infrared sensing field of non-brake method class, exactly, be to provide one in focal plane array sensing device, preferably carry out layout thermistor based on MEMS technology and corresponding integrated morphology is provided, also disclose a kind of pixel circuit being integrated with thermistor array in the lump.
Background technology
Uncooled infrared detector device is widely used as thermal sensing, such as, based on the thermal effect of infrared radiation.Traditional sensing device is more common in thermal reactor, pyroelectricity and micro--bolograph (Micro-bolometer) etc., bolograph based on microbridge (Micro-bridge) structure is tending towards being widely used, and causes the floating change of the resistance of thermistor and respond out corresponding change in radiation intensity by perception infrared radiation thermal effect.Infrared imaging is that the sensing outside visible light wave range scope extends, and focal plane array is the sensitive components of infrared imaging, has dominated the quality of infrared imaging.It is many-sided for affecting the factor of pixel in focal plane array, thermal insulation for example between pixel or absorptivity difference, change in resistance and temperature coefficient of resistance etc., the problem that typical such as prior art is optimizing pixel array area excessive also treats harshly improvement, two ports mainly due to adjacent thermistor are all independently, they can't the proportional reduction with the reduction of semiconductor manufacturing live width, then easily cause pixel array area larger.In addition, the layout of port and pixel is incorrect very easily brings out negative crosstalk and parasitic capacitance and dead resistance etc. between adjacent thermistor.Under the prerequisite additionally not increasing device size, how realizing the better layout of thermistor focal plane array and compatible present production process and solve existing negative factor, is the puzzlement that prior art faces.
Utility model content
In an embodiment of the present utility model, provide a kind of thermistor integrated morphology, mainly comprise: the array comprising multiple thermistor, each thermistor there are four bights, each bight respectively forms an otch, wherein, in described array, two pairs of thermistors are limited with two row of arbitrary neighborhood by two row of arbitrary neighborhood, the thermistor arranged diagonally for a pair wherein and another to the public symmetrical center positions place of the thermistor arranged diagonally, nationality forms a vacant district by each otch layout of this center position the most contiguous of these two pairs of thermistors, be located at the shared terminal in described vacant district, first, second thermistor that in array, any row are adjacent before and after being provided with, described first thermistor deviates from and is connected with the first conductive arm in a first bight place of the second thermistor, and described second thermistor deviates from and is connected with the second conductive arm in a second bight place of the first thermistor, first thermistor with its first bight being connected with first, second conductive arm with a shared terminal of the otch position at a 4th bight place at diagonal angle each other, its second bight of the otch at a third corner place at diagonal angle and the second thermistor each other.
Above-mentioned thermistor integrated morphology, first conductive arm extends to the third corner of the first thermistor with the first clockwise along the edge of the first thermistor from the first bight of the first thermistor, second conductive arm extends to the 4th bight of the second thermistor with the second clockwise along the edge of the second thermistor from the second bight of the second thermistor, thus on a shared terminal arranging of the otch first, second conductive arm being connected to the otch of the third corner of the most contiguous first thermistor and the 4th bight of the second thermistor.
Above-mentioned thermistor integrated morphology, the 3rd conductive arm being connected to the third corner place of the first thermistor extends to the first bight of the first thermistor with the first clockwise along the edge of the first thermistor from the third corner of the first thermistor, and be connected with the shared terminal of incision in the first bight being arranged at the most contiguous first thermistor.
Above-mentioned thermistor integrated morphology, the 4th conductive arm being connected to the 4th bight place of the second thermistor extends to the second bight of the second thermistor with the second clockwise along the edge of the second thermistor from the 4th bight of the second thermistor, and be connected with the shared terminal of incision in the second bight being arranged at the most contiguous second thermistor.
Above-mentioned thermistor integrated morphology, first conductive arm be arranged in first, second thermistor between the two the part in gap and the second conductive arm be arranged in first, second thermistor between the two a gap part be arranged side by side and extend parallel to each other, thus first, second conductive arm to be connected on a shared terminal set by incision in the incision of the third corner of the most contiguous first thermistor and the 4th bight of the second thermistor.
Above-mentioned thermistor integrated morphology, contain multiple basic resistance unit of being made up of first, second both thermistor or be directly called resistance unit in any row of array, the shared terminal that in the shared terminal that in any one basic resistance unit, the otch in the second bight of the most contiguous second thermistor is arranged and the basic resistance unit of the adjacent next one, the otch in the first bight of the most contiguous first thermistor is arranged is same share terminal.
Above-mentioned thermistor integrated morphology, in an array in the mode that two adjacent thermistors of any front and back of same row are electrically connected mutually, further all thermistors of same row are all connected in series, and the thermistor arbitrarily with a line in array is set to not be electrically connected each other each other.
In an embodiment of the present utility model, provide a kind of pixel circuit with thermistor array, mainly comprise: comprise multiple basic pixel unit or be directly called pixel cellular array, in any row, often the basic pixel unit of row all comprises a resistance and two switches with this resistant series; Arrange three resistance of arbitrary neighborhood in all resistance of same row, two resistance being wherein positioned at the resistance two ends in centre position adjacent with front and back are respectively connected, thus are all connected in series by resistance all in same row; Often be connected with a switch of this row between one end of a resistance of row and a first node in same row and between the other end of this resistance and a Section Point, be connected with another switch of this row, reading the control of first, second internodal resistance by the basic pixel unit of each row two switches separately in same row.
The above-mentioned pixel circuit with thermistor array, the mode reading each resistance of same row at first node and Section Point comprises, there is provided quantity to equal basic pixel list switch separately that a series of different time series pulse signals of line number in same row drives different rows respectively, wherein in same row, two switches of any a line are subject to the driving of same time series pulse signals.
The above-mentioned pixel circuit with thermistor array, nationality is by the time series pulse signals of a series of non-overlapping, disconnect again after making the switch of each row successively perform connection one section of Preset Time successively according to the order from first trip to footline, and in two time series pulse signals being supplied to the basic pixel unit of two row adjacent arbitrarily, drive the moment that the first logic state of the previous time series pulse signals of previous row basic pixel list breaker in middle terminates, and between the moment that after driving, a rear time series pulse signals of a line basic pixel list breaker in middle enters the first logic state, a predetermined time delay is set.
In an embodiment of the present utility model, provide a kind of read method of the pixel circuit with thermistor array, mainly comprise the following steps: comprising in multiple basic pixel cellular array, the basic pixel unit arranging often row in any row all comprises a resistance and two switches with this resistant series; Be connected by three resistance of arbitrary neighborhood in all resistance of same row, two resistance being wherein positioned at middle resistance two ends adjacent with front and back are respectively connected, thus are all connected in series by resistance all in same row; In same row often a resistance of row one end be connected one between a first node and belong to the switch of this row and the other end of this resistance and between a Section Point, be connected another switch belonging to this row; There is provided quantity to equal a series of time series pulse signals of line number in same row, drive the basic pixel list switch separately of different rows in these row respectively, make two switches of any a line in same row be subject to the driving of same time series pulse signals; Disconnect again after in same column, the switch of each row successively performs connection one section of Preset Time according to the order from first trip to footline, drive in two time series pulse signals of the basic pixel unit of two row adjacent arbitrarily, drive the moment that the first logic state of the previous time series pulse signals of previous row basic pixel list breaker in middle terminates, and between the moment that after driving, a rear time series pulse signals of a line basic pixel list breaker in middle enters the first logic state, a predetermined time delay is set.
Advantage of the present utility model and the beneficial effect using the utility model to reach:
The technical solution of the utility model, by the ports share of adjacent thermistor, reduce crosstalk and parasitic capacitance and dead resistance between adjacent thermistor, greatly can improve integrated level or the packing ratio of pixel, from the array angle analysis of pixel composition, the suitable prior art of entire area reduces more than at least 20%, and can be convenient to manufacture technics.
Accompanying drawing explanation
Read following detailed description also with reference to after the following drawings, Characteristics and advantages of the present utility model will be apparent:
What Fig. 1 was exemplary illustrate in thermistor array, and two row two arrange the plan view from above of the two pairs of thermistors limited.
Fig. 2 is the schematic diagram of two-dimentional thermistor array as focal plane array.
Fig. 3 is with independent row thermistor schematic diagram exemplarily in the pixel circuit of thermistor array.
Fig. 4 is a series of time series pulse signals of the switch driving different rows in independent row.
Fig. 5 is the profile that two-dimentional thermistor array is suspended in the substrate of integrated CMOS reading circuit.
Embodiment
See Fig. 1 ~ 2, illustrate and adopt two-dimentional thermistor array as focal plane array, infrared radiation is converted to thermal signal by the un-cooled infrared focal plane array based on thermistor, require that resistance material is extremely sensitive to thermal change, higher temperature coefficient of resistance and lower material noise should be had.What when layout array, our leading setting was different is on all four between the column and the column on layout type, just as any two row copy mutually, based on the program, and in order to the facility herein in explaination, also specially to point out that from thermistor array complete shown in Fig. 2 two row 155,156 that adjoin mutually before and after acquisition separately carry out describing illustrate to correspond to Fig. 1, the pixel distribution that whole permutation is complete thus so in order.For two adjacent row 155,156 in the whole array of thermistor, the first trip showing previous column 155 in fig. 2 comprises a thermistor PIXP
1, the second row comprises a thermistor PIXP
2, the third line comprises a thermistor PIXP
3... until the n-th line of footline comprises a thermistor PIXP
n, here n should be more than or equal to 1 natural number.The then first trip of row 155 comprises a thermistor PIXS
1, the second row comprises a thermistor PIXS
2, the third line comprises a thermistor PIXS
3... until the n-th line of footline comprises a thermistor PIXS
n.Return again see Fig. 1, just define in fact four thermistor PIXP close to each other based on two adjacent row 165,166 before and after acquisition independent in these two row again after two in advance selected row 155,156
k-1, PIXS
k-1and PIXP
k, PIXS
k, in other words, we will representatively characterize the layout of whole array with these four thermistors.No matter should be appreciated that when reading herein and usually know the knowledgeable to having this area, be early stage the proposed germanium silicon/silicon (Si based on P type alloy of industry
1-Xge
x/ Si) the semi-conducting material of multi-quantum pit structure still based on vanadium oxide VO
xwith the sensitive material etc. based on amorphous silicon AmorphousSilicon, be all applicable to the thermistor that the utility model is mentioned.
The object thermistor PIXP of research
k-1, PIXS
k-1be positioned at same a line 165, thermistor PIXP
k, PIXS
kbe positioned at same a line 166, thermistor PIXP
k-1, PIXP
kbe positioned at same row 155, thermistor PIXS
k-1, PIXS
kbe positioned at same row 156.Be easy in the drawings learn, be originally rendered as square thermistor substantially due to each bight and be removed formation otch, and be respectively connected with conductive arm at a pair diagonal angle place of each thermistor and make their shapes rule no longer so very.Further the incision in each bight of each thermistor is provided with a shared terminal, two thermistors adjacent before and after same row will shared in common shared terminal.In FIG, in four selected thermistors mentioned above, wherein a pair substantially in the symmetrically arranged thermistor PIXP of diagonally opposing corner for the detailed embodiment of these layout details of array
k-1, PIXS
khave symmetrical center positions 255, another is to thermistor PIXP
k, PIXS
k-1also be symmetrical arranged in diagonally opposing corner substantially with this symmetrical center positions 255.Each bight due to each thermistor is provided with an otch, obviously, then and thermistor PIXP
k-1, PIXS
k-1and PIXP
k, PIXS
kfour otch that they are distributed in symmetrical center positions 255 place separately gather together, and just define the vacant district being positioned at this center 255 place, and so-called vacant district essence does not arrange the region of any thermistor material.Or with the language description of other substitutability, with the thermistor PIXP of a line
k-1, PIXS
k-1(or thermistor PIXP
k, PIXS
k) both longitudinal symmetrical center line 180 and the thermistor PIXP of same row
k-1, PIXP
k(or thermistor PIXS
k-1, PIXS
k) both lateral symmetry center line 185 intersects at a center 255, in other words, this center 255 directly these two pairs of thermistors center position in the plane also without any improper, the otch that the two pairs of resistance is positioned at this center 255 just forms vacant district, so, here description thermistor and the relative position relation in vacant district can be characterized by the various literal expression modes converted arbitrarily by nationality, in reading this paper or the essence that should respect fully utility model spirit when understanding claim institute limited range.Great facility can be provided thus, because thermistor needs electrical interconnects to form pixel circuit, thermistor realizes interconnection then needs some conductive arms and some interconnect terminals, the conductive arm of elongate can be arranged among the narrow gap between adjacent thermistor, and one of meaning that vacant district exists arranges interconnect terminals.Graphic is with the shared terminal CP of layout in the center 255 of these four thermistors
ifor example is explained.
Before and after above discussing, two row 155,156 are the relations in order to deliberately illustrate in array between the column and the column, and then will explain in detail as row among row self of example and the relation between going separately.For example for the thermistor PIXP of same row 155
k-1, PIXP
k, be square thermistor PIXP originally
k-1essence has first to fourth four bights 121,122,123 and 124 added up to of counterclockwise sequence, and respectively there is an otch in each bight, and same is square thermistor PIXP originally
kessence also has first to fourth four bights 131,132,133 and 134 added up to of counterclockwise sequence, and respectively there is an otch in each bight.Thermistor PIXP
k-1deviate from thermistor PIXP
kthe incision in the first bight 121 be connected with the first conductive arm 101b, and thermistor PIXP
kdeviate from thermistor PIXP
k-1the incision in the second bight 132 be connected with the second conductive arm 101c, thermistor PIXP here
k-1deviate from PIXP
kbight refer to that it is away from PIXP
ktwo bights 121 and 124 instead of near PIXP
ktwo bights 122 and 123, thermistor PIXP
kdeviate from PIXP
k-1bight refer to that it is away from PIXP
k-1two bights 132 and 133 instead of near PIXP
k-1two bights 131 and 134, the same or similar description occurred hereinafter should be understood with explanation identical therewith.First conductive arm 101b is along thermistor PIXP
k-1edge from thermistor PIXP
k-1the first bight 121 counterclockwise to extend to thermistor PIXP
k-1third corner 123 place, essence be also along first bend from starting point first bight 121 extend to the second bight 122 after again bending to extend near third corner 123 and the first conductive arm 101b is arranged, because thermistor PIXP in the path stopped
k-1with between other thermistors being enclosed in its surrounding be not contact but separated from one another and remain with certain thin narrow slot, the layout type saving area is most set to the first conductive arm 101b along thermistor PIXP
k-1edge and with thermistor PIXP
k-1edge parallel, but with thermistor PIXP
k-1the certain predeterminable range of marginating compartment.Second conductive arm 101c is along thermistor PIXP
kedge from thermistor PIXP
kthe second bight 132 extend to thermistor PIXP in a clockwise direction
kthe 4th bight 134 place, essence be also along first bend from starting point second bight 132 extend to the first bight 131 after again bending extend near the 4th the bight 134 and path stopped and arrange the and conductive arm 101c, same thermistor PIXP
kand be separate and remain with certain thin narrow slot between other thermistors being enclosed in its surrounding, preferably the second conductive arm 101c be set to along thermistor PIXP
kedge and with thermistor PIXP
kedge parallel, but with thermistor PIXP
kthe certain predeterminable range of marginating compartment.
Because above one shared terminal CP
ibe positioned at thermistor PIXP
k-1with its first bight 121 each other third corner 123 place at diagonal angle otch and be positioned at thermistor PIXP simultaneously
kwith these two incision site places of otch at the 4th bight 134 place at diagonal angle each other, its second bight 132, simultaneously again because the first conductive arm 101b is from thermistor PIXP
k-1the first bight 121 counterclockwise to extend to thermistor PIXP
k-1third corner 123 place, and the second conductive arm 101c is from thermistor PIXP
kthe second bight 132 extend to thermistor PIXP
kthe 4th bight 134 place, then select the first conductive arm 101b of electrode material and the second conductive arm 101c can at the shared terminal CP of center 255 place and conductive material
idirect mechanical connects and is electrically connected, and notices that wherein electrode material can adopt but be not restricted to the conventional electric conducting material such as such as Ti, TiN, Ta, TaN, TiW, NiCr.
In addition, one of our object allows all thermistors of same row all be connected in series, so thermistor PIXP in figure
k-1except will with thermistor PIXP
kelectrical interconnects is in shared terminal CP
ioutside place, thermistor PIXP
k-1also need the previous thermistor PIXP do not illustrated with it
k-2be connected in a shared terminal CP
i-1place, and thermistor PIXP
kalso will with its a rear thermistor PIXP do not illustrated
k+1be connected in a shared terminal CP
i+1place, note k and i be here all be more than or equal to 1 natural number.Concrete gimmick is, is connected to thermistor PIXP
k-1the 3rd conductive arm 101a of an elongate at third corner 123 place along thermistor PIXP
k-1edge from thermistor PIXP
k-1third corner 123 counterclockwise to extend to thermistor PIXP
k-1the first bight 121 place, and be arranged at thermistor PIXP
k-1the first bight 121 incision near a shared terminal CP
i-1connect, in fact along after first extending to the 4th bight 124 from the third corner 123 of starting point again bending to extend near the first bight 121 and the 3rd conductive arm 101a is arranged in the path stopped, equally the 3rd conductive arm 101a is set to along thermistor PIXP
k-1edge and with thermistor PIXP
k-1edge parallel, but with thermistor PIXP
k-1the certain predeterminable range of marginating compartment.In addition, thermistor PIXP is connected to
kthe 4th conductive arm 101d of an elongate at the 4th bight 134 place along thermistor PIXP
kedge from thermistor PIXP
kthe 4th bight 134 extend to thermistor PIXP in a clockwise direction
kthe second bight 132 place, and be arranged at thermistor PIXP
kthe second bight 132 incision near a shared terminal CP
i+1connect, in fact along after first extending to third corner 133 from the 4th bight 134 of starting point again bending to extend near the second bight 132 and the 4th conductive arm 101d is arranged in the path stopped, equally the 4th conductive arm 101d is set to along thermistor PIXP
kedge and with thermistor PIXP
kedge parallel, but with thermistor PIXP
kthe certain predeterminable range of marginating compartment.
It must be emphasized that, the first conductive arm 101b is positioned at thermistor PIXP
k-1, PIXP
ka part between the two in gap and the second conductive arm 101c are positioned at thermistor PIXP
k-1, PIXP
kin gap, a part is arranged side by side between the two, and these two parts extend parallel to each other, this parallel two parts spacing can arrange very little, very closely each other overlaps them all without any doubt even, because they originally need electrical couplings.
We find, in same row 155, and an optional in fact separately thermistor PIXP
ktwo conductive arm related is not completely the same on pattern with other all thermistors with conductive arm, that is independent thermistor PIXP
kit is not the minimum structure cell repeated in row 155.In order to explain this point, thermistor PIXP in same row 155 can be learned
1with thermistor PIXP
3completely the same similarly is what copy, but thermistor PIXP
1with its rear thermistor PIXP
2but not identical layout, but thermistor PIXP
2with thermistor PIXP
4but be identical layout, that is first kind thermistor (PIXP of identical topology/pattern
1, PIXP
3, PIXP
5) with the Equations of The Second Kind thermistor (PIXP of identical topology/pattern
2, PIXP
4, PIXP
6) configuration of mutual alternate intervals occurs.If but conversely speaking, by thermistor PIXP
k-1be referred to as the first thermistor and by thermistor PIXP
kbe referred to as the second thermistor, first, second thermistor integrated simultaneously and be merged into a basic resistance unit.We turn back to Fig. 2 again, in any row of array, such as, in graphic row 155, by a pair first, second thermistor (PIXP
1, PIXP
2) both are defined as a basic resistance unit Cell
1, by another to first, second thermistor (PIXP
3, PIXP
4) both are defined as and Cell
1another adjacent basic resistance unit Cell
2, then in same row 155, each resistance can be divided into a series of basic resistance unit Cell, and basic resistance unit Cell is then the structure cell repeated, and can learn basic resistance unit Cell very intuitively in figure
1with basic resistance unit Cell
2identical.It should be noted that any one basic resistance unit is as Cell
1in the second thermistor (as PIXP
2) the second bight 132 otch near arrange a shared terminal CP
3with adjacent rear/next basic resistance unit as Cell
2in the first thermistor (as PIXP
3) the first bight 121 otch near arrange a shared terminal CP
3it is same share terminal.Or changing a kind of saying, any one basic resistance unit is as Cell
2in the first thermistor (as PIXP
3) the first bight 121 otch near arrange a shared terminal CP
3with adjacent before/a upper basic resistance unit is as Cell
1in the second thermistor (as PIXP
2) the second bight 132 otch near arrange a shared terminal CP
3it is same share terminal.Basic resistance unit Cell in same row 155
mrepeat.
Obviously, in an array in the mode that two adjacent thermistors of any front and back of same row such as 155 are electrically connected mutually, further all thermistors of these same row 155 are all connected in series, different row have the layout identical with row 155, and the thermistor arbitrarily with a line such as 165 in array is set to not be electrically connected each other each other, be at least connected to each other by conductive arm and/or shared terminal the plane at focal plane array and thermistor array place is not direct in other words.Just as the thermistor PIXP that the front and back with a line in Fig. 1 are adjoined mutually
k-1, PIXS
k-1their respective conductive arms one group that shares in position of simultaneously not connecting between them shares terminal CS
i-1, CP
ion, the thermistor PIXP that the front and back with a line are adjoined mutually
k, PIXS
ktheir respective conductive arms one group that shares in position of also simultaneously not connecting between them shares terminal CP
i, CS
i+1on.But greatly totally different with the layout type of same a line in same row, because the thermistor PIXP adjoined mutually before and after in same row
k-1, PIXP
ktheir respective conductive arms connect the one group of CP shared in terminal shared in position between them simultaneously
ion, or the thermistor PIXS that in same row, front and back are adjoined mutually
k-1, PIXS
ktheir respective conductive arms one group that shares in position of simultaneously connecting between them shares terminal CP
i, CS
iin a CS
ion.
Be based on above on physical structure level and analyze focal plane array, Fig. 3 is then the resistance R of all mutual series connection to same row
1, R
2, R
3... R
nthe pixel circuit level that they are formed is analyzed.Based on content above, we to know in same row before and after two adjacent thermistors to be all set as being electrically connected between them on one group of of sharing in terminal, if by thermistor R
1, R
2, R
3... R
nbe compared to the thermistor PIXP of same row 155
1, PIXP
2, PIXP
3... PIXP
n, and the thermistor R that in Fig. 3, front and back are adjacent
1, R
2the common node 301 of interconnection
1terminal CP quite shares in place
2, the thermistor R that front and back are adjacent
2, R
3the common node 301 of interconnection
2terminal CP quite shares in place
3... the thermistor R that front and back are adjacent
n-1, R
nthe common node 301 of interconnection
n-1terminal CP quite shares in place
n.Notice that pixel circuit and the planarizing two-dimentional thermistor array of simple Fig. 2 are except the resistant series of same row, be not quite similar part in addition.Be embodied in the biswitch control again of each resistance, a resistance R of the first row in same row
1one end and a first node TER
1between be connected with a switch S of this first row
1,1and this resistance R
1the other end and a Section Point TER
2between be connected with another switch S of this first row
1,2, resistance R
2one end and first node TER
1between be connected with resistance R
2a switch S of place second row
2,1and this resistance R
2the other end and Section Point TER
2between be connected with resistance R
2another switch S of being expert at
2,2, resistance R
3one end and first node TER
1between be connected with resistance R
3a switch S of place the third line
3,1and this resistance R
3the other end and Section Point TER
2between be connected with resistance R
3another switch S of being expert at
3,2, resistance R
none end and first node TER
1between be connected with resistance R
na switch S of the n-th line at place
n, 1and this resistance R
nthe other end and Section Point TER
2between be connected with resistance R
nanother switch S of being expert at
n, 2, the rest may be inferred.
In pixel circuit, in any row, the basic pixel units/modules PIXC of a line comprises a resistance R arbitrarily
nand with this resistance R
ntwo switch S of series connection
n, 1, S
n, 2, such as wherein graphic in row in the basic pixel unit PIXC of the first row
1comprise and be connected on first node TER
1, switch S between Section Point TER2
1,1, resistance R
1, switch S
1,2, and the basic pixel unit PIXC of the second row
2comprise and be connected on first node TER
1, Section Point TER
2between switch S
2,1, resistance R
2, switch S
2,2... the basic pixel unit PIXC of n-th line
ncomprise and be connected on first node TER
1, Section Point TER
2between switch S
n, 1, resistance R
n, switch S
n, 2etc., the rest may be inferred.Although what Fig. 3 showed is single-row, the circuit of entirety includes in fact the multiple row identical with the single row of Fig. 3, and therefore pixel circuit is made up of multiple basic pixel cell array.Each resistance R of same row is read at first node TER1 and Section Point TER2
1, R
2, R
3... R
nmode specifically comprise, provide quantity to equal a series of different time series pulse signals (PU of line number n in same row
1, PU
2, PU
3... PU
n) drive the basic pixel list PIXC of different rows respectively
1, PIXC
2, PIXC
3... PIXC
nrespective switch, such as, time series pulse signals PU
1driving switch S
1,1, S
1,2and be coupled to their control end, time series pulse signals PU
2driving switch S
2,1, S
2,2and be coupled to their control end ... time series pulse signals PU
ndriving switch S
n, 1, S
n, 2and be coupled to their control end etc.Note two switch (S of any a line in same row
n, 1, S
n, 2) be synchronously subject to same time series pulse signals PU
ndriving, the switch with a line turns on and off simultaneously.It should be noted that, the switch that the utility model context is mentioned refers to the three port type electronic switches that industry adopts, as field effect transistor or bipolar tube or junction transistor etc. or their combination, generally include an input and an output, and comprise the control end for connecting between control input end and output or turning off.
Nationality is by the time series pulse signals (PU of a series of non-overlapping
1, PU
2, PU
3... PU
n), make the basic pixel list PIXC of different each row
1, PIXC
2, PIXC
3... PIXC
n) each self-corresponding switch (S
1,1, S
1,2), (S
2,1, S
2,2) ... (S
n, 1, S
n, 2) according to from first trip (S
1,1, S
1,2) to footline (S
n, 1, S
n, 2) sequencing, disconnect again after successively performing connection one section of Preset Time successively, embody the feature of time series pulse signals non-overlapping.Switch turn on and off in action imbody time series pulse signals schematic diagram in the diagram, initial state, first via time series pulse signals PU
1enter high level logic state from low-level logic state and continue T
o1default turn-on time drive and connect the switch (S of this first row
1,1, S
1,2), time period T
o1the moment first via time series pulse signals PU terminated
1enter low-level logic state and cause now switch (S
1,1, S
1,2) be turned off, but from time period T
o1postpone a predetermined time delay T
d1afterwards, the second road time series pulse signals PU
2start enter high level logic state from low-level logic state and continue T
o2time drive and connect the switch (S of this second row
2,1, S
2,2).Preset time period T
o2the moment second road time series pulse signals PU terminated
2enter low-level logic state and cause now switch (S
2,1, S
2,2) be turned off, but from section T default turn-on time
o2postpone a predetermined time delay T
d2afterwards, the 3rd road time series pulse signals PU
3start enter high level logic state from low-level logic state and continue T
o3time drive and connect the switch (S of this third line
3,1, S
3,2).The like, the (n-1)th road time series pulse signals PU
n-1enter high level logic state from low-level logic state and continue T
on-1default turn-on time drive and connect the switch (S of this (n-1)th row
n-1,1, S
n-1,2), time period T
on-1the moment (n-1)th road time series pulse signals PU terminated
n-1enter low-level logic state and cause now switch (S
n-1,1, S
n-1,2) be turned off, but from time period T
on-1postpone a predetermined time delay T
dn-1afterwards, the n-th road time series pulse signals PU
nstart enter high level logic state from low-level logic state and continue T
ontime drive and connect the switch (S of this n-th line
n, 1, S
n, 2), conducting period T
onn-th road time series pulse signals PU after terminating
nbegin turning into low level shutdown switch (S
n, 1, S
n, 2).Can be summarized as substantially, be supplied to two row basic pixel unit PIXC adjacent arbitrarily
k-1, PIXC
ktwo time series pulse signals in, drive previous row basic pixel list PIXC
k-1breaker in middle (S
k-1,1, S
k-1,2) previous time series pulse signals PU
k-1moment of terminating of the first logic state, with a line basic pixel list PIXC after driving
kbreaker in middle (S
k, 1, S
k, 2) a rear time series pulse signals PU
ka predetermined time delay T was set between the moment entering the first logic state
dn, K > 1 here.
Fig. 5 be two-dimentional thermistor array be suspended in Multi-View Modeling ROIC substrate 201 on the profile of vertical direction, the reading circuit ROIC that substrate 201 is compatible with traditional CMOS manufacturing process and can prepares based on CMOS integrated circuit, the transistor switch (S of such as P type above or N-type
n, 1, S
n, 2) can be integrated in substrate 201.Thermistor 204 prepared by thermo-sensitive material is lived by physical support primarily of passivating material 207, the electric conducting material 205 forming conductive arm, support pier stud 203, and is suspended on substrate 201, arranges resonant cavity toward contact between thermistor 204 and substrate 201.Relative with pixel, and the structure being defined as blind element for eliminating underlayer temperature and ambient temperature interference then can be located at the upper surface of the substrate 201 below thermistor 204, the vertical interconnected guide pillar 206 belonging to the part supporting pier stud 203 is mainly used as conduction and is equivalent to microbridge pier, and it is equivalent to the shared terminal in Fig. 1 in fact, sometimes the cross section of interconnected guide pillar 206 can be replaced by the shared terminal of the complanation in Fig. 1, thermistor 204 is coupled on the integrated circuit of the such as ROIC in substrate 201 by vertical interconnected guide pillar 206, such as interconnected guide pillar 206 is directly connected on the metal material liner 202 of substrate 201 surface setting, the connectivity port that is coupled is carried out with external circuit because liner 202 is built-in circuits integrated in substrate 201.Conventional MEMS micro-processing technology is compatible with the micro-bridge structure that produces and meet and require and the sensor with focal plane array herein.
The details describing focal plane array comparatively detailed herein proves that the electric resistance array of itself and prior art exists larger difference in order to do one's utmost to reader, and this difference is by the ports share of adjacent thermistor, reduce crosstalk and parasitic capacitance and dead resistance between adjacent thermistor, greatly can improve integrated level or the packing ratio of pixel.From the array of pixel composition, the suitable prior art of entire area reduces more than at least 20%, and can be convenient to manufacture technics.
Above, by illustrating and accompanying drawing, give the exemplary embodiments of the ad hoc structure of embodiment, above-mentioned utility model proposes existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present utility model and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong in intention of the present utility model and scope.
Claims (10)
1. a thermistor integrated morphology, is characterized in that, comprising:
Comprise the array of multiple thermistor, each thermistor there are four bights, each bight respectively forms an otch, wherein, in described array, limit two pairs of thermistors by two row of arbitrary neighborhood with two row of arbitrary neighborhood, the thermistor arranged diagonally for a pair is wherein with another to the public symmetrical center positions place of the thermistor arranged diagonally, and nationality forms a vacant district by each otch layout of this center position the most contiguous of these two pairs of thermistors;
Be located at the shared terminal in described vacant district;
First, second thermistor that in array, any row are adjacent before and after being provided with, described first thermistor deviates from and is connected with the first conductive arm in a first bight place of the second thermistor, and described second thermistor deviates from and is connected with the second conductive arm in a second bight place of the first thermistor;
First thermistor with its first bight being connected with first, second conductive arm with a shared terminal of the otch position at a 4th bight place at diagonal angle each other, its second bight of the otch at a third corner place at diagonal angle and the second thermistor each other.
2. thermistor integrated morphology according to claim 1, it is characterized in that, first conductive arm extends to the third corner of the first thermistor with the first clockwise along the edge of the first thermistor from the first bight of the first thermistor, second conductive arm extends to the 4th bight of the second thermistor with the second clockwise along the edge of the second thermistor from the second bight of the second thermistor, thus by first, on the shared terminal that the otch that second conductive arm is connected to the otch of the third corner of the most contiguous first thermistor and the 4th bight of the second thermistor is arranged.
3. thermistor integrated morphology according to claim 1, it is characterized in that, the 3rd conductive arm being connected to the third corner place of the first thermistor extends to the first bight of the first thermistor with the first clockwise along the edge of the first thermistor from the third corner of the first thermistor, and be connected with the shared terminal of incision in the first bight being arranged at the most contiguous first thermistor.
4. thermistor integrated morphology according to claim 1, it is characterized in that, the 4th conductive arm being connected to the 4th bight place of the second thermistor extends to the second bight of the second thermistor with the second clockwise along the edge of the second thermistor from the 4th bight of the second thermistor, and be connected with the shared terminal of incision in the second bight being arranged at the most contiguous second thermistor.
5. thermistor integrated morphology according to claim 1, it is characterized in that, first conductive arm be arranged in first, second thermistor between the two the part in gap and the second conductive arm be arranged in first, second thermistor between the two a gap part be arranged side by side and extend parallel to each other, thus first, second conductive arm to be connected on a shared terminal set by incision in the incision of the third corner of the most contiguous first thermistor and the 4th bight of the second thermistor.
6. thermistor integrated morphology according to claim 1, it is characterized in that, array any one row in contain multiple basic resistance unit be made up of first, second both thermistor, in any one basic resistance unit the second bight of the most contiguous second thermistor otch arrange a shared terminal and the basic resistance unit of the adjacent next one in the most contiguous first thermistor the first bight otch arrange a shared terminal be same share terminal.
7. thermistor integrated morphology according to claim 1, it is characterized in that, in an array in the mode that two adjacent thermistors of any front and back of same row are electrically connected mutually, further all thermistors of same row are all connected in series, and the thermistor arbitrarily with a line in array is set to not be electrically connected each other each other.
8. with a pixel circuit for thermistor array, it is characterized in that, comprising:
Comprise multiple basic pixel cellular array, in any row, often the basic pixel unit of row all comprises a resistance and two switches with this resistant series;
Arrange three resistance of arbitrary neighborhood in all resistance of same row, two resistance being wherein positioned at the resistance two ends in centre position adjacent with front and back are respectively connected, thus are all connected in series by resistance all in same row;
Often be connected with a switch of this row between one end of a resistance of row and a first node in same row and between the other end of this resistance and a Section Point, be connected with another switch of this row, reading the control of first, second internodal resistance by the basic pixel unit of each row two switches separately in same row.
9. according to claim 8 with the pixel circuit of thermistor array, it is characterized in that, the mode reading each resistance of same row at first node and Section Point comprises, there is provided quantity to equal basic pixel list switch separately that a series of different time series pulse signals of line number in same row drives different rows respectively, wherein in same row, two switches of any a line are subject to the driving of same time series pulse signals.
10. according to claim 9 with the pixel circuit of thermistor array, it is characterized in that, nationality is by the time series pulse signals of a series of non-overlapping, disconnect again after making the switch of each row successively perform connection one section of Preset Time successively according to the order from first trip to footline, and in two time series pulse signals being supplied to the basic pixel unit of two row adjacent arbitrarily, drive the moment that the first logic state of the previous time series pulse signals of previous row basic pixel list breaker in middle terminates, and between the moment that after driving, a rear time series pulse signals of a line basic pixel list breaker in middle enters the first logic state, a predetermined time delay is set.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158886A (en) * | 2015-03-30 | 2016-11-23 | 中航（重庆）微电子有限公司 | Integrated morphology and pixel circuit with thermistor array |
| CN112362170A (en) * | 2020-09-14 | 2021-02-12 | 武汉鲲鹏微纳光电有限公司 | Infrared detector |
-
2015
- 2015-03-30 CN CN201520184416.3U patent/CN204809222U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158886A (en) * | 2015-03-30 | 2016-11-23 | 中航（重庆）微电子有限公司 | Integrated morphology and pixel circuit with thermistor array |
| CN112362170A (en) * | 2020-09-14 | 2021-02-12 | 武汉鲲鹏微纳光电有限公司 | Infrared detector |
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