CN204791189U - A intelligent image processing appearance for image boundary draws - Google Patents
A intelligent image processing appearance for image boundary draws Download PDFInfo
- Publication number
- CN204791189U CN204791189U CN201520519618.9U CN201520519618U CN204791189U CN 204791189 U CN204791189 U CN 204791189U CN 201520519618 U CN201520519618 U CN 201520519618U CN 204791189 U CN204791189 U CN 204791189U
- Authority
- CN
- China
- Prior art keywords
- circuit
- edge
- image
- image processing
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The utility model discloses an intelligent image processing appearance for image boundary draws, main by camera, AD converting circuit and be used for carrying on the FPGA chip that image boundary extracted and form, AD converting circuit, AD converting circuit connection FPGA chip are connected to the camera, be provided with reduction vision circuit, image filter circuit, edge enhancement circuit, edge detection circuit and marginal positioning circuit at the FPGA on chip, reduction image circuit connection image filter circuit, image filter circuit connects the edge enhancement circuit, edge enhancement circuit connection edge detection circuit, edge detection circuit connection edge positioning circuit, reduction image circuit connection edge enhancement 3, for the violent region of grey level change of realizing remaining the image at the digital image processing in -process, the treatment circuit that adopts the FPGA chip to draw as image boundary not only reaches the positioning accuracy who improves the image, simultaneously the data volume among the reducible image subsequent processing.
Description
Technical field
The utility model relates to technical field of image processing, specifically, is a kind of intelligent image processing instrument for Edge extraction.
Background technology
Edge extracting, refers in Digital Image Processing, for a process of picture profile.For boundary, the place that gray-value variation is more violent, is just defined as edge.Namely flex point, flex point refers to the point that function generation concavity and convexity changes.Second derivative is the place of zero.Be not first order derivative, because first order derivative is zero, expression is extreme point.
Edge definition: the place (place that image intensity value change is the most violent) that variation of image grayscale rate is maximum.The discontinuous edge caused that gradation of image changes at surface normal.It is generally acknowledged that edge extracting to retain the violent region of the grey scale change of image, this mathematically, method is exactly differential (being exactly difference for digital picture) the most intuitively, in the angle of signal transacting, alternatively with Hi-pass filter, i.e. reserved high-frequency signal.
FPGA(Field-ProgrammableGateArray), i.e. field programmable gate array, it is the product further developed on the basis of the programming devices such as PAL, GAL, CPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, overcomes again the shortcoming that original programming device gate circuit number is limited.
Utility model content
The purpose of this utility model is to design a kind of intelligent image processing instrument for Edge extraction, for the region that the grey scale change realizing retaining image in Digital Image Processing process is violent, adopt fpga chip as the treatment circuit of Edge extraction, not only reach the positioning precision improving image, the data volume in pictures subsequent process can be reduced simultaneously.
The utility model is achieved through the following technical solutions: a kind of intelligent image processing instrument for Edge extraction, primarily of video camera, A/D convertor circuit and the fpga chip composition for carrying out Edge extraction, described video camera connects A/D convertor circuit, and described A/D convertor circuit connects fpga chip; Reduction vision circuit, image filtering circuit, edge intensifier circuit, edge detect circuit and edge local circuit is provided with in described fpga chip, described reduction vision circuit connection layout is as filtering circuit, described image filtering circuit connects edge intensifier circuit, described edge intensifier circuit connects edge detect circuit, described edge detect circuit connects edge positioning circuit, and described reduction vision circuit connects A/D convertor circuit.
For better realizing the utility model further, also comprise dsp chip, described dsp chip connects edge positioning circuit.
For better realizing the utility model further, also comprise DA change-over circuit, described DA change-over circuit connects dsp chip.
For better realizing the utility model further, described dsp chip is also connected by I2C bus with between A/D convertor circuit and DA change-over circuit.
For better realizing the utility model further, also comprise display, described display connects DA change-over circuit.
For better realizing the utility model further, the display screen of described display adopts LED LCDs.
For better realizing the utility model further, also comprise memory circuitry, described memory circuitry connects dsp chip.
For better realizing the utility model further, described memory circuitry comprises the random access memory and FLASH memory that are connected with dsp chip respectively.
The utility model compared with prior art, has the following advantages and beneficial effect:
(1) the utility model is realize retaining the violent region of the grey scale change of image in Digital Image Processing process, adopt fpga chip as the treatment circuit of Edge extraction, not only reach the positioning precision improving image, the data volume in pictures subsequent process can be reduced simultaneously.
(2) the utility model adopts fpga chip as Edge extraction treatment circuit, and its efficient data processing performance, effectively can improve the serviceability of whole instrument, and effectively improves the stability of image real time transfer and ageing.
(3) the utility model utilizes FPGA can form the speed advantage of Edge extraction process in the feature of hardware parallel organization and pipeline organization, can meet the requirement of view synthesis completely, have very strong practicality.
(4) the utility model processing mode of adopting multiple memorizers to combine in dsp chip processing links, further can improve the handling property of whole instrument, and can reach the object of effectively backup, evidence-based when late time data is called.
Accompanying drawing explanation
Fig. 1 is theory diagram of the present utility model.
Fig. 2 is the schematic block circuit diagram arranged in fpga chip described in the utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but embodiment of the present utility model is not limited thereto.
Embodiment 1:
The utility model proposes a kind of intelligent image processing instrument for Edge extraction, for the region that the grey scale change realizing retaining image in Digital Image Processing process is violent, adopt fpga chip as the treatment circuit of Edge extraction, not only reach the positioning precision improving image, the data volume in pictures subsequent process can be reduced simultaneously, as shown in Figure 1, primarily of video camera, A/D convertor circuit and the fpga chip composition for carrying out Edge extraction, described video camera connects A/D convertor circuit, and described A/D convertor circuit connects fpga chip; Reduction vision circuit, image filtering circuit, edge intensifier circuit, edge detect circuit and edge local circuit is provided with in described fpga chip, described reduction vision circuit connection layout is as filtering circuit, described image filtering circuit connects edge intensifier circuit, described edge intensifier circuit connects edge detect circuit, described edge detect circuit connects edge positioning circuit, and described reduction vision circuit connects A/D convertor circuit.
The utility model is carried, after powering on, video camera is transferred in fpga chip after the image of shooting is converted to digital signal by A/D convertor circuit, Edge extraction process is completed in fpga chip, when carrying out Edge extraction process, first by have A/D convertor circuit change after digital signal by reduce vision circuit carry out pre-service, then utilize image filtering circuit to carry out signal filtering, the process of finishing smooth image; Picture signal after filtering process is again transferred in edge intensifier circuit and adopts gradient operator to be treated to gradient image signal, then utilizes edge detect circuit to complete the threshold segmentation process of picture signal this gradient image signal; Finally in edge local circuit, be processed into edge second order value picture signal, process in order to subsequent conditioning circuit, due to the operation in edge extracting process, image position accuracy is improved, thus reduce the data volume in pictures subsequent process.
Further, for improving captured image definition, described video camera adopts ccd video camera or CCD camera.
Embodiment 2:
The present embodiment is at the enterprising one-step optimization in the basis of above-described embodiment, for better realizing the utility model further, as shown in Figure 1, be arranged to following structure: also comprise dsp chip, described dsp chip connects edge positioning circuit, will be transferred in dsp chip and carry out image procossing further after being processed into edge second order value picture signal, so as the later stage can high-fidelity be reduced into former figure, there will not be image fault, also can ensure the data processing performance of whole processing instrument simultaneously.
Embodiment 3:
The present embodiment is at the enterprising one-step optimization in the basis of above-described embodiment, for better realizing the utility model further, as shown in Figure 1, is arranged to following structure: also comprise DA change-over circuit, and described DA change-over circuit connects dsp chip; After dsp chip process, carrying out digital-to-analog conversion based on Hi-Fi picture signal by utilizing DA change-over circuit, can complete image restoring be carried out with connection circuit after an action of the bowels.
Embodiment 4:
The present embodiment is at the enterprising one-step optimization in the basis of embodiment 3, for better realizing the utility model further, as shown in Figure 1, be arranged to following structure: described dsp chip is also connected by I2C bus with between A/D convertor circuit and DA change-over circuit, when optimum configurations or the debugging of carrying out DA change-over circuit and A/D convertor circuit, dsp chip utilizes I2C bus to carry out parameter testing or setting to DA change-over circuit and A/D convertor circuit.
Embodiment 5:
The present embodiment is the enterprising one-step optimization in basis in embodiment 3 or 4, for better realizing the utility model further, as shown in Figure 1, be arranged to following structure: also comprise display, described display connects DA change-over circuit, analog picture signal after DA conversion will be undertaken being reduced to image by display and by image by real-time the showing of the screen on display, watch in time knowing in order to user.
Embodiment 6:
The present embodiment is at the enterprising one-step optimization in the basis of above-described embodiment, for better realizing the utility model further, the display screen of described display adopts LED LCDs, adopt LED LCDs effectively can reduce energy loss, the volume of total can be reduced simultaneously, make it have more portability.
Embodiment 7:
The present embodiment is at the enterprising one-step optimization in the basis of embodiment 2-6 any embodiment, for better realizing the utility model further, as shown in Figure 1, be arranged to following structure: also comprise memory circuitry, described memory circuitry connects dsp chip, when dsp chip carries out data processing, effectively can carry out data processing by combined memory circuit, thus improve the performance of data processing.
Embodiment 8:
The present embodiment is at the enterprising one-step optimization in the basis of above-described embodiment, and for better realizing the utility model further, described memory circuitry comprises the random access memory and FLASH memory that are connected with dsp chip respectively; Described memory circuit comprises random access memory and FLASH memory, and the FLASH memory extended out adopts SPR4096A, is mainly used to the data message that storage system needs.SPR4096AFJash has following feature: the storage space of 512K × 8; The SRAM of embedded 4K × 8; Outer CPU can visit Flash/SRAM by serial line interface or 8 bit parallel interfaces; The voltage range of I/O interface is 2.25 ~ 3.6V, and supports the battery saving mode of standby.Greatly can reduce the cost of whole processing instrument.In use, in data handling procedure, dsp chip effectively can complete exchanges data in conjunction with random access memory and FLASH memory, to reach good data process effects.
Described random access memory adopts dynamic storage or/and static memory; The feature of static memory (SRAM) is that operating rate is fast, as long as power supply is not removed, the information of write SRAM would not disappear, do not need refresh circuit, not destroying when reading the information originally deposited simultaneously, can repeatedly read once write, but integrated level is lower, power consumption is comparatively large, makes cache memory (Cache) and use in the utility model.DRAM is dynamic RAM (DynamicRandomAccessMemory), it utilizes the grid of field effect transistor to the distributed capacitance between its substrate to the information of preserving, with the number of stored charge, namely the height of capacitance terminal voltage represents " 1 " and " 0 ", uses in the utility model as primary memory.
The above; it is only preferred embodiment of the present utility model; not do any pro forma restriction to the utility model, every any simple modification, equivalent variations done above embodiment according to technical spirit of the present utility model, all falls within protection domain of the present utility model.
Claims (10)
1. the intelligent image processing instrument for Edge extraction, it is characterized in that: primarily of video camera, A/D convertor circuit and the fpga chip composition for carrying out Edge extraction, described video camera connects A/D convertor circuit, and described A/D convertor circuit connects fpga chip; Reduction vision circuit, image filtering circuit, edge intensifier circuit, edge detect circuit and edge local circuit is provided with in described fpga chip, described reduction vision circuit connection layout is as filtering circuit, described image filtering circuit connects edge intensifier circuit, described edge intensifier circuit connects edge detect circuit, described edge detect circuit connects edge positioning circuit, and described reduction vision circuit connects A/D convertor circuit.
2. a kind of intelligent image processing instrument for Edge extraction according to claim 1, is characterized in that: also comprise dsp chip, and described dsp chip connects edge positioning circuit.
3. a kind of intelligent image processing instrument for Edge extraction according to claim 2, is characterized in that: also comprise DA change-over circuit, and described DA change-over circuit connects dsp chip.
4. a kind of intelligent image processing instrument for Edge extraction according to claim 3, is characterized in that: described dsp chip is also connected by I2C bus with between A/D convertor circuit and DA change-over circuit.
5. a kind of intelligent image processing instrument for Edge extraction according to claim 3 or 4, is characterized in that: also comprise display, and described display connects DA change-over circuit.
6. a kind of intelligent image processing instrument for Edge extraction according to claim 5, is characterized in that: the display screen of described display adopts LED LCDs.
7. a kind of intelligent image processing instrument for Edge extraction according to claim 5, is characterized in that: also comprise memory circuitry, and described memory circuitry connects dsp chip.
8. a kind of intelligent image processing instrument for Edge extraction according to claim 7, is characterized in that: described memory circuitry comprises the random access memory and FLASH memory that are connected with dsp chip respectively.
9. a kind of intelligent image processing instrument for Edge extraction according to Claims 2 or 3 or 4 or 6, is characterized in that: also comprise memory circuitry, and described memory circuitry connects dsp chip.
10. a kind of intelligent image processing instrument for Edge extraction according to claim 9, is characterized in that: described memory circuitry comprises the random access memory and FLASH memory that are connected with dsp chip respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520519618.9U CN204791189U (en) | 2015-07-17 | 2015-07-17 | A intelligent image processing appearance for image boundary draws |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520519618.9U CN204791189U (en) | 2015-07-17 | 2015-07-17 | A intelligent image processing appearance for image boundary draws |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204791189U true CN204791189U (en) | 2015-11-18 |
Family
ID=54531193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520519618.9U Expired - Fee Related CN204791189U (en) | 2015-07-17 | 2015-07-17 | A intelligent image processing appearance for image boundary draws |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204791189U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107945197A (en) * | 2017-12-20 | 2018-04-20 | 南通使爱智能科技有限公司 | A kind of intelligent image processing instrument for Edge extraction |
-
2015
- 2015-07-17 CN CN201520519618.9U patent/CN204791189U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107945197A (en) * | 2017-12-20 | 2018-04-20 | 南通使爱智能科技有限公司 | A kind of intelligent image processing instrument for Edge extraction |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN205140493U (en) | Control display screen carries out device of screen switching anyhow | |
| EP3161793B1 (en) | Adaptive partition mechanism with arbitrary tile shape for tile based rendering gpu architecture | |
| CN103679134B (en) | A kind of to sea Infrared Targets imaging identification device | |
| WO2008060961A3 (en) | Pixel cache for 3d graphics circuitry | |
| CN105243399B (en) | A kind of method and apparatus that realizing image convolution, the method and apparatus for realizing caching | |
| CN205608814U (en) | Augmented reality system based on zynq software and hardware concurrent processing | |
| CN202615038U (en) | Wireless intelligent microscopic system terminal | |
| US20220317964A1 (en) | Display method for interactive system, interactive system, and electronic device | |
| CN103778606A (en) | Image processing method and related devices | |
| CN202261557U (en) | System of utilizing cloud storage via wireless WIFI technology by digital camera | |
| CN204791189U (en) | A intelligent image processing appearance for image boundary draws | |
| CN203787060U (en) | Display screen test device provided with plurality of VGA output interfaces | |
| CN104915311A (en) | Integrated information processor for infrared image | |
| CN109907555B (en) | Solar power supply type cabinet | |
| Tagliavini et al. | Always-on motion detection with application-level error control on a near-threshold approximate computing platform | |
| CN107945197A (en) | A kind of intelligent image processing instrument for Edge extraction | |
| CN204374982U (en) | Based on the intelligent acquisition equipment of image authentication code technology | |
| CN103854625B (en) | Based on liquid crystal indicator and the display packing thereof of CPLD | |
| CN103093175A (en) | Face identification system on chip based on field programmable gate array (FPGA) | |
| CN203596060U (en) | Canteen card swiping machine based on machine vision | |
| Khan et al. | Universal bridge interface for DVP-compatible image sensors | |
| CN207854046U (en) | A kind of laser range finder and its laser ranging display control program | |
| CN202709292U (en) | High-simulation fireplace | |
| CN204217075U (en) | A kind of Computerized image processing system adopting intelligent identification technology | |
| CN206849098U (en) | A kind of human resource management model |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151118 Termination date: 20160717 |