CN204791027U - Safe solid state hard drives controller - Google Patents
Safe solid state hard drives controller Download PDFInfo
- Publication number
- CN204791027U CN204791027U CN201520468502.7U CN201520468502U CN204791027U CN 204791027 U CN204791027 U CN 204791027U CN 201520468502 U CN201520468502 U CN 201520468502U CN 204791027 U CN204791027 U CN 204791027U
- Authority
- CN
- China
- Prior art keywords
- controller
- enciphering
- module
- deciphering
- flash memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The utility model relates to a safe solid state hard drives controller has microprocessor, memory, flash memory, buffer memory and memory controller and the many channel controller of flash memory, says at each sweetgum fruit of the many channel controller of flash memory that leading one -level adds / the deciphering module, adds / decrypts the module and carry out bi -directional data transmission with many channel controller of flash memory and flash memory controller. The utility model discloses add / deciphering is efficient, does not occupy system resource, and transparent completely to the user, resource consumption is littleer, need not the loaded down with trivial details operation of user to it is safer, stable, reliable, but proclaimed in writing, ciphertext operation parallel operation.
Description
Technical field
The utility model relates to a kind of hard disk, specifically a kind of safe solid-state hard disk controller.
Background technology
Current general hard disc of computer is roughly divided into traditional mechanical hard disk and solid state hard disc, and solid state hard disc is more and more favored with advantages such as its high readwrite performance, super low-power consumption and volume are little.Solid state hard disc critical piece is divided into controller, NANDFlash and other appurtenances, and its middle controller is the control axis of whole solid state hard disc, determines function and the performance of solid state hard disc.At present, the solid state hard disc on market all adopts software enciphering/deciphering mode in data security, namely utilizes software to be transferred to solid state hard disc by after data enciphering/deciphering, and this mode shortcoming has the following aspects:
1. take computer system (CPU, internal memory, operating system etc.) resource;
2. enciphering/deciphering efficiency is low;
3. couple user is opaque, needs user to carry out loaded down with trivial details operation;
4. enciphering/deciphering software is once damage, and data just cannot correctly read;
At present, there is not been reported for the solid-state hard disk controller that can solve the problem.
Utility model content
Exist for solid-state hard disk controller in prior art and state the deficiencies such as poor stability, the technical problems to be solved in the utility model be to provide a kind of high security not occupying system resources, to the completely transparent safe solid-state hard disk controller of user.
For solving the problems of the technologies described above, the technical solution adopted in the utility model is:
The safe solid-state hard disk controller of the utility model, there is microprocessor, internal memory, flash memory, buffer memory and Memory Controller Hub and flash memory Multi Channel Controller, in each paths preposition one-level enciphering/deciphering module of flash memory Multi Channel Controller, enciphering/deciphering module and flash memory Multi Channel Controller and flash controller carry out bidirectional data transfers.
Enciphering/deciphering module comprises: temporal cache unit, control circuit module, data security module and key management module, wherein temporal cache unit and flash memory Multi Channel Controller and control circuit module carry out bidirectional data transfers, temporal cache unit receives from the be-encrypted data of flash memory Multi Channel Controller, and control circuit module is called be-encrypted data and delivered to data security module and be encrypted; The key of key management module store and management enciphering/deciphering module, exports key data to data security module.
Data security module is made up of enciphering/deciphering processing unit and two dual-port buffer cells, and wherein enciphering/deciphering processing unit realizes symmetric encipherment algorithm; Two dual-port buffer cells and enciphering/deciphering processing unit carry out bidirectional data transfers, and the data after encryption send to flash controller by dual-port buffer cell through local bus, are stored in flash memory.
Enciphering/deciphering module is built in flash controller.
The utility model has following beneficial effect and advantage:
1. hardware encryption/decryption module is built in high speed solid hard disk controller by the utility model, makes it the solid-state hard disk controller chip becoming a kind of high security, and this controller chip enciphering/deciphering efficiency is high, and not occupying system resources is completely transparent to user.
2. the utility model adopts multi-stage pipeline arrangement to realize the real-time encrypted of data and deciphering, compares software enciphering and deciphering algorithm, and hardware approach speed is faster, and resource consumption is less, without the need to user's troublesome operation, and safer, stable, reliable.
3. the utility model adopts multi-stage pipeline Parallel Design, have 64 flash memory passages, built-in one-level enciphering/deciphering module in each passage flash controller, the data of encryption are needed to carry out enciphering/deciphering process through enciphering/deciphering module, do not need the data of encrypting directly to give flash controller to store, expressly, ciphertext operation can parallel work-flow.
Accompanying drawing explanation
Fig. 1 is the utility model solid-state hard disk controller chip logic structural drawing;
Fig. 2 is the built-in enciphering/deciphering module's logic structure figure of the utility model solid-state hard disk controller chip.
Embodiment
Below in conjunction with Figure of description, the present invention is further elaborated.
As shown in Figure 1, the safe solid-state hard disk controller of the utility model, there is microprocessor, internal memory, flash memory, buffer memory and Memory Controller Hub and flash memory Multi Channel Controller, in each paths preposition one-level enciphering/deciphering module of flash memory Multi Channel Controller, enciphering/deciphering module and flash memory Multi Channel Controller and flash controller carry out bidirectional data transfers.
As shown in Figure 2, enciphering/deciphering module comprises: temporal cache unit, control circuit module, data security module and key management module, wherein temporal cache unit and flash memory Multi Channel Controller and control circuit module carry out bidirectional data transfers, temporal cache unit receives from the be-encrypted data of flash memory Multi Channel Controller, and control circuit module is called be-encrypted data and delivered to data security module and be encrypted; The key of key management module store and management enciphering/deciphering module, exports key data to data security module.
Data security module is made up of enciphering/deciphering processing unit and two dual-port buffer cells, and wherein enciphering/deciphering processing unit realizes symmetric encipherment algorithm, comprises DES, 3DES, AES; Two dual-port buffer cells and enciphering/deciphering processing unit carry out bidirectional data transfers, and the data after encryption send to flash controller by dual-port buffer cell through local bus, are stored in flash memory.
The utility model is each road flash memory (NANDFlash) passage preposition one-level enciphering/deciphering module at solid-state hard disk controller, and enciphering/deciphering module is formed primarily of following a few part:
(1) temporal cache unit (TMU): its effect is storage control signal and data stream, and is forwarded in the appropriate time, to ensure the sequential integrality of encryption system.
(2) control circuit module (CCM): this module is used for the enciphering/deciphering process of control data stream and enciphering/deciphering operation, is the nerve center of whole system.
(3) data security module: being made up of enciphering/deciphering processing unit and two dual-port buffer cells, is the core component realizing fixed disk data enciphering.Wherein:
(31) enciphering/deciphering unit (E/DU): realize conventional symmetric encipherment algorithm, comprise DES, 3DES, AES.
(32) dual-port buffer cell (DMU): be used for data cached, the data stream displacement from encryption port/deciphering port is converted to one group of to be added/data decryption input of enciphering/deciphering unit simultaneously, or adds/separate data by one of enciphering/deciphering unit group and export to be shifted and be converted to the data stream going to deciphering port/encryption port.
(4) key management module (KMM): the key of this module in charge store and management enciphering/deciphering module.
The utility model adopts multi-stage pipeline Parallel Design, the present embodiment has 64 flash memory passages, built-in one-level enciphering/deciphering module in each passage flash controller, the data of encryption are needed to carry out enciphering/deciphering process through enciphering/deciphering module, do not need the data of encrypting directly to give flash controller to store, expressly, ciphertext operation can parallel work-flow.
The course of work of the present utility model is as follows:
As shown in Figure 1, data to be stored are sent to solid-state hard disk controller local bus by hard-disk interface by main frame, after solid-state hard disk controller microprocessor receives data, decoding instruction, analyze data, determine which data needs encryption, and data to be stored are sent to solid-state hard disk controller Memory Controller Hub, by algorithm, solid-state hard disk controller determines which flash chip is which data be stored in, enciphering/deciphering module is sent to by needing the data of encryption, data without the need to encryption directly send to flash controller, finally send to flash memory storage, this is the whole flow process that data store.Digital independent therewith process is contrary, and what system host was sent to microprocessor is the control signal reading data, and what receive is the data needing to read.
As shown in Figure 2, be-encrypted data is sent by local bus by flash memory Multi Channel Controller, and be-encrypted data enters temporal cache unit (TMU) and calls for control circuit module (CCM).Control circuit module (CCM) calls be-encrypted data, then deliver to enciphering/deciphering unit (E/DU) to be encrypted, in ciphering process, key management module provides key for encrypting, data after encryption deliver to local bus by dual-port buffer cell (DMU), send to flash memory to store, this is complete data encryption process.During data decryption, process is contrary with encryption, what local bus sent enter, and temporal cache unit (TMU) calls for control circuit module (CCM), then deliver to enciphering/deciphering unit (E/DU) to be decrypted, deliver to local bus by dual-port buffer cell (DMU) after encryption, send to flash memory Multi Channel Controller.
Claims (4)
1. a safe solid-state hard disk controller, there is microprocessor, internal memory, flash memory, buffer memory and Memory Controller Hub and flash memory Multi Channel Controller, it is characterized in that: in each paths preposition one-level enciphering/deciphering module of flash memory Multi Channel Controller, enciphering/deciphering module and flash memory Multi Channel Controller and flash controller carry out bidirectional data transfers.
2. by safe solid-state hard disk controller according to claim 1, it is characterized in that: enciphering/deciphering module comprises: temporal cache unit, control circuit module, data security module and key management module, wherein temporal cache unit and flash memory Multi Channel Controller and control circuit module carry out bidirectional data transfers, temporal cache unit receives from the be-encrypted data of flash memory Multi Channel Controller, and control circuit module is called be-encrypted data and delivered to data security module and be encrypted; The key of key management module store and management enciphering/deciphering module, exports key data to data security module.
3., by safe solid-state hard disk controller according to claim 2, it is characterized in that: data security module is made up of enciphering/deciphering processing unit and two dual-port buffer cells, and wherein enciphering/deciphering processing unit realizes symmetric encipherment algorithm; Two dual-port buffer cells and enciphering/deciphering processing unit carry out bidirectional data transfers, and the data after encryption send to flash controller by dual-port buffer cell through local bus, are stored in flash memory.
4., by safe solid-state hard disk controller according to claim 1, it is characterized in that: enciphering/deciphering module is built in flash controller.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201520468502.7U CN204791027U (en) | 2015-07-02 | 2015-07-02 | Safe solid state hard drives controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201520468502.7U CN204791027U (en) | 2015-07-02 | 2015-07-02 | Safe solid state hard drives controller |
Publications (1)
Publication Number | Publication Date |
---|---|
CN204791027U true CN204791027U (en) | 2015-11-18 |
Family
ID=54531031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201520468502.7U Expired - Fee Related CN204791027U (en) | 2015-07-02 | 2015-07-02 | Safe solid state hard drives controller |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN204791027U (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106650511A (en) * | 2016-02-01 | 2017-05-10 | 天固科技(杭州)有限公司 | Scheme for improving encryption performance of encryption system |
CN110163011A (en) * | 2019-05-14 | 2019-08-23 | 北京计算机技术及应用研究所 | A kind of high-speed secure hard disk design method |
TWI712889B (en) * | 2018-08-21 | 2020-12-11 | 日商東芝記憶體股份有限公司 | Memory device and program |
CN112084138A (en) * | 2020-08-21 | 2020-12-15 | 杭州电子科技大学 | SoC (system on chip) security disk control chip architecture design method for trusted storage |
CN112256602A (en) * | 2020-10-22 | 2021-01-22 | 方一信息科技(上海)有限公司 | PCIe SSD controller, data storage system and data transmission method |
-
2015
- 2015-07-02 CN CN201520468502.7U patent/CN204791027U/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106650511A (en) * | 2016-02-01 | 2017-05-10 | 天固科技(杭州)有限公司 | Scheme for improving encryption performance of encryption system |
TWI712889B (en) * | 2018-08-21 | 2020-12-11 | 日商東芝記憶體股份有限公司 | Memory device and program |
CN110163011A (en) * | 2019-05-14 | 2019-08-23 | 北京计算机技术及应用研究所 | A kind of high-speed secure hard disk design method |
CN112084138A (en) * | 2020-08-21 | 2020-12-15 | 杭州电子科技大学 | SoC (system on chip) security disk control chip architecture design method for trusted storage |
CN112256602A (en) * | 2020-10-22 | 2021-01-22 | 方一信息科技(上海)有限公司 | PCIe SSD controller, data storage system and data transmission method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN204791027U (en) | Safe solid state hard drives controller | |
CN102073808B (en) | Method for encrypting and storing information through SATA interface and encryption card | |
CN204066121U (en) | A kind of PCI-E encrypted card | |
CN102737270B (en) | A kind of bank intelligent card chip secure coprocessor based on domestic algorithm | |
CN101854353A (en) | Multi-chip parallel encryption method based on FPGA | |
CN109240952B (en) | High-speed data encryption NVMe-SATA converter circuit | |
CN104217180B (en) | A kind of encryption storage dish | |
CN107256363A (en) | A kind of high-speed encryption and decryption device being made up of encryption/decryption module array | |
US20100128874A1 (en) | Encryption / decryption in parallelized data storage using media associated keys | |
US10104342B2 (en) | Techniques for secure provisioning of a digital content protection scheme | |
CN101540191B (en) | Real-time encrypted U disk and high speed encryption-decryption method | |
CN115549911B (en) | Encryption and decryption system, method, processor and server | |
CN112084138A (en) | SoC (system on chip) security disk control chip architecture design method for trusted storage | |
CN101729242A (en) | Method and device for generating symmetric block ciphers | |
CN203930840U (en) | A kind of hardware encryption card | |
CN107278305B (en) | Digital rights management playback fault avoidance | |
CN103777918A (en) | Hardware accelerator | |
CN103077362B (en) | There is the GPIO IP kernel of security mechanism | |
CN101482909B (en) | Enciphering algorithm module accelerating machine and its data high-speed encryption and decryption method | |
CN214122946U (en) | High-speed national cryptographic algorithm password card based on FPGA | |
CN203982391U (en) | A kind of PCI-E encrypted card with network interface | |
CN102110066B (en) | Tax-control encryption card control method | |
US10326587B2 (en) | Ultra-lightweight cryptography accelerator system | |
CN202394238U (en) | High-speed encryption/decryption system utilizing graphic processor parallel computation | |
US20220416997A1 (en) | Handling unaligned transactions for inline encryption |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151118 Termination date: 20180702 |
|
CF01 | Termination of patent right due to non-payment of annual fee |