CN204613395U - A kind of digital signal processor for ship-navigation radar - Google Patents

Abstract

The utility model relates to radar signal processing field, be specifically related to a kind of digital signal processor for ship-navigation radar, take the version of " FPGA+DSP ", give full play to the feature of the powerful logic control ability of FPGA and DSP igh-speed wire-rod production line ability, processing power is stronger compared with traditional ship-navigation radar digital signal processor, memory capacity is larger, interface is more flexible, there is extensibility; Add ethernet communication function, radar digital signal processing machine can be made to move to the upper unit of marine radar by the mode of ethernet communication, radar return data after having processed transfer to the display terminal of radar lower unit eventually through Ethernet, effectively prevent signal attenuation and interference problem that traditional boats and ships radar signal processor occurs during receiving video signals under long distance; Improve for existing ship-navigation radar digital signal processing method, anti-interference stronger with clutter suppression capability, signal transacting better effects if.

Description

A kind of digital signal processor for ship-navigation radar

Technical field

The utility model relates to radar signal processing field, is specifically related to a kind of digital signal processor for ship-navigation radar.

Background technology

Radar signal processor is the important component part of radar system, mainly completes the function sampled to the vision signal of radar receiver output, process and transmit.Early stage radar uses mimic channel to process signal, not only complex structure, and circuit itself also very easily receives interference.Along with the development of digital technology, Radar Signal Processing turns by digital circuit.Because the environment for use of radar and purposes are not quite similar, the structure of radar signal processor and the function that will complete also difference thereupon.Ship-navigation radar is as the one application of radar in naval technology, there is provided the functions such as navigation, collision avoidance can to underway ship, but the ship-navigation radar of current domestic use mostly is external product, because external long-term correlation technique of blocking causes homemade goods slower development, therefore study the special digital signal processor being applied to ship-navigation radar and the domestic ship-navigation radar development of propelling is had very important significance.

Traditional radar digital signal processing machine adopts DSP to realize, this Technical comparing is ripe, as adopted 3 dsp chips as the core of radar signal processor in document " Design of Radar Signal Processor based on ADSP_TS101 chip ", completing the signal processing function such as digital pulse compression, moving target detect and controlling the operation of whole radar system.But DSP instruction is more suitable for implementation algorithm instead of logic control, the versatility of its external interface is poor, to seem underaction to the control of radar system.Maritime Affairs University Of Dalian Li Bo devises a kind of marine radar digital signal processor based on FPGA, its all functions are realized by FPGA, although FPGA has the incomparable logic control ability of DSP, but the complexity of FPGA on algorithm realization is higher than general processor, and also high to the requirement of resource in sheet when realizing complicated algorithm, need the fpga chip of middle and high end to realize, so just make the construction cycle long, cost is high, is unfavorable for realizing through engineering approaches.

In addition, existing ship-navigation radar digital signal processor is designed in the lower unit (comprising signal processor and display terminal) of radar, receive the vision signal exported from unit on radar (comprising radar transmitter, receiver, antenna) to process, due to the environment for use that marine radar is special, on radar, unit and lower unit are often at a distance of more than ten meters, this method for designing just needs to transmit simulating signal, inevitably causes signal attenuation and is subject to various disturbing effect.

Utility model content

Technical purpose of the present utility model is to overcome the problems referred to above, a kind of digital signal processor for ship-navigation radar is provided, realize the Systematical control of ship-navigation radar and the function of signal transacting, and improve for existing ship-navigation radar signal processing method, to reach better effect, realize digital signal processor to combine with unit on radar simultaneously, overcome traditional ship-navigation radar vision signal from upper unit to lower unit transmitting procedure in the signal attenuation that causes and interference problem.

To achieve these goals, the technical scheme that the utility model adopts is: a kind of digital signal processor for ship-navigation radar, it is characterized in that, comprise A/D sampling thief, synchronous DRAM SDRAM1, static RAM SRAM, nonvolatile memory FLASH, Ethernet interface, programmable logic device (PLD) FPGA, digital signal processor DSP, ethernet controller, expansion interface and synchronous DRAM SDRAM2; The digital signal output end of A/D sampling thief and sampling clock input end are connected with the data terminal of programmable logic device (PLD) FPGA and output terminal of clock respectively, and the data terminal of synchronous DRAM SDRAM1 is connected with address end with the data terminal of programmable logic device (PLD) FPGA respectively with address end; The data terminal of static RAM SRAM is connected with address end with the data terminal of programmable logic device (PLD) FPGA respectively with address end, and the data terminal of ethernet controller is connected with control end with the data terminal of programmable logic device (PLD) FPGA respectively with control end; Ethernet interface is connected with the output terminal of ethernet controller, and expansion interface is connected with the GPIO interface of programmable logic device (PLD) FPGA; The data terminal of nonvolatile memory FLASH is connected with address end with the data terminal of digital signal processor DSP respectively with address end, and the data terminal of synchronous DRAM SDRAM2 is connected with address end with the data terminal of digital signal processor DSP respectively with address end; Programmable logic device (PLD) FPGA is connected with the EMIF bus interface of digital signal processor DSP by DSP.

Described A/D sampling thief is converted to digital signal to the radar return video signal sampling that ship-navigation radar receiver exports; Described digital signal processor, near ship-navigation radar receiver, adopts Ethernet transmission mode to send data to the display terminal of radar lower unit.

Described ethernet controller is used for the driving of ethernet communication, comprises packing and the decompress(ion) of data; Described Ethernet interface is used as the communication interface of digital signal processor and display terminal.

Described programmable logic device (PLD) FPGA is used for the logic of marine radar system and sequential control, signals collecting, transmission and Signal Pretreatment; The EMIF interface that digital signal processor DSP is carried by it is connected with memory storage SDRAM 2, FLASH and FPGA (for the process of radar signal, described radar signal is the signal exported after FPGA pre-service).

Described synchronous DRAM SDRAM1 is used for the good radar return data of stores processor and stores; The data that described static RAM SRAM exports for storing A/D sampling thief, and realize ping-pong operation when data are transmitted with the fifo module of FPGA inside; Described synchronous DRAM SDRAM2 is for storing pending radar return data; Described nonvolatile memory FLASH is for storing the user program code of dsp operation.

Described A/D sampling thief is made up of SMA radio-frequency joint, radio frequency transmission transformer, A/D chip; Vision signal enters the input end of radio frequency transmission transformer through SMA radio-frequency joint, output difference sub-signal after transformer conversion, the clock signal of A/D chip is provided by the clock module of programmable logic device (PLD) FPGA inside, adds radio-frequency transformer (RFT) (clock signal is converted into differential signal) between the output terminal of clock and the input end of clock of A/D chip of FPGA; The data terminal of A/D chip is connected with FPGA.

For a digital signal processing method for ship-navigation radar, it is characterized in that, comprise the steps:

(1) first target azimuth angle is calculated, then carry out automatic noise gate process;

(2) judge whether that needing to carry out co-channel interference suppresses process, suppresses step as needs then carry out co-channel interference, otherwise enters step (3);

(3) judge whether to need ocean clutter cancellation process, as needs then carry out ocean clutter cancellation step, otherwise terminate.

Aforesaid a kind of digital signal processing method for ship-navigation radar, also comprises the steps:

(4) judge whether to need precipitation clutter to suppress process, suppress process as needs then carry out precipitation clutter, otherwise enter step (5);

(5) judge whether to need tail to show, as needs then carry out tail display, otherwise terminate.Wherein step (4) and step (5) are prior art, and the utility model is not described in detail.

The detailed process calculated target azimuth angle of step (1) is as follows: connect bow detecting sensor output terminal by expansion interface, when antenna turns to bow position, sensor feedback signal inputs to programmable logic device FPGA, represents a circle scanning and starts; Setting antenna scanning speed is T _sc, the recurrence interval transmitted is T _τ, the orientation angles so residing for each target wherein n represents the n-th pulse counted from ship's head that target is positioned at;

The detailed process of the automatic noise gate process of step (1) is as follows: programmable logic device FPGA arranges noise statistics module, after the gain of each adjustment radar receiver, noise average is obtained, in this, as new noise gate according to the Received signal strength that radar produces when not transmitting.

The detailed process of step (2) is as follows: call IP kernel by FPGA and generate 3 RAM modules, by adjacent 3 recurrence interval T _τinterior echo data is successively stored in 3 RAM modules, suppress level block to produce corresponding threshold Q according to the suppression grade INT1 of setting or INT2 simultaneously, grade is wherein suppressed to preset in a program, regulate by radar display control terminal, then the data in co-channel interference signal detection module reading RAM and threshold value composition echoed signal matrix, remember that the echo data in first recurrence interval is x _n(n=0,1 ... n), the echo data in second recurrence interval is y _n(n=0,1 ... n), the echo data in the 3rd recurrence interval is z _n(n=0,1 ... n), then signal matrix is:

$\left[\begin{array}{cccc}{x}_1& x_2& \·\·\·\·\·\·& x_n\\ y_1& y_2& \·\·\·\·\·\·& y_n\\ z_1& z_2& \·\·\·\·\·\·& z_n\\ Q& Q& \·\·\·\·\·\·& Q\end{array}\right]$

Use monitoring matrix $\left[\begin{array}{cccc}1& -1& 0& -1\\ 0& 1& -1& -1\\ -1& 0& 1& -1\end{array}\right]$ Be multiplied with signal matrix, obtain matrix of consequence, matrix of consequence intermediate value is that positive respective signal is co-channel interference signal; The non-interference signal substituting of its adjacent periods of co-channel interference signal that co-channel interference signal cancellation module will detect, and by the data accumulation on the same range unit of radar in adjacent 3 recurrence intervals, wherein cumulative is exactly by x _n(n=0,1 ... n), y _n(n=0,1 ... n), z _n(n=0,1 ... n) data when n gets identical value are added, and can improve signal to noise ratio (S/N ratio) after cumulative, the data of output be cumulative after value.

The detailed process of step (3) is as follows: first by carrying out parametric statistics to N frame scan echo data before given radar, the value wherein after corresponding above-mentioned 3 pulse period accumulations of frame data.Draw the rayleigh distributed model of these data and the characteristic ginseng value of Wei Buer distributed model; Then parameter value is updated to respectively in rayleigh distributed and Wei Buer distribution probability density function;

Rayleigh distributed probability density function is:

$f\left(x\right)=\frac{x}{{\mathrm{\σ}}^2}\exp [-\frac{x^2}{2{\mathrm{\σ}}^2}],x>0$

In formula, x is sea clutter amplitude, and σ is sea clutter standard deviation, also referred to as form parameter;

Wei Buer distribution probability density function is:

$f\left(x\right)={\left(\frac{x}{q}\right)}^{p-1}\left(\frac{p}{q}\right)\exp [-{\left(\frac{x}{q}\right)}^2],x>0,p>0,q>0$

In formula, x is sea clutter amplitude, and q is scale parameter, and p is form parameter;

Obtain the data sequence of 2 kinds of distributions, then make comparisons with the distribution series of radar return data, select immediate distributed model, follow-up N+i frame radar return data and background are finally offseted process, wherein i=1 by the background offseted using this model as sea clutter, 2,3 Remember that follow-up N+i frame echo data sequence is f, background model sequence is y, obtain frequency spectrum function F and frequency spectrum function Y respectively, and then the power spectral density function calculating them is respectively P to echo data sequence and background model sequence as FFT _fand P _y, finally by F and Y, P _fwith P _ywork subtracts each other and offsets.

Compared with prior art, the utility model tool has the following advantages:

(1) the utility model takes the version of " FPGA+DSP ", gives full play to the feature of the powerful logic control ability of FPGA and DSP igh-speed wire-rod production line ability.FPGA completes logic to radar system and sequential control, signals collecting, transmission and Signal Pretreatment function, and DSP completes the relevant treatment to radar echo signal.The utility model processing power compared with traditional ship-navigation radar digital signal processor is stronger, memory capacity is larger, interface is more flexible, have extensibility.

(2) the utility model adds ethernet communication function, and ethernet communication has the features such as transfer rate is high, the long range propagation bit error rate is low.Radar digital signal processing machine can be made to move to the upper unit of marine radar by the mode of ethernet communication, radar return data after having processed transfer to the display terminal of radar lower unit eventually through Ethernet, effectively prevent signal attenuation and interference problem that traditional boats and ships radar signal processor occurs during receiving video signals under long distance.

(3) the utility model improves for existing ship-navigation radar digital signal processing method, anti-interference stronger with clutter suppression capability, signal transacting better effects if.

Accompanying drawing explanation

Fig. 1 is the basic composition block diagram of ship-navigation radar digital signal processor of the present utility model.

Fig. 2 is the groundwork schematic diagram of ship-navigation radar digital signal processor of the present utility model.

Fig. 3 is that the utility model high speed A/D sample circuit realizes block diagram.

Fig. 4 is that the EMIF bus interface that in the utility model, FPGA and DSP communicates realizes block diagram.

Fig. 5 is the Interface realization block diagram of the utility model high speed ethernet controller and FPGA.

Fig. 6 is ship-navigation radar digital signal processor PCB domain of the present utility model.

Fig. 7 is ship-navigation radar digital signal processor signal processing flow schematic diagram of the present utility model.

Fig. 8 is co-channel interference Restrainable algorithms realization flow schematic diagram in the utility model.

Fig. 9 is sea clutter Adaptive Suppression algorithm realization schematic flow sheet in the utility model.

Embodiment

The technical scheme realized for making the utility model, technical characteristic, reaching object and effect is easy to understand, below in conjunction with embodiment, setting forth the utility model further.

The digital signal processor for ship-navigation radar that the utility model provides, comprises high-speed a/d sampling thief, Fast Ethernet controller, Ethernet interface, high-speed synchronous dynamic RAM SDRAM1 and SDRAM2, high speed static random access memory SRAM, nonvolatile memory FLASH, programmable logic device (PLD) FPGA, digital signal processor DSP and expansion interface.FPGA and DSP combines by the utility model, both co-ordinations complete the function of radar system control and signal transacting, simultaneously by the receiver of signal processor near unit on radar, Ethernet transmission mode is adopted to send data to the display terminal of radar lower unit.

Described high-speed a/d sampling thief has 16 high resolving power, and sampling rate reaches 80MSPS, completes the video signal sampling exported ship-navigation radar receiver, radar echo signal is changed into digital signal.

Described Fast Ethernet controller completes the driving of ethernet communication, comprises packing and the decompress(ion) of data.

Described Ethernet interface is used as the communication interface of digital signal processor and display terminal.

Described programmable logic device (PLD) FPGA mainly completes logic to marine radar system and sequential control, signals collecting, transmission and Signal Pretreatment function.

Described high-speed synchronous dynamic RAM SDRAM1 completes and stores the radar return data handled well.

The data that described high speed static random access memory SRAM completes high-speed a/d sampling thief exports store, and realize ping-pong operation when data are transmitted with the fifo module of FPGA inside.

The EMIF interface that described digital signal processor DSP is carried by it is connected with external memory storage SDRAM 2, FLASH and FPGA, realizes communication each other, completes the signal transacting of marine radar.

Described high-speed synchronous dynamic RAM SDRAM2 completes pending radar return data and stores.

Described nonvolatile memory FLASH completes the storage of dsp operation code and user data.

Described expansion interface is used to provide the control interface of radar servo system, the expansion interface when input interface of bow input and follow-up function upgrading.

With reference to Fig. 1, the ship-navigation radar digital signal processor that the utility model provides, comprise high-speed a/d sampling thief (namely high-speed a/d C 1.), high-speed synchronous dynamic RAM SDRAM1 2., high speed static random access memory SRAM 3., nonvolatile memory FLASH 4., Ethernet interface 5., programmable logic device (PLD) FPGA 6., digital signal processor DSP 7., Fast Ethernet controller 8., expansion interface 9. with high-speed synchronous dynamic RAM SDRAM2 10..High-speed a/d sampling thief digital signal output end 1. and sampling clock input end are connected with programmable logic device (PLD) FPGA data terminal 6. and output terminal of clock respectively.High-speed synchronous dynamic RAM SDRAM1 data terminal 2. and address end are connected with address end with programmable logic device (PLD) FPGA data terminal 6. respectively.High speed static random access memory SRAM data terminal 3. and address end are connected with address end with programmable logic device (PLD) FPGA data terminal 6. respectively.Fast Ethernet controller data terminal 8. and control end are connected with control end with programmable logic device (PLD) FPGA data terminal 6. respectively.5. Ethernet interface is connected with Fast Ethernet controller output terminal 8..9. expansion interface is connected with programmable logic device (PLD) FPGA GPIO interface 6..Nonvolatile memory FLASH data terminal 4. and address end are connected with address end with digital signal processor DSP data terminal 7. respectively.High-speed synchronous dynamic RAM SDRAM2 data terminal 10. and address end are connected with address end with digital signal processor DSP data terminal 7. respectively.7. 6. programmable logic device (PLD) FPGA be connected by the EMIF bus interface of DSP with digital signal processor DSP.

In this example, high-speed a/d sampling thief adopts AD9460BSVZ-80 chip, it is a 16 single-chips sampling analog to digital converter, sampling hold circuit in a built-in sheet, the sampling rate of this device is up to 80MSPS, there is outstanding signal to noise ratio (S/N ratio), be applicable to adopting the instrument and meter of base band (<100MHz) and intermediate frequency, imaging of medical and radar receiver to apply.High-speed synchronous dynamic RAM SDRAM1 and SDRAM2 adopts IS42S16320B chip, and it has 16 BITBUS network, 512Mb memory capacity, can meet the storage of Large Volume Data.High speed static random access memory SRAM adopts IS61LV25616-10T chip, and it has 16 BITBUS network, 4Mb memory capacity.Nonvolatile memory FLASH adopts SST39VF1601 chip, and it has 16 BITBUS network, 64Mb memory capacity.Fast Ethernet controller adopts DM9000A chip, and it is a 10M/100M self-adaptation ethernet control chip, can meet the transmission of high-speed data.Ethernet interface adopts RJ45_HR911105A integrated transformer socket.Programmable logic device (PLD) FPGA adopts the EP4CE30F23C8N chip of altera corp, it has resource and GPIO in abundant sheet, meet the connection with various interface, digital signal processor DSP adopts the high-speed floating point type processor TMS320C6713BGDP300 chip of TI company, its dominant frequency reaches 300MHz, processing speed can reach 2400MIPS, has powerful signal handling capacity.

With reference to Fig. 2, ship-navigation radar digital signal processor basic functional principle of the present utility model is: radar echo signal is received by antenna and enters receiver, and receiver carries out frequency conversion, filtering, amplification and detection etc. to echoed signal and processes then output video signal.Digital signal processor receives the vision signal from radar receiver, wherein high-speed a/d sampling thief is sampled to signal, output digit signals controls its inner FIFO and high speed static random access memory SRAM to programmable logic device (PLD) FPGA, FPGA and realizes the radar return data buffer storage after to sampling and carry out ping-pong operation.Digital signal processor DSP is connected with FPGA by inner EMIF bus interface, read pending radar return data and buffer memory in high speed synchronous DRAM SDRAM2, then signal is processed, the data handled well are buffered to high speed synchronous DRAM SDRAM1, finally by Fast Ethernet, the data handled well are transferred to Radar Display Terminal.Wherein, programmable logic device (PLD) FPGA also completes the radar system controlling functions such as detection and the sequential control that transmits of control to radar servo system, bow signal.Because the utility model carries out data transmission by Ethernet, the position of digital signal processor just can move to the upper unit of marine radar, the signal attenuation can effectively avoiding traditional boats and ships radar signal processor to occur during receiving video signals under long distance and interference problem.

With reference to Fig. 3, in order to eliminate even-order harmonic component, suppressing common-mode noise source, playing the effect of system rejection to disturbance, the utility model high speed A/D sample circuit adopts the form of Differential Input.The vision signal that radar receiver exports is single-ended signal, therefore need first single-ended signal to be converted into differential signal, the utility model adopts ETC1-1-13TR radio frequency transmission transformer to realize this function, vision signal enters the input end of radio frequency transmission transformer through SMA radio-frequency joint, output difference sub-signal after transformer conversion.The clock signal of high-speed a/d sampling thief is provided by the clock module of programmable logic device (PLD) FPGA inside, A/D chip due to the utility model employing needs the clock signal of input difference form, therefore between the output terminal of clock and the input end of clock of A/D chip of FPGA, add ADT1-1WT radio-frequency transformer (RFT), realize clock signal by the single-ended conversion to differential signal.In addition, the data terminal DB [0..15] of A/D chip is connected with FPGA, and the data after sampling are sent into FPGA.The DCO end of A/D chip is connected with FPGA, in order to verify that whether sampling clock is consistent with input clock.OR end (i.e. the overrange signal output port of A/D chip) of A/D chip is connected with FPGA, and when AD input end signal voltage exceeds input range, this port exports and will become 1 from 0.

With reference to Fig. 4, in the utility model, digital signal processor DSP mainly carries out data communication by external memory interface EMIF and the FPGA of C6713B chip, and EMIF can realize the connection of DSP and different kinds of memory.Be connected with EMIF and FPGA, thus make FPGA platform serve as a coprocessor or high speed data transmission interface.EMIF bus interface mainly comprises FPDP TED, address port TEA, gating port TCE ,/WE ,/RE ,/OE, low byte enable port TBE, EMIF output terminal of clock mouth ECLKOUT and bus arbitration port ARDY ,/HOLD ,/HOLDA.

With reference to Fig. 5, because the external bus of the Fast Ethernet controller DM9000A of the utility model employing meets ISA standard.Therefore, directly realize being connected with FPGA by isa bus.Wherein, the FPDP that SDO [0..15] is ethernet controller, CS# is controller enable port, IOR# is controller read command port, IOW# is controller write order port, CMD is that control order form selects port, and INT is the interrupt request port of controller, and RESET# is the reseting port of controller.The existing driving to Fast Ethernet controller DM9000A is examined by the NIOS II of FPGA inside is soft.

With reference to Fig. 6, power supply, when Design PCB, is concentrated and is placed on apex zone, and carry out the filtering of π type by ship-navigation radar digital signal processor of the present utility model.High-speed a/d sample circuit is placed on left side and with FPGA near, shorten signal wire cabling, to be arranged in edges of boards easy to use for various expansion interface simultaneously.In addition, PCB of the present utility model adopts six Rotating fields, by being isolated by signals layer and providing the method for power supply complete separately and ground level to reduce signal cross-talk and electromagnetic interference (EMI).

With reference to Fig. 7, based on above-mentioned digital signal processor hardware platform, the utility model to marine radar echo signal processing flow process is: first calculate target azimuth angle, then automatic noise gate process is carried out, then judge whether that carrying out co-channel interference suppresses process, if need to carry out co-channel interference suppression, then run co-channel interference Restrainable algorithms, otherwise continue to judge whether to carry out squelch process, in like manner, continue to judge whether to carry out ocean clutter cancellation function, precipitation clutter inhibit feature and tail Presentation Function, the signal handled well the most at last transfers to display terminal by Fast Ethernet.The utility model improves for the part signal disposal route of traditional ship-navigation radar, specific as follows:

(1) target azimuth angle calculates.Tradition ship-navigation radar realizes the calculating to target azimuth by complicated circuits such as orientation code-disc, light activated elements, the utility model connects bow detecting sensor output terminal (bow detecting sensor is an external switching regulator Hall element) by expansion interface, when antenna turns to bow position, sensor will feed back a signal and input to programmable logic device FPGA, represent a circle scanning to start, in this example, suppose that antenna scanning speed is T _sc, the recurrence interval transmitted is T _τ, the orientation angles so residing for each target wherein n represents the n-th pulse counted from ship's head that target is positioned at.Method described in the utility model instead of traditional complicated circuit, not only realizes simply but also more accurate.

(2) noise gate process automatically.Comprise various noise signal in marine radar echoed signal, traditional ship-navigation radar, by radar echo signal and a certain noise gate being compared, regards as noise lower than this threshold value, otherwise, regard as echo signal.Can produce noise bounce owing to regulating during receiver gain, classic method cannot change noise gate automatically.The utility model devises a kind of noise gate disposal route automatically, noise statistics module is realized by programmable logic device FPGA, after each adjustment gain, obtain noise average according to the Received signal strength that radar produces when not transmitting, in this, as new noise gate.Compared with classic method, method described in the utility model has the adaptivity to noise.

(3) co-channel interference suppresses process.Traditional ship-navigation radar co-channel interference suppression method is also the shortcoming that partial target is removed while there is removal interference, and the utility model adopts a kind of three pulse correlation methods of improvement, and specific implementation as shown in Figure 8.In this example, call IP kernel by FPGA and generate 3 RAM modules, by the echo data in adjacent 3 recurrence intervals successively stored in, suppress level block to produce corresponding threshold Q according to selected suppression grade INT1 or INT2 simultaneously, the large young pathbreaker of Q value affects inhibition, wherein suppresses grade to preset in a program; Then the data in co-channel interference signal detection module reading RAM and threshold value composition echoed signal matrix, remember that the echo data in first recurrence interval is x _n(n=0,1 ... n), the echo data in second recurrence interval is y _n(n=0,1 ... n), the echo data in the 3rd recurrence interval is z _n(n=0,1 ... n), then signal matrix is:

$\left[\begin{array}{cccc}{x}_1& x_2& \&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;& x_n\\ y_1& y_2& \&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;& y_n\\ z_1& z_2& \&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;& z_n\\ Q& Q& \&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;& Q\end{array}\right]$

Use monitoring matrix $\left[\begin{array}{cccc}1& -1& 0& -1\\ 0& 1& -1& -1\\ -1& 0& 1& -1\end{array}\right]$ Be multiplied with signal matrix, obtain matrix of consequence, matrix of consequence intermediate value is that positive respective signal is co-channel interference signal; The non-interference signal substituting of its adjacent periods of co-channel interference signal that co-channel interference signal cancellation module will detect, and by the data accumulation on the same range unit of radar in adjacent 3 recurrence intervals.

Suppose i-th radar pulse echoed signal R in single cycle _it () is by ideal pulse echoed signal S _i(t) and incoherent additive noise signal N _i(t) superposition composition:

R _i(t)＝S _i(t)+N _i(t),0<t<T

Wherein T represents the time of a recurrence interval, and t represents any instant in the recurrence interval,

I-th radar pulse echoed signal signal to noise ratio (S/N ratio) is:

Can be expressed as after the pulse echo signal accumulation in adjacent 3 cycles:

Signal to noise ratio (S/N ratio) after echoed signal accumulation is: ${\mathrm{SNR}}_3={\left(\frac{S}{N}\right)}_3=\frac{{[3\&times;S_i\left(t\right)]}^2}{E\left\{\underset{i=1}{\overset{3}{\mathrm{\&Sigma;}}}{\left[N_i\left(t\right)\right]}^2\right\}+E\left[\underset{i\&NotEqual;j}{\mathrm{\&Sigma;}}{N}_i\left(t\right)N_j\left(t\right)\right]}$

Noise due to each cycle is separate, so have:

Therefore the signal to noise ratio (S/N ratio) after echoed signal accumulation: $\sqrt{3}\mathrm{SNR}\&le;{\mathrm{SNR}}_3=\frac{3^2{\left[S_i\left(t\right)\right]}^2}{E\left\{\underset{i=1}{\overset{3}{\mathrm{\&Sigma;}}}{\left[N_i\left(t\right)\right]}^2\right\}}\&le;3\mathrm{SNR}$

Method described in the utility model improves signal to noise ratio (S/N ratio) while removal co-channel interference signal, protects echo signal, simultaneously can according to the effect suppressing grade to control co-channel interference suppression.

(4) ocean clutter cancellation process.Sea clutter is the set of many scattering points, and the resolution of ship-navigation radar radar when different range MODE of operation can change thereupon, and the probability density of sea clutter amplitude also directly changes in rayleigh distributed and Wei Buer distribution thereupon.The utility model adopts a kind of Adaptive Suppression disposal route, and it realizes schematic flow sheet as shown in Figure 9, first by carrying out parametric statistics to N frame scan echo data before given radar, draws the various distributed model characteristic ginseng values of these data; Then parameter value is brought into respectively in rayleigh distributed and Wei Buer distribution probability density function.

Rayleigh distributed probability density function is:

$f\left(x\right)=\frac{x}{{\mathrm{\&sigma;}}^2}\exp [-\frac{x^2}{2{\mathrm{\&sigma;}}^2}],x>0$

In formula, x is sea clutter amplitude, and σ is sea clutter standard deviation, also referred to as form parameter.

Wei Buer distribution probability density function is:

$f\left(x\right)={\left(\frac{x}{q}\right)}^{p-1}\left(\frac{p}{q}\right)\exp [-{\left(\frac{x}{q}\right)}^2],x>0,p>0,q>0$

In formula, x is sea clutter amplitude, and q is scale parameter, and p is form parameter.

Obtain the data sequence of 2 kinds of distributions, then make comparisons with the distribution series of radar return data, select immediate distributed model, the background offseted using this model as sea clutter, finally by follow-up N+i (i=1,2,3 ...) frame radar return data and background offset process.Remember follow-up N+i (i=1,2,3 ...) frame echo data sequence is f, background model sequence is y, obtains frequency spectrum function F and Y respectively to echo data sequence and background model sequence as FFT, and then the power spectral density function calculating them is respectively P _fand P _y, finally by F and Y, P _fwith P _ywork subtracts each other and offsets.

More than show and describe ultimate principle of the present utility model, principal character and advantage of the present utility model.The technician of the industry should understand; the utility model is not restricted to the described embodiments; what describe in above-described embodiment and instructions just illustrates principle of the present utility model; under the prerequisite not departing from the utility model spirit and scope; the utility model also has various changes and modifications, and these changes and improvements all fall within the scope of claimed the utility model.The claimed scope of the utility model is defined by appending claims and equivalent thereof.

Claims (6)

1. the digital signal processor for ship-navigation radar, it is characterized in that, comprise A/D sampling thief, synchronous DRAM SDRAM1, static RAM SRAM, nonvolatile memory FLASH, Ethernet interface, programmable logic device (PLD) FPGA, digital signal processor DSP, ethernet controller, expansion interface and synchronous DRAM SDRAM2; The digital signal output end of A/D sampling thief and sampling clock input end are connected with the data terminal of programmable logic device (PLD) FPGA and output terminal of clock respectively, and the data terminal of synchronous DRAM SDRAM1 is connected with address end with the data terminal of programmable logic device (PLD) FPGA respectively with address end; The data terminal of static RAM SRAM is connected with address end with the data terminal of programmable logic device (PLD) FPGA respectively with address end, and the data terminal of ethernet controller is connected with control end with the data terminal of programmable logic device (PLD) FPGA respectively with control end; Ethernet interface is connected with the output terminal of ethernet controller, and expansion interface is connected with the GPIO interface of programmable logic device (PLD) FPGA; The data terminal of nonvolatile memory FLASH is connected with address end with the data terminal of digital signal processor DSP respectively with address end, and the data terminal of synchronous DRAM SDRAM2 is connected with address end with the data terminal of digital signal processor DSP respectively with address end; Programmable logic device (PLD) FPGA is connected with the EMIF bus interface of digital signal processor DSP by DSP.

2. a kind of digital signal processor for ship-navigation radar according to claim 1, is characterized in that, described A/D sampling thief is converted to digital signal to the radar return video signal sampling that ship-navigation radar receiver exports; Described digital signal processor, near ship-navigation radar receiver, adopts Ethernet transmission mode to send data to the display terminal of radar lower unit.

3. a kind of digital signal processor for ship-navigation radar according to claim 2, is characterized in that, described ethernet controller is used for the driving of ethernet communication, comprises packing and the decompress(ion) of data; Described Ethernet interface is used as the communication interface of digital signal processor and display terminal.

4. a kind of digital signal processor for ship-navigation radar according to claim 1, is characterized in that, described programmable logic device (PLD) FPGA is used for the logic of marine radar system and sequential control, signals collecting, transmission and Signal Pretreatment; The EMIF interface that digital signal processor DSP is carried by it is connected with memory storage SDRAM 2, FLASH and FPGA, for the process of radar signal.

5. a kind of digital signal processor for ship-navigation radar according to claim 1, is characterized in that, described synchronous DRAM SDRAM1 is used for the good radar return data of stores processor and stores; The data that described static RAM SRAM exports for storing A/D sampling thief, and realize ping-pong operation when data are transmitted with the fifo module of FPGA inside; Described synchronous DRAM SDRAM2 is for storing pending radar return data; The user program code that described nonvolatile memory FLASH runs for storing DSP.

6. a kind of digital signal processor for ship-navigation radar according to claim 1, is characterized in that, described A/D sampling thief is made up of SMA radio-frequency joint, radio frequency transmission transformer, A/D chip; Vision signal enters the input end of radio frequency transmission transformer through SMA radio-frequency joint, output difference sub-signal after transformer conversion, the clock signal of A/D chip is provided by the clock module of programmable logic device (PLD) FPGA inside, between the output terminal of clock and the input end of clock of A/D chip of FPGA, add radio-frequency transformer (RFT), clock signal is converted into differential signal by described radio-frequency transformer (RFT); The data terminal of A/D chip is connected with FPGA.