CN204577067U - A kind of array base palte and display panel - Google Patents
A kind of array base palte and display panel Download PDFInfo
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- CN204577067U CN204577067U CN201520295434.9U CN201520295434U CN204577067U CN 204577067 U CN204577067 U CN 204577067U CN 201520295434 U CN201520295434 U CN 201520295434U CN 204577067 U CN204577067 U CN 204577067U
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Abstract
The utility model discloses a kind of array base palte and display panel, this array base palte comprises viewing area and the rim area around viewing area, viewing area is provided with common electrode layer and touch-control routing layer, common electrode layer comprises multiple public electrode unit, and touch-control routing layer comprises many touch-control cablings be electrically connected with public electrode unit; The p-wire that rim area is provided with test cell and is electrically connected with test cell, the other end of p-wire is electrically connected with the structure to be tested in array base palte viewing area, for treating test structure and test before array base palte assembling, p-wire comprises at least one the first p-wires and the first p-wire and touch-control cabling are positioned at same layer.First p-wire is arranged on and the rim area of touch-control routing layer with layer by array base palte provided by the utility model, and without the need to additionally increasing frame area to place the first p-wire, thus reduce the frame area of array base palte and display panel, to be adapted to the development trend of narrow frame.
Description
Technical field
The utility model relates to display technique field, particularly relates to a kind of array base palte and a kind of display panel.
Background technology
Display panel of the prior art comprises array base palte and color membrane substrates, wherein, described array base palte usually needs to test the structure of described array base palte viewing area before assembling with described color membrane substrates, after the structured testing of described viewing area is qualified, again at the lower frame district of described display panel binding driving circuit, and assemble with described color membrane substrates, to reduce the underproof probability of described display panel.
But, display panel of the prior art, because the area of its drive circuit area is less, usually by being used for, upper side frame district relative with described drive circuit area in described display panel is arranged on to the test circuit that described viewing area structure is tested, then each structure of viewing area is electrically connected to described test circuit by the p-wire being positioned at same layer with described driving circuit from the rim area of the described display panel left and right sides to test, thus add the area of described display panel rim area, be not suitable for the development trend of narrow frame.
Utility model content
For solving the problems of the technologies described above, the utility model embodiment provides a kind of array base palte and comprises the display panel of this array base palte, to reduce the area of described display panel rim area, thus is adapted to the development trend of narrow frame.
For solving the problem, the utility model embodiment provides following technical scheme:
A kind of array base palte, described array base palte comprises viewing area and rim area, described rim area is arranged around the surrounding of described viewing area, described viewing area is provided with common electrode layer and touch-control routing layer, wherein, described common electrode layer comprises multiple public electrode unit, and described touch-control routing layer comprises many touch-control cablings be electrically connected with described public electrode unit;
The p-wire that described rim area is provided with test cell and is electrically connected with described test cell, the other end of described p-wire is electrically connected with the structure to be tested in described array base palte viewing area, for testing the structure to be tested in described array base palte viewing area before described array base palte assembling, described p-wire comprises at least one the first p-wires, and described first p-wire and described touch-control cabling are positioned at same layer.
Optionally, described public electrode unit is used as public electrode in the display stage, is used as self-capacitance touch control electrode in the touch-control stage.
Optionally, described public electrode unit is used as public electrode in the display stage, is used as to drive touch control electrode or induction touch control electrode in the touch-control stage.
Optionally, described rim area comprises: be positioned at the first rim area on the left of described viewing area, be positioned on the right side of described viewing area with the second rim area, the 4th rim area that is positioned at the 3rd rim area on the upside of described viewing area and is positioned on the downside of described viewing area, described first p-wire is positioned at described first rim area and/or the second rim area at least partly.
Optionally, the viewing area of described array base palte is provided with source-drain electrode layer and grid layer, and the rim area of described array base palte is provided with gate driver circuit.
Optionally, described first p-wire in the projection of the part of described first rim area and/or the second rim area between the projection and the projection of described viewing area of described gate driver circuit,
Optionally, described p-wire also comprises: at least one the second p-wires, described second p-wire and described source-drain electrode layer are positioned at same layer.
Optionally, described second p-wire is positioned at described 3rd rim area and/or the 4th rim area.
Optionally, described second p-wire part is positioned at described first rim area and/or the second rim area, and part is positioned at described 3rd rim area and/or the 4th rim area.
Optionally, described second p-wire in the projection of the part of described first rim area and/or the second rim area between the projection and the projection of described viewing area of described gate driver circuit.
Optionally, described p-wire also comprises at least one 3rd p-wires, and described 3rd p-wire and described grid layer are positioned at same layer.
Optionally, described 3rd p-wire is positioned at described 3rd rim area and/or the 4th rim area.
Optionally, described 3rd p-wire part is positioned at described first rim area and/or the second rim area, and part is positioned at described 3rd rim area and/or the 4th rim area.
Optionally, described 3rd p-wire in the projection of the part of described first rim area and/or the second rim area between the projection and the projection of described viewing area of described gate driver circuit.
A kind of display panel, comprising: the array base palte be oppositely arranged and color membrane substrates, and the liquid crystal layer between described array base palte and described color membrane substrates, and wherein, described array base palte is the array base palte described in above-mentioned any one.
Compared with prior art, technique scheme has the following advantages:
The array base palte that the utility model embodiment provides comprises viewing area and rim area, described rim area is arranged around the surrounding of described viewing area, wherein, described viewing area is provided with common electrode layer and touch-control routing layer, the p-wire that described rim area is provided with test cell and is electrically connected with described test cell, the other end of described p-wire is electrically connected with the structure to be tested in described array base palte viewing area, for testing the structure to be tested in described array base palte viewing area before described array base palte assembling, described p-wire comprises at least one the first p-wires, described first p-wire and described touch-control cabling are positioned at same layer.
Due in prior art array base palte, touch-control cabling in described touch-control routing layer is only positioned at viewing area, it is insulation course with the rim area that layer is corresponding, there is no cabling, and described first p-wire is arranged on and the rim area of described touch-control routing layer with layer by the array base palte that the utility model embodiment provides, and without the need to additionally increasing frame area to place described first p-wire, thus reduce the frame area of described array base palte, and then reduce the frame area of the display panel comprising this array base palte, to be adapted to the development trend of narrow frame.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The vertical view of the array base palte that Fig. 1 provides for the utility model first embodiment;
The cut-open view of the array base palte that Fig. 2 provides for the utility model second embodiment;
The vertical view of the array base palte that Fig. 3 provides for the utility model second embodiment;
The cut-open view of the array base palte that Fig. 4 provides for the utility model the 5th embodiment;
The vertical view of the array base palte that Fig. 5 provides for the utility model the 5th embodiment;
The cut-open view of the array base palte that Fig. 6 provides for the utility model the 6th embodiment;
The vertical view of the array base palte that Fig. 7 provides for the utility model the 6th embodiment;
The cut-open view of the array base palte that Fig. 8 provides for the utility model the 7th embodiment;
The vertical view of the array base palte that Fig. 9 provides for the utility model the 7th embodiment;
The cut-open view of the array base palte that Figure 10 provides for the utility model the 8th embodiment;
The cut-open view of the array base palte that Figure 11 provides for the utility model the 9th embodiment;
Described in the array base palte that Figure 12 provides for the utility model the 9th embodiment, the first p-wire walks a kind of vertical view of line position;
Described in the array base palte that Figure 13 provides for the utility model the 9th embodiment, the first p-wire walks the another kind of vertical view of line position;
The cut-open view of the array base palte that Figure 14 provides for the utility model the tenth embodiment;
The cut-open view of the array base palte that Figure 15 provides for the utility model the 14 embodiment;
The cut-open view of the display panel that Figure 16 provides for the utility model embodiment.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.
Set forth a lot of detail in the following description so that fully understand the utility model, but the utility model can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when doing similar popularization without prejudice to when the utility model intension, and therefore the utility model is by the restriction of following public specific embodiment.
The utility model first embodiment provides a kind of array base palte, as shown in Figure 1, this array base palte comprises viewing area 100 and rim area 200, wherein, described viewing area 100 is provided with common electrode layer (not shown) and touch-control routing layer (not shown), described common electrode layer comprises multiple public electrode unit, and described touch-control routing layer comprises many touch-control cablings be electrically connected with described public electrode unit, described rim area 200 is provided with test cell 30 and is electrically connected p-wire 20 with described test cell 30, the other end of described p-wire 20 is electrically connected with the structure to be tested 40 in described array base palte viewing area 100, for testing the structure to be tested 40 in described array base palte viewing area 100 before described array base palte assembling, described p-wire 20 comprises at least one the first p-wires, and described first p-wire and described touch-control cabling are positioned at same layer, thus utilize described touch-control cabling to place described first p-wire with the rim area of layer, and without the need to additionally increasing frame area to place described first p-wire, reduce the frame area of described array base palte, and then reduce the frame area of the display panel comprising this array base palte, to be adapted to the development trend of narrow frame.
It should be noted that, in the utility model embodiment, the rim area 200 of described array base palte is provided with multiple test cell 30 and many p-wires 20 usually, preferably, described test cell 30 and described p-wire 20 one_to_one corresponding, and the test cell 30 corresponding with it is electrically connected, but the utility model does not limit this, and the test cell 30 arranged in described array base palte rim area 200 and the quantity of p-wire 20 are determined on a case-by-case basis.
Concrete, in the utility model second embodiment, as shown in Figure 2, described array base palte comprises: first substrate 1; Be positioned at multiple public electrode unit 2 of the described surperficial viewing area of first substrate 1 100; Be positioned at the first insulation course 3 that described public electrode unit 2 deviates from described first substrate 1 side, described first insulation course 3 covers described public electrode unit 2 and described first substrate 1 surface completely; Be positioned at many touch-control cablings 4 of the described first surperficial viewing area 100 of insulation course 3, described touch-control cabling 4 is electrically connected with described public electrode unit 2 by the first via hole 5; Be positioned at least one the first p-wires 6 of the described first surperficial rim area 200 of insulation course 3, described first p-wire 6 and described touch-control cabling 4 mutually insulated.
On the basis of above-described embodiment, in the 3rd embodiment of the present utility model, described array base palte for making self-capacitance display panel, in this embodiment, described public electrode unit 2 is used as public electrode in the display stage, is used as self-capacitance touch control electrode in the touch-control stage; In the 4th embodiment of the present utility model, described array base palte is for making mutual capacitance display panel, in this embodiment, described public electrode unit 2 is used as public electrode in the display stage, be used as to drive touch control electrode or induction touch control electrode in the touch-control stage, the utility model does not limit this, specifically depends on the circumstances.
It should be noted that, when described public electrode unit 2 was used as to drive touch control electrode in the touch-control stage, described array base palte also comprises induction touch control electrode, and described induction touch control electrode and described public electrode unit 2 form touch control electrode, jointly for touch control detection; When described public electrode unit 2 is used as induction touch control electrode in the touch-control stage, described array base palte also comprises driving touch control electrode, and described driving touch control electrode and described public electrode unit 2 form touch control electrode, jointly for touch control detection.
As shown in Figure 3, in the utility model embodiment, described rim area 200 comprises: the 4th rim area 204 being positioned at the first rim area 201 on the left of described viewing area 100, being positioned at the second rim area 202 on the right side of described viewing area 100, being positioned at the 3rd rim area 203 on the upside of described viewing area 100 and being positioned on the downside of described viewing area 100; Described first p-wire 6 is positioned at described first rim area 201 and/or the second rim area 202 at least partly.In the 5th embodiment of the present utility model, as shown in Figure 4 and Figure 5, described first p-wire 6 is positioned at described first rim area 201; In the 6th embodiment of the present utility model, as shown in Figure 6 and Figure 7, described first p-wire 6 is positioned at described second rim area 202; In the 7th embodiment of the present utility model, as as described in Fig. 8 and Fig. 9, when described p-wire 20 comprises many first p-wires 6, described first rim area 201 can also be positioned at by part first p-wire 6, described first p-wire 6 of part is positioned at described second rim area 202, the utility model does not limit this, specifically depends on the circumstances.
It should be noted that, in the utility model embodiment, described first p-wire 6 only can be positioned at the first rim area 201 and/or the second rim area 202, partly can also be positioned at described first rim area 201 and/or the second rim area 202, part is positioned at described 3rd rim area 203 and/or the 4th rim area 204, the utility model does not limit this, as long as ensure that described first p-wire 6 is positioned at described first rim area 201 and/or the second rim area 202 at least partly, test cell 30 can be electrically connected to by described first p-wire 6 to make the structure to be tested 40 in described array base palte viewing area 100.
On the basis of above-mentioned any embodiment, in the utility model embodiment, the viewing area 100 of described array base palte is provided with source-drain electrode layer and grid layer, and the rim area 200 of described array base palte is provided with gate driver circuit.Concrete, in the 8th embodiment of the present utility model, as shown in Figure 10, viewing area 100 between described common electrode layer and described first substrate 1 is provided with source-drain electrode layer, viewing area 100 between described source-drain electrode layer and described first substrate 1 is provided with grid layer, wherein, described source-drain electrode layer comprises many source-drain electrode lines 7, described grid layer comprises many gate lines 8, and described source-drain electrode line 7 is insulated by described second insulation course 9 and described public electrode unit 2 phase, insulated by described 3rd insulation course 10 and described gate line 8 phase; Rim area 200 between described common electrode layer and described first substrate 1 is provided with gate driver circuit 11.It should be noted that, in the present embodiment, described gate driver circuit 11 is positioned at same layer with described grid layer, but the utility model does not limit this, in other embodiments of the utility model, described gate driver circuit 11 can also be positioned at other layers, specifically depends on the circumstances.
On the basis of above-described embodiment, in the 9th embodiment of the present utility model, as shown in figure 11, described first p-wire 6 in the projection of the part of described first rim area 201 and/or the second rim area 202 between the projection and the projection of described viewing area 100 of described gate driver circuit 11, described first p-wire 6 is made to utilize the region described in original frame area between gate driver circuit 11 and described viewing area 100, but the utility model does not limit this, specifically depend on the circumstances.
Concrete, in an embodiment of the present utility model, as shown in figure 12, the cascade district 210 of described first p-wire 6 between the projection and the projection of described viewing area 100 of described gate driver circuit 11, it should be noted that, in the present embodiment, described cascade district 210 is provided with multiple via hole 50, in order to reduce the probability of the situation such as signal shorts and signal disturbing, described first p-wire 6 walk the position that line position preferably avoids described via hole 50 vertical direction, namely described first p-wire 6 the projection in described cascade district 210 and the projection of described via hole 50 not overlapping.
In another embodiment of the present utility model, as shown in figure 13, described rim area 200 is also provided with the many gate drive signal lines 60 be connected with described gate driver circuit electricity 11, in an embodiment of the present embodiment, described first p-wire 6 can also be positioned at directly over described gate drive signal line 60, and namely described first p-wire 6 overlaps with the projection of described gate drive signal line 60 along the projection in described gate drive signal line 60 direction in described rim area 200.In other embodiments of the present utility model, described first p-wire 6 can also optional position directly over described gate driver circuit 11 or between described gate driver circuit 11 and described viewing area 100, the utility model does not limit this, specifically depends on the circumstances.
On the basis of above-mentioned any embodiment, in the tenth embodiment of the present utility model, as shown in figure 14, described p-wire also comprises: at least one the second p-wires 12, described second p-wire 12 is positioned at same layer with described source-drain electrode layer, to divide two-layer setting by the p-wire being originally all positioned at same layer, thus under identical frame area, increase the spacing of adjacent p-wire, weaken the interference of test signal in adjacent p-wire, or when adjacent p-wire uniform distances, reduce the frame area that described p-wire takies further.It should be noted that, although in the present embodiment, described second p-wire 12 is positioned at same layer with described source-drain electrode layer, but the utility model does not limit this, in other embodiments of the present utility model, described second p-wire 12 can also be positioned at same layer with other electrode layers, or arranges one deck separately, specifically depends on the circumstances.
On the basis of above-described embodiment, in the 11 embodiment of the present utility model, described second p-wire 12 is positioned at the 3rd rim area 203 and/or the 4th rim area 204, for connecting described first p-wire 6 and test circuit, in the 12 embodiment of the present utility model, described second p-wire 12 part is positioned at described first rim area 201 and/or the second rim area 202, part is positioned at described 3rd rim area 203 and/or the 4th rim area 204, directly be connected with test circuit with the structure to be tested in described array base palte viewing area 100, the utility model does not limit this, specifically depend on the circumstances.
On the basis of above-described embodiment, in the 13 embodiment of the present utility model, when described second p-wire 12 part is positioned at described first rim area 201 and/or the second rim area 202, when part is positioned at described 3rd rim area 203 and/or the 4th rim area 204, described second p-wire 12 in the projection of the part of described first rim area 201 and/or the second rim area 202 between the projection and the projection of described viewing area 100 of described gate driver circuit 11, described second p-wire 12 is made to utilize the region described in original frame area between gate driver circuit 11 and described viewing area 100, but the utility model does not limit this, specifically depend on the circumstances.
On the basis of above-mentioned any embodiment, in the 14 embodiment of the present utility model, as shown in figure 15, described p-wire also comprises: at least one 3rd p-wires 13, described 3rd p-wire 13 is positioned at same layer with described grid layer, to divide two-layer or three layers of setting by the p-wire being originally all positioned at same layer, thus under identical frame area, increase the spacing of adjacent p-wire, weaken the interference of test signal in adjacent p-wire, or when adjacent p-wire uniform distances, reduce the frame area that described p-wire takies further.It should be noted that, although in the present embodiment, described 3rd p-wire 13 is positioned at same layer with described grid layer, but the utility model does not limit this, in other embodiments of the present utility model, described 3rd p-wire 13 can also be positioned at same layer with other electrode layers, or arranges one deck separately, specifically depends on the circumstances.
On the basis of above-described embodiment, in the 15 embodiment of the present utility model, described 3rd p-wire 13 is positioned at the 3rd rim area 203 and/or the 4th rim area 204, for connecting described first p-wire 6 and test circuit, in the 16 embodiment of the present utility model, described 3rd p-wire 13 part is positioned at described first rim area 201 and/or the second rim area 202, part is positioned at described 3rd rim area 203 and/or the 4th rim area 204, directly be connected with test circuit with the structure to be tested in described array base palte viewing area 100, the utility model does not limit this, specifically depend on the circumstances.
On the basis of above-described embodiment, in the 17 embodiment of the present utility model, when described 3rd p-wire 13 part is positioned at described first rim area 201 and/or the second rim area 202, when part is positioned at described 3rd rim area 203 and/or the 4th rim area 204, described 3rd p-wire 13 in the projection of the part of described first rim area 201 and/or the second rim area 202 between the projection and the projection of described viewing area 100 of described gate driver circuit 11, described 3rd p-wire 13 is made to utilize the region described in original frame area between gate driver circuit 11 and described viewing area 100, but the utility model does not limit this, specifically depend on the circumstances.
Accordingly, the utility model embodiment still provides a kind of display panel, as shown in figure 16, described display panel comprises: the array base palte 300 be oppositely arranged and color membrane substrates 400, and the liquid crystal layer 500 between described array base palte 300 and described color membrane substrates 400, wherein, described array base palte 300 is the array base palte described in the above-mentioned any embodiment of the utility model.
In sum, the array base palte that the utility model embodiment provides and comprising in the display panel of this array base palte, described viewing area 100 is provided with common electrode layer and touch-control routing layer, described rim area 200 is provided with p-wire, described p-wire is used for testing the structure of described array base palte viewing area 100 before described array base palte assembling, described p-wire comprises at least one the first p-wires 6, and described first p-wire 6 is positioned at same layer with described touch-control cabling 4.
Due in prior art array base palte, touch-control cabling 4 in described touch-control routing layer is only positioned at viewing area 100, it is insulation course with the rim area 200 that layer is corresponding, there is no electrode wires, and described first p-wire 6 is arranged on and the rim area of described touch-control routing layer with layer by the array base palte that the utility model embodiment provides, and without the need to additionally increasing frame area to place described first p-wire 6, thus reduce the frame area of described array base palte, and then reduce the frame area of the display panel comprising this array base palte, to be adapted to the development trend of narrow frame.
In this instructions, various piece adopts the mode of going forward one by one to describe, and what each some importance illustrated is the difference with other parts, between various piece identical similar portion mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the utility model.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein when not departing from spirit or scope of the present utility model, can realize in other embodiments.Therefore, the utility model can not be restricted to embodiment illustrated herein, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (15)
1. an array base palte, described array base palte comprises viewing area and rim area, described rim area is arranged around the surrounding of described viewing area, it is characterized in that, described viewing area is provided with common electrode layer and touch-control routing layer, wherein, described common electrode layer comprises multiple public electrode unit, and described touch-control routing layer comprises many touch-control cablings be electrically connected with described public electrode unit;
The p-wire that described rim area is provided with test cell and is electrically connected with described test cell, the other end of described p-wire is electrically connected with the structure to be tested in described array base palte viewing area, for testing the structure to be tested in described array base palte viewing area before described array base palte assembling, described p-wire comprises at least one the first p-wires, and described first p-wire and described touch-control cabling are positioned at same layer.
2. array base palte according to claim 1, is characterized in that, described public electrode unit is used as public electrode in the display stage, is used as self-capacitance touch control electrode in the touch-control stage.
3. array base palte according to claim 1, is characterized in that, described public electrode unit is used as public electrode in the display stage, is used as to drive touch control electrode or induction touch control electrode in the touch-control stage.
4. array base palte according to claim 1, it is characterized in that, described rim area comprises: be positioned at the first rim area on the left of described viewing area, be positioned on the right side of described viewing area with the second rim area, the 4th rim area that is positioned at the 3rd rim area on the upside of described viewing area and is positioned on the downside of described viewing area, described first p-wire is positioned at described first rim area and/or the second rim area at least partly.
5. array base palte according to claim 4, is characterized in that, the viewing area of described array base palte is provided with source-drain electrode layer and grid layer, and the rim area of described array base palte is provided with gate driver circuit.
6. array base palte according to claim 5, is characterized in that, described first p-wire in the projection of the part of described first rim area and/or the second rim area between the projection and the projection of described viewing area of described gate driver circuit.
7. the array base palte according to claim 5 or 6, is characterized in that, described p-wire also comprises: at least one the second p-wires, described second p-wire and described source-drain electrode layer are positioned at same layer.
8. array base palte according to claim 7, is characterized in that, described second p-wire is positioned at described 3rd rim area and/or the 4th rim area.
9. array base palte according to claim 7, is characterized in that, described second p-wire part is positioned at described first rim area and/or the second rim area, and part is positioned at described 3rd rim area and/or the 4th rim area.
10. array base palte according to claim 9, is characterized in that, described second p-wire in the projection of the part of described first rim area and/or the second rim area between the projection and the projection of described viewing area of described gate driver circuit.
11. array base paltes according to claim 5-6 or any one of 8-10, it is characterized in that, described p-wire also comprises at least one 3rd p-wires, and described 3rd p-wire and described grid layer are positioned at same layer.
12. array base paltes according to claim 11, is characterized in that, described 3rd p-wire is positioned at described 3rd rim area and/or the 4th rim area.
13. array base paltes according to claim 11, is characterized in that, described 3rd p-wire part is positioned at described first rim area and/or the second rim area, and part is positioned at described 3rd rim area and/or the 4th rim area.
14. array base paltes according to claim 13, is characterized in that, described 3rd p-wire in the projection of the part of described first rim area and/or the second rim area between the projection and the projection of described viewing area of described gate driver circuit.
15. 1 kinds of display panels, it is characterized in that, comprising: the array base palte be oppositely arranged and color membrane substrates, and the liquid crystal layer between described array base palte and described color membrane substrates, wherein, described array base palte is the array base palte described in any one of claim 1-14.
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| CN105182640A (en) * | 2015-09-06 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN105549792A (en) * | 2016-02-05 | 2016-05-04 | 上海天马微电子有限公司 | Array substrate and display panel |
| CN106325608A (en) * | 2016-10-28 | 2017-01-11 | 上海中航光电子有限公司 | Touch display panel and touch display device |
| CN106648210A (en) * | 2016-10-19 | 2017-05-10 | 合肥鑫晟光电科技有限公司 | Display panel and preparation method thereof, display device |
| CN106775124A (en) * | 2017-01-20 | 2017-05-31 | 上海天马微电子有限公司 | A kind of touch-control display panel and display device |
| CN108874201A (en) * | 2016-02-04 | 2018-11-23 | 厦门天马微电子有限公司 | A kind of array substrate and display panel |
| CN111292660A (en) * | 2020-02-12 | 2020-06-16 | 合肥鑫晟光电科技有限公司 | OLED driving backboard, detection method thereof and display device |
| CN112820766A (en) * | 2018-03-28 | 2021-05-18 | 上海天马微电子有限公司 | Flexible display panel and display device |
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| CN105182640A (en) * | 2015-09-06 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN105182640B (en) * | 2015-09-06 | 2019-06-07 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN108874201B (en) * | 2016-02-04 | 2021-06-15 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN108874201A (en) * | 2016-02-04 | 2018-11-23 | 厦门天马微电子有限公司 | A kind of array substrate and display panel |
| CN105549792B (en) * | 2016-02-05 | 2019-02-12 | 上海天马微电子有限公司 | Array substrate and display panel |
| CN105549792A (en) * | 2016-02-05 | 2016-05-04 | 上海天马微电子有限公司 | Array substrate and display panel |
| CN106648210A (en) * | 2016-10-19 | 2017-05-10 | 合肥鑫晟光电科技有限公司 | Display panel and preparation method thereof, display device |
| CN106648210B (en) * | 2016-10-19 | 2023-11-28 | 合肥鑫晟光电科技有限公司 | Display panel, preparation method thereof and display device |
| CN106325608A (en) * | 2016-10-28 | 2017-01-11 | 上海中航光电子有限公司 | Touch display panel and touch display device |
| CN106325608B (en) * | 2016-10-28 | 2023-06-16 | 上海中航光电子有限公司 | Touch display panel and touch display device |
| CN106775124A (en) * | 2017-01-20 | 2017-05-31 | 上海天马微电子有限公司 | A kind of touch-control display panel and display device |
| CN106775124B (en) * | 2017-01-20 | 2022-09-16 | 上海天马微电子有限公司 | Touch display panel and display device |
| CN112820766A (en) * | 2018-03-28 | 2021-05-18 | 上海天马微电子有限公司 | Flexible display panel and display device |
| CN111292660A (en) * | 2020-02-12 | 2020-06-16 | 合肥鑫晟光电科技有限公司 | OLED driving backboard, detection method thereof and display device |
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