CN204576512U - A kind of low mismatch clock output circuit - Google Patents
A kind of low mismatch clock output circuit Download PDFInfo
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- CN204576512U CN204576512U CN201520181791.2U CN201520181791U CN204576512U CN 204576512 U CN204576512 U CN 204576512U CN 201520181791 U CN201520181791 U CN 201520181791U CN 204576512 U CN204576512 U CN 204576512U
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Abstract
The utility model relates to a kind of low mismatch clock output circuit, comprise clock generation circuit, supply module and multiple clock output module, all be connected by tree clock signal line between clock generation circuit with clock output module, all be connected by power lead between supply module with clock output module, clock tree signal wire adopts tree structure wiring, and power lead adopts tree structure wiring.There is the technical matters of mismatch in the output clock of the clock output module that the utility model solves in existing clock output circuit, in clock output circuit of the present utility model, power lead adopts tree-shaped wire laying mode, eliminate the mismatch of power supply between clock output module, improve system performance.
Description
Technical field
The utility model relates to chip field, especially a kind of low mismatch clock output circuit.
Background technology
See Fig. 1, common dram chip tree clock signal line wiring method.
In the ordinary course of things, tree clock signal line in the clock output circuit of dram chip can strictly observe tree structure wiring, make clock from clock generation circuit to each clock output module the path of process mate completely, even identical, between the clock that each clock output module so just can be made to export, deviation is minimum, data and clock output area just can have larger allowance, under dram chip can be operated in higher frequency.But reality is, even if the tree clock signal line between clock generation circuit and clock output module adopts tree-shaped wire laying mode, still there is mismatch phenomenon in the output clock of clock output module.For above-mentioned defect, those skilled in the art think that between tree clock signal line, tree structure has problems a very long time, the mismatch phenomenon just caused.But this mismatch phenomenon is not unanimously all resolved.
Following situation is just found through great many of experiments:
See Fig. 2, each clock output module needs supply module to provide power supply could normal work, and existing situation power lead can adopt mode in Fig. 2 to arrange, namely clock output module can from nearest power lead line, for self provides power supply.But, clock output module meeting current sinking I, power lead has dead resistance R, the magnitude of voltage that therefore the clock output module of diverse location obtains is different simultaneously, such as: clock output module 21 voltage is assumed to be V1, so clock output module 22 voltage can only reach V1-I*R.The clock that clock output module exports is closely related with its voltage again, and when voltage is lower, clock can be slack-off, and when voltage is higher, clock can accelerate.So cause producing mismatch between the output clock of each clock output module, data and clock output area can be had a strong impact on when high frequency, and the performance of DRAM.
Summary of the invention
In order to the output clock solving the clock output module in existing clock output circuit exists the technical matters of mismatch, the utility model provides a kind of low mismatch clock output circuit.
Technical solution of the present utility model:
A kind of low mismatch clock output circuit, comprise clock generation circuit, supply module and multiple clock output module, all be connected by tree clock signal line between described clock generation circuit with clock output module, all be connected by power lead between described supply module with clock output module, its special character is: described clock tree signal wire adopts tree structure wiring, and described power lead adopts tree structure wiring.
Above-mentioned supply module has one or more.
The distributing position of above-mentioned supply module is symmetrical in the center of multiple clock output module.
The advantage that the utility model has:
1, in clock output circuit of the present utility model, power lead adopts tree-shaped wire laying mode, eliminates the mismatch of power supply between clock output module, improves system performance.
2, the utility model adopts symmetrical tree-shaped wire laying mode, make the power lead of each clock output module through same path, same current value can be flow through, have same dead resistance simultaneously, just can obtain same supply voltage, reduce the mismatch between clock output module.
Accompanying drawing explanation
Fig. 1 is existing clock line schematic wiring diagram;
Fig. 2 is existing clock line and power lead schematic wiring diagram;
Fig. 3 is power lead schematic wiring diagram of the present utility model;
Fig. 4 is that the utility model simulation result compares (rising edge);
Fig. 5 is that the utility model simulation result compares (negative edge);
Wherein Reference numeral is: 11,12,13 ... 48-clock output module,
Specific embodiment
See Fig. 3, low mismatch clock output circuit of the present utility model, comprise clock generation circuit, supply module and multiple clock output module, all be connected by tree clock signal line between clock generation circuit with clock output module, all be connected by power lead between supply module with clock output module, clock tree signal wire adopts tree structure wiring, and power lead adopts tree structure wiring.
Supply module can have one or more, such as, shown in Fig. 3, supply module be two, lay respectively at the both sides of clock output module.The quantity of supply module depends on the number of clock output module, but needs geographically demand fulfillment to be symmetrical arranged, and symmetric points are positioned at the center of clock output module.
The utility model adopts symmetrical tree-shaped wire laying mode to the power lead of Clock Tree, makes the power lead of each clock output module through same path, can flow through same current value, has same dead resistance simultaneously, just can obtain same supply voltage.
Be that the utility model rising edge simulation result compares schematic diagram see Fig. 4, wherein horizontal ordinate is the time, ordinate is voltage, left-most curve is simulation result of the present utility model, the right curve is the simulation result signal of prior art, and as can be seen from the figure the mismatch of clock output rising edge is reduced to 21.5% of prior art.
Be that the utility model negative edge simulation result compares schematic diagram see Fig. 5, wherein horizontal ordinate is the time, ordinate is voltage, left-most curve is simulation result of the present utility model, the right curve is the simulation result signal of prior art, as can be seen from the figure the mismatch of clock output negative edge is reduced to 18% of prior art, and mismatch reduces greatly.
Claims (3)
1. one kind low mismatch clock output circuit, comprise clock generation circuit, supply module and multiple clock output module, all be connected by tree clock signal line between described clock generation circuit with clock output module, all be connected by power lead between described supply module with clock output module, it is characterized in that: described clock tree signal wire adopts tree structure wiring, and described power lead adopts tree structure wiring.
2. low mismatch clock output circuit according to claim 1, is characterized in that: described supply module has one or more.
3. low mismatch clock output circuit according to claim 1 and 2, is characterized in that: the distributing position of described supply module is symmetrical in the center of multiple clock output module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520181791.2U CN204576512U (en) | 2015-03-27 | 2015-03-27 | A kind of low mismatch clock output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520181791.2U CN204576512U (en) | 2015-03-27 | 2015-03-27 | A kind of low mismatch clock output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204576512U true CN204576512U (en) | 2015-08-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520181791.2U Active CN204576512U (en) | 2015-03-27 | 2015-03-27 | A kind of low mismatch clock output circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204576512U (en) |
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2015
- 2015-03-27 CN CN201520181791.2U patent/CN204576512U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee before: Xi'an Sinochip Semiconductors Co., Ltd. |