CN204558019U - Based on the STT-RAM reading circuit of two-stage amplifier - Google Patents
Based on the STT-RAM reading circuit of two-stage amplifier Download PDFInfo
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- CN204558019U CN204558019U CN201520242558.0U CN201520242558U CN204558019U CN 204558019 U CN204558019 U CN 204558019U CN 201520242558 U CN201520242558 U CN 201520242558U CN 204558019 U CN204558019 U CN 204558019U
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Abstract
The utility model relates to a kind of STT-RAM reading circuit based on two-stage amplifier.The parallel magnetic tunnel-junction comprising an Open-loop amplifier and be connected with this Open-loop amplifier, control logic circuit and the first phase inverter, described first phase inverter is also connected with the first d type flip flop and the second d type flip flop, the clock control input end of described first d type flip flop and the second d type flip flop is connected to the first clock signal output terminal and the second clock signal output part of the first clock output module respectively, the reversed-phase output of described first d type flip flop and the second d type flip flop exports the high position data and low data that store in parallel magnetic tunnel-junction respectively, described control logic circuit is also connected with one for providing the external voltage output circuit of reference voltage.The reading circuit that the utility model provides effectively can improve reading speed, saves power consumption, increases output voltage swing and gain, improves the reliability of whole reading circuit when docking with digital display circuit.
Description
Technical field
The utility model relates to a kind of STT-RAM reading circuit based on two-stage amplifier.
Background technology
Traditional random-access memory (ram) such as dynamic RAM (DRAM) has cheaper price, but access speed is comparatively slow, permanance is poor and data can only preserve very short a period of time.Owing to must refresh a secondary data every a period of time, it is larger that this result in again power consumption.Static RAM (SRAM) has the advantages such as access speed is very fast, power consumption is lower, non-volatile, but expensive, integrated level is lower.
Spin transfer torque random access memory (STT-RAM) emerging in recent years, due to the advantage such as permanance and fast reading and writing of its high density, low-leakage current, non-volatile, overlength, is expected to the first-selected product becoming following high-speed cache.
This patent, based on a kind of tree-shaped reading circuit scheme of novelty, proposes the modified node method that effectively can reduce this reading circuit overall power consumption.The tree-shaped read schemes of this novelty adopts Open-loop amplifier as the comparer of reading circuit, Open-loop amplifier does not need reboot time, can compare continuously, therefore adopt Open-loop amplifier can improve the reading speed of circuit, there is reading time short advantage.The program adopts two stage amplifer cascade structure, increases output voltage swing and gain, improves the reliability of whole reading circuit when docking with digital display circuit.
Summary of the invention
The purpose of this utility model is to provide one effectively to improve reading speed, saves power consumption, increases output voltage swing and gain, improves the STT-RAM reading circuit based on two-stage amplifier of the reliability of whole reading circuit when docking with digital display circuit.
For achieving the above object, the technical solution of the utility model is: a kind of STT-RAM reading circuit based on two-stage amplifier, the parallel magnetic tunnel-junction, control logic circuit and the first phase inverter that comprise an Open-loop amplifier and be connected with this Open-loop amplifier, described first phase inverter is also connected with the first d type flip flop and the second d type flip flop, and the clock control input end of described first d type flip flop and the second d type flip flop is connected to the first clock signal output terminal and the second clock signal output part of the first clock output module respectively, the source electrode of described Open-loop amplifier first metal-oxide-semiconductor, the source electrode of the second metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor and the source electrode of the 8th metal-oxide-semiconductor are all connected to vdd terminal, the grid of described first metal-oxide-semiconductor is connected with the grid of the second metal-oxide-semiconductor, the grid of described 6th metal-oxide-semiconductor is connected with the drain electrode of the first metal-oxide-semiconductor to the drain electrode of the 3rd metal-oxide-semiconductor, the grid of described 8th metal-oxide-semiconductor is connected with the drain electrode of the second metal-oxide-semiconductor to the drain electrode of the 4th metal-oxide-semiconductor, the source electrode of described 3rd metal-oxide-semiconductor is connected to the drain electrode of the 5th metal-oxide-semiconductor with the source electrode of the 4th metal-oxide-semiconductor, the source electrode of described 5th metal-oxide-semiconductor is connected to ground, the drain electrode of described 6th metal-oxide-semiconductor connects the drain electrode of the 7th metal-oxide-semiconductor, the source electrode of described 7th metal-oxide-semiconductor meets GND, the drain electrode of described 8th metal-oxide-semiconductor is connected to the input end of the first phase inverter with the drain electrode of the 9th metal-oxide-semiconductor, the source ground of described 9th metal-oxide-semiconductor, the grid of described 7th metal-oxide-semiconductor is connected with the grid of the drain electrode of the 7th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor, the described grid of the 3rd metal-oxide-semiconductor and the source electrode of the first metal-oxide-semiconductor are connected to the two ends of parallel magnetic tunnel-junction respectively, the grid of described 4th metal-oxide-semiconductor is connected to control logic circuit, the reversed-phase output of described first d type flip flop and the second d type flip flop exports the high position data and low data that store in parallel magnetic tunnel-junction respectively, described control logic circuit is also connected with one for providing the external voltage output circuit of reference voltage, also comprise 1 the tenth metal-oxide-semiconductor, the described grid of the 3rd metal-oxide-semiconductor and the tie point of parallel magnetic tunnel-junction are connected to the drain electrode of the tenth metal-oxide-semiconductor, the source ground of described tenth metal-oxide-semiconductor, the grid of described tenth metal-oxide-semiconductor connects the 3rd clock signal output terminal of second clock output module.
In the utility model embodiment, described control logic circuit comprises the bidirectional switch circuit of the first clock signal control exported by the first d type flip flop reversed-phase output signal and the first clock signal output terminal, described bidirectional switch circuit comprises interconnective first two-way switch and the second two-way switch, and described bidirectional switch circuit is for controlling the connection of first, second, and third reference voltage output terminal of the 4th metal-oxide-semiconductor grid and external voltage output circuit.
In the utility model embodiment, described first clock output module comprises the first delay circuit, the second delay circuit, the 3rd two-way switch and the 4th two-way switch, described first delay circuit and the second delay circuit are connected to the 3rd clock signal output terminal, and described 3rd two-way switch and the 4th two-way switch are respectively used to the connection of control first delay circuit and the second delay circuit and the first clock signal output terminal and second clock signal output part.
In the utility model embodiment, the time delay being less than the second delay circuit time delay of described first delay circuit.
Compared to prior art, the utility model has following beneficial effect: the utility model circuit adopts Open-loop amplifier, saves the reboot time of circuit, improves the reading speed of circuit; Open-loop amplifier have employed two stage amplifer cascade structure, saves power consumption, increases output voltage swing and gain, improves the reliability of whole reading circuit when docking with digital display circuit; Built-in control logic, reduces use difficulty, and the controlling cost of peripheral system; In addition, compared with other reading circuits, this circuit adopts the read schemes of tree-shaped, has the advantage such as reading speed, less hardware consumption, lower cost faster.
Accompanying drawing explanation
Fig. 1 is two kinds of structural drawing of magnetic tunnel-junction.
Fig. 2 is the two stage amplifer basic block diagram of Open-loop amplifier.
Fig. 3 is the circuit theory diagrams of the utility model reading circuit.
The workflow diagram of the reading circuit of Fig. 4 designed by the utility model.
Fig. 5 is control logic circuit schematic diagram.
Fig. 6 is the first clock output module schematic diagram.
Fig. 7 is the analogous diagram that the utility model reads the STT-RAM of parallel magnetic tunnel junction structure.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is specifically described.
A kind of STT-RAM reading circuit based on two-stage amplifier of the present utility model, the parallel magnetic tunnel-junction, control logic circuit and the first phase inverter that comprise an Open-loop amplifier and be connected with this Open-loop amplifier, described first phase inverter is also connected with the first d type flip flop and the second d type flip flop, and the clock control input end of described first d type flip flop and the second d type flip flop is connected to the first clock signal output terminal and the second clock signal output part of the first clock output module respectively, the source electrode of described Open-loop amplifier first metal-oxide-semiconductor, the source electrode of the second metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor and the source electrode of the 8th metal-oxide-semiconductor are all connected to vdd terminal, the grid of described first metal-oxide-semiconductor is connected with the grid of the second metal-oxide-semiconductor, the grid of described 6th metal-oxide-semiconductor is connected with the drain electrode of the first metal-oxide-semiconductor to the drain electrode of the 3rd metal-oxide-semiconductor, the grid of described 8th metal-oxide-semiconductor is connected with the drain electrode of the second metal-oxide-semiconductor to the drain electrode of the 4th metal-oxide-semiconductor, the source electrode of described 3rd metal-oxide-semiconductor is connected to the drain electrode of the 5th metal-oxide-semiconductor with the source electrode of the 4th metal-oxide-semiconductor, the source electrode of described 5th metal-oxide-semiconductor is connected to ground, the drain electrode of described 6th metal-oxide-semiconductor connects the drain electrode of the 7th metal-oxide-semiconductor, the source electrode of described 7th metal-oxide-semiconductor meets GND, the drain electrode of described 8th metal-oxide-semiconductor is connected to the input end of the first phase inverter with the drain electrode of the 9th metal-oxide-semiconductor, the source ground of described 9th metal-oxide-semiconductor, the grid of described 7th metal-oxide-semiconductor is connected with the grid of the drain electrode of the 7th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor, the described grid of the 3rd metal-oxide-semiconductor and the source electrode of the first metal-oxide-semiconductor are connected to the two ends of parallel magnetic tunnel-junction respectively, the grid of described 4th metal-oxide-semiconductor is connected to control logic circuit, the reversed-phase output of described first d type flip flop and the second d type flip flop exports the high position data and low data that store in parallel magnetic tunnel-junction respectively, described control logic circuit is also connected with one for providing the external voltage output circuit of reference voltage, also comprise 1 the tenth metal-oxide-semiconductor, the described grid of the 3rd metal-oxide-semiconductor and the tie point of parallel magnetic tunnel-junction are connected to the drain electrode of the tenth metal-oxide-semiconductor, the source ground of described tenth metal-oxide-semiconductor, the grid of described tenth metal-oxide-semiconductor connects the 3rd clock signal output terminal of second clock output module.
Described control logic circuit comprises the bidirectional switch circuit of the first clock signal control exported by the first d type flip flop reversed-phase output signal and the first clock signal output terminal, described bidirectional switch circuit comprises interconnective first two-way switch and the second two-way switch, and described bidirectional switch circuit is for controlling the connection of first, second, and third reference voltage output terminal of the 4th metal-oxide-semiconductor grid and external voltage output circuit.
Described first clock output module comprises the first delay circuit, the second delay circuit, the 3rd two-way switch and the 4th two-way switch, described first delay circuit and the second delay circuit are connected to the 3rd clock signal output terminal, and described 3rd two-way switch and the 4th two-way switch are respectively used to the connection of control first delay circuit and the second delay circuit and the first clock signal output terminal and second clock signal output part.The time delay being less than the second delay circuit time delay of described first delay circuit.
For allowing those skilled in the art more understand the technical solution of the utility model, specifically tell about principle of the present utility model below in conjunction with accompanying drawing.
There are two kinds of structures STT-RAM inside for the magnetic tunnel-junction (magnetic tunnel junctions, MTJs) storing data: serial magnetic tunnel-junction (as Suo Shi Fig. 1 (1)) and parallel magnetic tunnel-junction (as Suo Shi Fig. 1 (2)).
Serial magnetic tunnel-junction is mingled with one deck magnesium oxide oxide layer by two ferromagnetic layers and forms, and wherein bedding iron magnetosphere is reference layer (reference layer), have fixing magnetic to, and another layer of ferromagnetic layer is free layer (free layer), its magnetic is to changing by changing electric current (switching current), and when the magnetic of two ferromagnetic layers is to time contrary, magnetic tunnel-junction is in high-impedance state, when the magnetic of two ferromagnetic layers is to time identical, magnetic tunnel-junction is in low resistance state, and the free layer of parallel magnetic tunnel-junction by two can independently control magnetic to region form, wherein soft district (soft domain) only need by a small area analysis just can change magnetic to, hard area (hard domain) then need a larger electric current just can change magnetic to, because the magnetic in two regions is to there being four kinds of combinations, therefore parallel magnetic tunnel-junction has four kinds of resistance states, because parallel magnetic tunnel-junction has higher tunnel magnetoresistance rate (Tunneling Magneto-resistance ratio (TMR)), the advantages such as less switching current and higher reliability, so the utility model adopts parallel magnetic tunnel-junction as the storage organization of STT-RAM.
This patent proposes a kind of tree-shaped reading circuit scheme of novelty, adopts Open-loop amplifier as the comparer of reading circuit.Because Open-loop amplifier does not need reboot time, can compare continuously, therefore adopt Open-loop amplifier can improve the reading speed of circuit, there is reading time short advantage.Because the required voltage difference compared is also little, in order to the degree that less voltage amplification can be able to be identified to digital display circuit, the gain of comparer just needs larger.In order to increase the reliability that Open-loop amplifier docks with digital display circuit, the output voltage swing of Open-loop amplifier requires again larger.So in order to obtain larger gain and the amplitude of oscillation, this patent adopts the structure of the cascade of two stage amplifer shown in Fig. 2.While saving power consumption, obtain higher gain, the amplifier of the first order adopts the structure of cascade, and in order to obtain the larger amplitude of oscillation, the second level adopts the simple structure of common-source stage.In digital display circuit, usually require that the amplitude of oscillation of voltage equals operating voltage (VDD), the amplitude of oscillation of Open-loop amplifier can not reach this requirement.Output voltage swing due to phase inverter can equal operating voltage (VDD), the output voltage swing of divided ring amplifier can play the effect of amplification, therefore at the output terminal V of Open-loop amplifier
out 'be connected in series a phase inverter, make final output voltage swing can reach the requirement of digital display circuit to voltage swing, to increase the reliability of whole system signal transmission.
The circuit theory diagrams of the reading circuit designed by this patent as shown in Figure 3, because a parallel magnetic channel has four kinds of resistances, value relatable is: R11>R10>R01>R0 0, wherein R11, R10, R01, R00 be respectively store data be 11,10,01, the resistance corresponding to parallel magnetic tunnel-junction of 00, when the 3rd clock signal C ONT is high level, NMOS(the tenth metal-oxide-semiconductor M10) enter saturation region (the tenth metal-oxide-semiconductor M10 should be a long ditch metal-oxide-semiconductor), produce the reading electric current of a fixed value, this electric current flows through parallel magnetic tunnel-junction, can produce and read voltage Vin, because the data stored in parallel magnetic tunnel-junction are different, its resistance is different, the reading voltage Vin produced has 4 kinds of different magnitudes of voltage, its voltage relationship is: V11<V10<V01<V00, wherein V11, V10, V01, V00 is respectively and stores data 11, 10, 01, the reading magnitude of voltage corresponding to parallel magnetic tunnel-junction of 00, thus, we only need the magnitude of voltage being judged Vin by comparer, can accurately learn the data stored in parallel magnetic tunnel-junction, in order to accurately screen four kinds of magnitudes of voltage of Vin, reading circuit of the present utility model needs external voltage output circuit to produce 3 reference voltages (the first reference voltage Vref 1, second reference voltage Vref 2, 3rd reference voltage Vref 3), voltage relationship is: V11 < the 3rd reference voltage Vref 3 < V10 < second reference voltage Vref 2 <V01 < first reference voltage Vref 1< V00.
As shown in Figure 4, the principle of work of whole reading circuit is as follows for the voltage searching algorithm process flow diagram of the tree-shaped that the utility model adopts:
1, when the 3rd clock signal C ONT exported when the 3rd clock signal output terminal is high level, the tenth metal-oxide-semiconductor M10 opens, and produces and reads voltage Vin, and voltage Vin is read in steering logic order and the second reference voltage Vref 2 compares;
2, reading circuit enters the reading adopting the voltage search pattern of the tree-shaped scheme shown in Fig. 4 to carry out two bits:
(1) as Vin>Vref2, the reading voltage Vin that known parallel magnetic tunnel-junction produces only has two kinds of possibility (V01, V00), therefore the high position data that parallel magnetic tunnel-junction stores is 0, Open-loop amplifier output end vo ut ' output low level, first inverter output Vout exports high level, then, first clock output module produces a clock pulse signal, i.e. the first clock signal clk1, control the first d type flip flop and store high position data (because the output end vo ut ' of Open-loop amplifier must through the first phase inverter to increase output voltage swing, therefore the data that the first d type flip flop reads in will export from the reversed-phase output of the first d type flip flop, to obtain real high position data 1st), after the first d type flip flop storage high position data terminates, steering logic makes Vin carry out comparing of next step with the first reference voltage Vref 1, at this moment, if Vin>Vref1, the reading voltage that then parallel magnetic tunnel-junction produces only has this possibility of V00, the low data stored is 0, Open-loop amplifier output end vo ut ' output low level, first inverter output Vout exports high level, if Vin<Vref1, the reading voltage that then parallel magnetic tunnel-junction produces only has this possibility of V01, the low level of the data stored is 1, Open-loop amplifier output end vo ut ' exports high level, first inverter output Vout output low level, when obtain low data more out after, first clock output module regeneration one pulse signal second clock signal clk2, control the second d type flip flop storage low data (identical with the storage means of high position data, the low data 2nd obtained is exported) by the reversed-phase output of the second d type flip flop, such reading circuit just completes the reading process of 2bit data,
(2) as Vin<Vref2, the reading voltage that parallel magnetic tunnel-junction produces only has two kinds of possibility (V11, V10), therefore the height stored in parallel magnetic tunnel-junction is data is 1, Open-loop amplifier output end vo ut ' exports high level, first inverter output Vout output low level, then, first clock output module produces a clock pulse signal first clock signal clk1, control the first d type flip flop storage high position data (identical with the situation of Vin>Vref2, the data that first d type flip flop reads in will export from the reversed-phase output of the first d type flip flop, to obtain real high position data 1st), after the first d type flip flop storage high position data terminates, steering logic makes Vin carry out comparing of next step with the 3rd reference voltage Vref 3, if Vin>Vref3, the reading voltage that then parallel magnetic tunnel-junction produces only has this kind of possibility of V10, the low data stored is 0, Open-loop amplifier output end vo ut ' output low level, inverter output Vout exports high level, if Vin<Vref3, the reading voltage that then parallel magnetic tunnel-junction produces only has this kind of possibility of V11, the low data stored is 1, Open-loop amplifier output end vo ut ' exports high level, first inverter output Vout output low level, after the data obtaining low level, first clock output module regeneration one pulse signal second clock signal clk2, control the second d type flip flop storage low data (identical with the storage means of a high position, the low data 2nd obtained is exported) by the reversed-phase output of the second d type flip flop, such reading circuit just completes the reading process of 2bit data,
The control logic circuit that this patent adopts as shown in Figure 5, first two-way switch S1, second two-way switch S2 is respectively the bidirectional switch circuit (structure of two-way switch is as shown in circle in Fig. 5) controlled by high position data 1st and the first clock signal clk1, first, 3rd clock signal C ONT saltus step is at first high level, NMOS tube shown in Fig. 3 the tenth metal-oxide-semiconductor M10 enters opening, at this moment the first clock signal clk1 is also low level, controlling the second two-way switch S2 makes Vref and Vref2 be connected, Vin and Vref2 is made to compare, first phase inverter exports comparative result, after the first phase inverter exports comparative result, first clock signal clk1 jumps to high level, control the first d type flip flop and store high position data, and export high position data 1st by the reversed-phase output of the first d type flip flop, simultaneously, first clock signal clk1 controls the second two-way switch S2 and Vref and Vref ' is connected, at this moment, high position data 1st just can select corresponding reference voltage (Vref1 or Vref3) to be connected with Vref ' by controlling the first two-way switch S1, when high position data 1st is high level, first two-way switch S1 makes Vref ' be connected with Vref3, when high position data 1st is low level, the first two-way switch S1 makes Vref ' be connected with Vref1, and thus, the control logic circuit designed by this patent just achieves the controlling functions of reading circuit.
In order to reduce the input end of clock mouth of reading circuit, this patent adopts the first clock output module as shown in Figure 6, comprise the first delay circuit Buffer1, second delay circuit Buffer2, 3rd two-way switch S3 and the 4th two-way switch S4, 3rd two-way switch S3 in figure, shown in 4th two-way switch S4 and Fig. 5, the structure of switch is identical, only need to provide a clock signal the 3rd clock signal C ONT can produce the first clock signal clk1 and second clock signal clk2 signal, when the 3rd clock signal C ONT is low level, 3rd clock signal C ONT controls the 3rd two-way switch S3 and is connected with second clock signal clk2 and GND with the output first clock signal clk1 of the 4th two-way switch S4, like this when the 3rd clock signal C ONT is low level, first clock signal clk1 and second clock signal clk2 can be set to low level rapidly, when the 3rd clock signal C ONT is high level, controlling the 3rd two-way switch S3 makes the first clock signal output terminal and second clock signal output part be connected with the output terminal clk2 ' of the second delay circuit Buffer2 with the output terminal clk1 ' of the first delay circuit Buffer1 respectively with the 4th two-way switch S4, be less than the time delay of the second delay circuit Buffer2 the time delay of the first delay circuit Buffer1, and arrange the time delay of the first delay circuit Buffer1 and the second delay circuit Buffer2 and must meet following condition: when the 3rd clock signal C ONT is high level by low transition, whole circuit starts the comparison carrying out high position data, after comparative result Vout stable output Deng high position data, the time delay of the first delay circuit Buffer1 makes clk1 ' be high level by low transition, first clock signal clk1 is also high level by low transition, control the first d type flip flop and store high position data, then circuit starts the comparison carrying out low data, after the comparative result Vout stable output of low data such as only having, the delayed-action of the second delay circuit Buffer2 makes clk2 ' be high level by low transition, second clock signal clk2 is also high level by high level saltus step, control the first d type flip flop and store low data, like this, the circuit shown in Fig. 6 just can complete the function reducing input end of clock mouth quantity.
All circuit of the present utility model are all through the simulating, verifying of Cadence software, the technique of Global Foundries 0.18um is adopted to design, for one group of typical STT-RAM parameter index, adopt the reading electric current of 60 μ A to verify designed circuit, the resistance of four kinds of states and the magnitude of voltage of reading as shown in table 1.
The reference voltage level chosen is as shown in table 2.
Store to read the data instance that data are the parallel magnetic tunnel-junction of 11, verify the feasibility of the reading circuit designed by the present invention.Figure 7 shows that the present invention reads the analogous diagram of STT-RAM data.As known in the figure, input voltage V
infirst with V
ref2(V
ref=1.67V) compare, inverter output V
outoutput voltage be that 0V, clk1 read high-order data and enter in d type flip flop, then export real high position data (1 by the reversed-phase output of d type flip flop
st) be 1 for high level 1.8V(represents high position data), then steering logic is according to the high position data result read out, and selects V
ref3(V
ref=1.64V) and input voltage V
incompare, inverter output V
outoutput voltage be that 0 V, clk2 read the data of low level and enter in d type flip flop, then export real low data (2 by the reversed-phase output of d type flip flop
nd) be 1 for high level 1.8V(represents high position data).Reading circuit designed by the present invention achieves the reading of two bits.The crucial metal-oxide-semiconductor size that in the present invention, Fig. 3 circuit adopts is as shown in table 3.
Be more than preferred embodiment of the present utility model, all changes done according to technical solutions of the utility model, when the function produced does not exceed the scope of technical solutions of the utility model, all belong to protection domain of the present utility model.
Claims (4)
1. the STT-RAM reading circuit based on two-stage amplifier, it is characterized in that: the parallel magnetic tunnel-junction, control logic circuit and the first phase inverter that comprise an Open-loop amplifier and be connected with this Open-loop amplifier, described first phase inverter is also connected with the first d type flip flop and the second d type flip flop, and the clock control input end of described first d type flip flop and the second d type flip flop is connected to the first clock signal output terminal and the second clock signal output part of the first clock output module respectively, the source electrode of described Open-loop amplifier first metal-oxide-semiconductor, the source electrode of the second metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor and the source electrode of the 8th metal-oxide-semiconductor are all connected to vdd terminal, the grid of described first metal-oxide-semiconductor is connected with the grid of the second metal-oxide-semiconductor, the grid of described 6th metal-oxide-semiconductor is connected with the drain electrode of the first metal-oxide-semiconductor to the drain electrode of the 3rd metal-oxide-semiconductor, the grid of described 8th metal-oxide-semiconductor is connected with the drain electrode of the second metal-oxide-semiconductor to the drain electrode of the 4th metal-oxide-semiconductor, the source electrode of described 3rd metal-oxide-semiconductor is connected to the drain electrode of the 5th metal-oxide-semiconductor with the source electrode of the 4th metal-oxide-semiconductor, the source electrode of described 5th metal-oxide-semiconductor is connected to ground, the drain electrode of described 6th metal-oxide-semiconductor connects the drain electrode of the 7th metal-oxide-semiconductor, the source electrode of described 7th metal-oxide-semiconductor meets GND, the drain electrode of described 8th metal-oxide-semiconductor is connected to the input end of the first phase inverter with the drain electrode of the 9th metal-oxide-semiconductor, the source ground of described 9th metal-oxide-semiconductor, the grid of described 7th metal-oxide-semiconductor is connected with the grid of the drain electrode of the 7th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor, the described grid of the 3rd metal-oxide-semiconductor and the source electrode of the first metal-oxide-semiconductor are connected to the two ends of parallel magnetic tunnel-junction respectively, the grid of described 4th metal-oxide-semiconductor is connected to control logic circuit, the reversed-phase output of described first d type flip flop and the second d type flip flop exports the high position data and low data that store in parallel magnetic tunnel-junction respectively, described control logic circuit is also connected with one for providing the external voltage output circuit of reference voltage, also comprise 1 the tenth metal-oxide-semiconductor, the described grid of the 3rd metal-oxide-semiconductor and the tie point of parallel magnetic tunnel-junction are connected to the drain electrode of the tenth metal-oxide-semiconductor, the source ground of described tenth metal-oxide-semiconductor, the grid of described tenth metal-oxide-semiconductor connects the 3rd clock signal output terminal of second clock output module.
2. the STT-RAM reading circuit based on two-stage amplifier according to claim 1, it is characterized in that: described control logic circuit comprises the bidirectional switch circuit of the first clock signal control exported by the first d type flip flop reversed-phase output signal and the first clock signal output terminal, described bidirectional switch circuit comprises interconnective first two-way switch and the second two-way switch, and described bidirectional switch circuit is for controlling the connection of first, second, and third reference voltage output terminal of the 4th metal-oxide-semiconductor grid and external voltage output circuit.
3. the STT-RAM reading circuit based on two-stage amplifier according to claim 1, it is characterized in that: described first clock output module comprises the first delay circuit, the second delay circuit, the 3rd two-way switch and the 4th two-way switch, described first delay circuit and the second delay circuit are connected to the 3rd clock signal output terminal, and described 3rd two-way switch and the 4th two-way switch are respectively used to the connection of control first delay circuit and the second delay circuit and the first clock signal output terminal and second clock signal output part.
4. the STT-RAM reading circuit based on two-stage amplifier according to claim 3, is characterized in that: the time delay being less than the second delay circuit time delay of described first delay circuit.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104795094A (en) * | 2015-04-21 | 2015-07-22 | 福州大学 | STT-RAM readout circuit based on dual-stage amplifier and control method thereof |
| CN109119119A (en) * | 2018-08-29 | 2019-01-01 | 上海华虹宏力半导体制造有限公司 | sense amplifier |
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2015
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104795094A (en) * | 2015-04-21 | 2015-07-22 | 福州大学 | STT-RAM readout circuit based on dual-stage amplifier and control method thereof |
| CN104795094B (en) * | 2015-04-21 | 2017-06-06 | 福州大学 | STT RAM reading circuits and its control method based on dual-stage amplifier |
| CN109119119A (en) * | 2018-08-29 | 2019-01-01 | 上海华虹宏力半导体制造有限公司 | sense amplifier |
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