CN204557029U - A kind of device architecture increasing LCOS pixel unit circuit memory capacitance - Google Patents

Abstract

The utility model proposes a device structure for enlarging the storage capacitance of an LCOS pixel unit circuit of a silicon-based liquid crystal display panel, and belongs to the microelectronic technical field of the information science and technology subject. The LCOS pixel unit device structure is set on a P-type silicon substrate, with N-type wells, PMOS access transistors, NMOS access transistors, pixel capacitors, stacked metal capacitors and narrow deep P ⁺ injection capacitors. The utility model establishes a reasonable pixel unit device structure, and the NMOS access transistor and the PMOS access transistor form a complementary MOS transmission gate, which effectively reduces the loss of pixel input data, and manufactures high density by rationally utilizing the existing metal layer of the process The stacked metal capacitor forms a narrow plate capacitor by implanting P ⁺ deep inside the P-type silicon substrate, and connects the above two capacitors in parallel with the pixel capacitance of the pixel unit, thereby increasing the capacitance value of the storage capacitor.

Description

A device structure for increasing storage capacity of LCOS pixel unit circuit

technical field

The utility model belongs to the microelectronic application technical field of the information science and technology subject, in particular to a silicon-based liquid crystal display pixel unit device structure field.

Background technique

Liquid Crystal on Silicon (LCOS, Liquid Crystal on Silicon) technology is a reflective new display technology that organically combines Liquid Crystal Display (LCD, Liquid Crystal Display) technology and Complementary Metal Oxide Semiconductor (CMOS, Complementary Metal Oxide Semiconductor) integrated circuit technology.

Usually the LCOS pixel unit circuit is composed of an N-channel Metal Oxide Semiconductor (NMOS, N-channel MetalOxide Semiconductor) transistor and a storage capacitor connected in series (R.Ishii, S.Katayama, H.Oka, S.yamazaki, S.lino "U.Efron, I.David, V.Sinelnikov, B.Apter "A CMOS/LCOS Image Transceiver Chip for Smart Goggle Applications" "IEEE TRANSACTIONS ON CIRCUITSAND SYSTEMS FOR VIDEO TECHNOLOGY", Volume 14, Issue 2, 2004 February, P269). The LCOS drive silicon substrate regularly (frame period) inputs data charges to the storage capacitor through the NMOS access transistor. In order to keep the charge leakage on the capacitor in each frame period less than 5%, a high-density storage capacitor ( Edited by the 142nd Committee of the Japan Society for the Promotion of Science, translated by Huang Ximin, Huang Huiguang, and Li Zhirong, "Liquid Crystal Device Handbook", Aviation Industry Press, 1992, P442). In the CMOS semiconductor process, the storage capacitor is usually implemented with a PIP structure and a MOS structure , these storage capacitors are arranged on the same plane as the transistors, and when the layout area of the pixel device is reduced, the capacitance of the storage capacitors will drop sharply.

Therefore, how to establish a reasonable pixel unit device structure, fully and effectively utilize the layout space of the pixel device, and prepare a high-density storage capacitor that meets the requirements is an important research topic of LCOS display technology at present.

Utility model content

The purpose of the utility model is to solve the problem of how to make full and effective use of the layout space of the pixel device to prepare a high-density storage capacitor meeting the requirements.

The purpose of this utility model is achieved in that:

A device structure for enlarging the storage capacitance of an LCOS pixel unit circuit of a silicon-based liquid crystal display panel, comprising a PMOS access transistor (1), an NMOS access transistor (2), an N-type well (3), and a first pixel capacitance (4) , the first stacked metal capacitor (5), the first narrow deep P ⁺ injection capacitor (6), the second pixel capacitor (7), the second stacked metal capacitor (8), the second narrow deep P ⁺ injection capacitor (9) and P-type silicon substrate (10); said N-type well (3), NMOS access transistor (2), first narrow deep P ⁺ injection capacitor (6) and second narrow The type deep P ⁺ injection capacitor (9) is placed on the P-type silicon substrate (10), and the PMOS access transistor (1) is placed in the N-type well (3); the gate G of the NMOS access transistor (2) is connected to On the first addressing signal line SCAN, the drain D is connected to the first pixel capacitor (4); the gate G of the PMOS access transistor (1) is connected to the second addressing signal line SCAN, and the drain D is connected to The second pixel capacitor (7); the drain of the PMOS access transistor (1) is connected to the drain of the NMOS access transistor (2), and the source of the PMOS access transistor (1) is connected to the drain of the NMOS access transistor (2). The sources S are all connected to the data input line DATA of the same column to receive image information; the NMOS access transistor (2) and the PMOS access transistor (1) form a complementary MOS transmission gate; covering the first pixel capacitance (4) The first layer of metal M1, the second layer of metal M2, the third layer of metal M3 and the fourth layer of metal M4 form the first stacked metal capacitor (5), the first pixel capacitor (4), the first stacked metal capacitor The capacitor (5) and the first narrow-type deep P+ injection capacitor (7) have a common end and are connected in parallel; the first layer of metal M1 of the first stacked metal capacitor (5) connected to the NMOS access transistor (2) is connected To ground signal line GND. The first layer of metal M1, the second layer of metal M2, the third layer of metal M3 and the fourth layer of metal M4 covering the second pixel capacitor (7) form a second stacked metal capacitor (8), and the second pixel The capacitor (7), the second stacked metal capacitor (8) and the second narrow deep P+ injection capacitor (9) have a common end, that is, they are connected in parallel; the second stacked metal capacitor connected to the PMOS access transistor (1) The first layer of metal M1 in the capacitor (8) is connected to the power signal line VCC. The NMOS access transistor (2) and the PMOS access transistor (1) form a complementary MOS transmission gate, which effectively reduces the loss of pixel input data. The pixel capacitor, the stacked metal capacitor and the narrow deep P+ injection capacitor have a common terminal, thereby increasing the unit capacitance of the storage capacitor and improving the performance of the LCOS.

The pixel capacitor is a transistor capacitor, the source and drain of the transistor are connected to the body of the transistor, the gate of the pixel capacitor is the upper plate of the pixel, the lower plate of the pixel is below the upper plate of the pixel, and the lower plate of the pixel is on the The technical field is also commonly referred to as the OD layer.

One end of the first narrow deep P ⁺ injection capacitor is connected to the drain of the NMOS access transistor, and the other end is connected to the lower plate of the first pixel capacitor; one end of the second narrow deep P ⁺ injection capacitor is connected to The drain of the PMOS access transistor is connected to the lower plate of the second pixel capacitor.

The addressing signal lines, ground signal lines and power signal lines are arranged horizontally and are formed by the second layer of metal in the stacked metal capacitor; the column data input signal lines are arranged vertically and are formed by the first layer of the stacked metal capacitor. metal formation.

The first layer of metal (M1) in the first stacked metal capacitor and the second stacked metal capacitor is connected to the third layer of metal (M3) through the first through hole (V1) and the second through hole (V2). connection, the second layer of metal (M2) is connected to the fourth layer of metal (M4) through the second via (V2) and the third via (V3).

Advantage and beneficial effect of the utility model:

Provide a new device structure for increasing the storage capacitor of the LCOS pixel unit circuit. On the limited layout area of the pixel device, the existing metal layer of the process is rationally used to manufacture high-density stacked metal capacitors, and the narrow P+ is formed by deep implantation. A flat-plate capacitor is used, and the above two capacitors are connected in parallel with the pixel capacitance of the pixel unit, thereby increasing the unit capacitance value of the storage capacitor.

Description of drawings

Figure 1 Schematic diagram of LCOS pixel unit device structure.

Figure 2 The layout structure diagram of NMOS access transistors and three parallel capacitors.

Figure 3 shows a cross-sectional view of a stacked metal capacitor layout.

In the figure, 1. PMOS access transistor, 2. NMOS access transistor, 4. The first pixel capacitor, 5. The first stacked metal capacitor, 6. The first narrow deep P+ injection capacitor, 7. The second pixel Capacitor, 8. The second stacked metal capacitor, 9. The second narrow deep P+ injection capacitor, 10. P-type silicon substrate;

CT contact hole

V1 first through hole

V2 second through hole

V3 The third through hole

M1 The first layer of metal

M2 second layer metal

M3 The third layer of metal

M4 The fourth layer of metal

G grid

S source

D drain

SCAN addressing signal line

DATA column data input signal line

VCC power signal line

GND ground signal line.

Detailed ways

The utility model is described in further detail below:

A device structure for enlarging the storage capacitance of an LCOS pixel unit circuit of a silicon-based liquid crystal display panel, comprising a PMOS access transistor (1), an NMOS access transistor (2), an N-type well (3), and a first pixel capacitance (4) , the first stacked metal capacitor (5), the first narrow deep P ⁺ injection capacitor (6), the second pixel capacitor (7), the second stacked metal capacitor (8), the second narrow deep P ⁺ Injection capacitor (9) and P-type silicon substrate (10).

The PMOS access transistor (1) located in the upper half is placed in the N-type well region (3), and its gate G is connected to the first layer metal M1 through the contact hole CT, and then connected to the addressing transistor through the first through hole V1 The signal line SCAN, and the NMOS access transistor (2) in the lower half is placed on the P-type silicon substrate (6), and its gate G is connected to the first layer of metal M1 through the contact hole CT, and then through the first through hole V1 is connected to another addressing signal line SCAN. The source S in the upper half of the PMOS access transistor (1) and the lower half of the NMOS access transistor (2) is connected to the source S, and the drain D is connected to the drain D; the source S of the access transistor is connected to The hole CT is connected to the column data input line DATA, the drain D of the NMOS access transistor (2) is connected to the first layer metal M1 through two contact holes CT, and then connected to the first pixel capacitance (4) through the contact hole CT The gate G of the PMOS access transistor (1) is connected to the first layer metal M1 through two contact holes CT, and then connected to the gate G of the second pixel capacitor (7) through the contact holes CT

The first pixel capacitor (4) and the second pixel capacitor (7) are transistor capacitors, and the source S and drain D of the transistor are connected to the body of the transistor. The gate G of the pixel capacitor is the upper plate of the pixel, and the lower plate of the pixel is below the upper plate of the pixel. The lower plate of the pixel is usually called the OD layer in the technical field. Partially overlapping, the size of the overlapping area determines its effective capacitance value.

The first stacked metal capacitor (5) is laid out above the space of the first pixel capacitor (4), and the second stacked metal capacitor (8) is laid out above the space of the second pixel capacitor (7). The capacitor is composed of a first layer of metal M1, a second layer of metal M2, a third layer of metal M3 and a fourth layer of metal M4. The first layer of metal M1 is connected to the third layer of metal M3 through the first through hole V1 and the second through hole V2, and the second layer of metal M2 is connected to the fourth layer of metal M4 through the second through hole V2 and the third through hole V3. .

The lower plate of the second pixel capacitor (7) in the N-type well region (3) is connected to the first layer of metal M1 through the contact hole CT, and then connected to the power signal line VCC through the first through hole V1; the P-type silicon substrate The lower plate of the first pixel capacitor (4) on (10) is connected to the first layer metal M1 through the contact hole CT, and then connected to the ground signal line GND through the first through hole V1. The pixel upper plate of the first pixel capacitor (4) is connected to the second layer metal M2 of the first stacked metal capacitor (5) through the contact hole CT and the first through hole V1, and is commonly connected to the NMOS access transistor (2 ), the drain electrode D of the first pixel capacitor (4) is connected to the first layer metal M1 of the first stacked metal capacitor (5) through the contact hole CT; the pixel of the second pixel capacitor (7) The upper plate is connected to the second layer metal M2 of the second stacked metal capacitor (8) through the contact hole CT and the first through hole V1, and is commonly connected to the drain D of the PMOS access transistor (1), and the second pixel The lower electrode plate of the pixel of the capacitor (7) is connected to the first layer metal M1 of the second stacked metal capacitor (8) through the contact hole CT, thereby forming the first pixel capacitor (4) and the first stacked metal capacitor The parallel connection of (5), the parallel connection of the second pixel capacitor (7) and the second stacked metal capacitor (8), increases the unit capacitance value of the storage capacitor.

The first narrow-type deep P ⁺ injection capacitor (6) is placed in the P-type silicon substrate (10), and one end of the capacitor is connected to the first layer metal M1 through the contact hole CT, and then connected to the NMOS access transistor ( 2) Drain D, the other end of the capacitor is connected to the first layer of metal M1 through the contact hole CT, and then connected to the lower plate of the first pixel capacitor (4) through the first through hole V1. The second narrow deep P ⁺ injection capacitor (9) is placed in the P-type silicon substrate (10), one end of the capacitor is connected to the first layer metal M1 through the contact hole CT, and then connected to the PMOS access transistor ( 1), the other end of the capacitor is connected to the first layer of metal M1 through the contact hole CT, and then connected to the lower plate of the second pixel capacitor (7) through the first through hole V1. So far, the first pixel capacitor (4), the parallel connection of the first narrow deep P+ injection capacitor (6) and the first stacked metal capacitor (5), the second pixel capacitor (7), and the second narrow deep P+ injection The parallel connection of the capacitor (9) and the second laminated metal capacitor (8) increases the unit capacitance value of the storage capacitor.

Fig. 1 shows a schematic diagram of the device structure of an embodiment of the utility model to increase the storage capacitance of the LCOS pixel unit circuit of the silicon-based liquid crystal display panel. The LCOS pixel unit has an addressing signal wiring SCAN, a power supply signal wiring VCC, and a column data input signal wiring DATA , ground signal wiring GND, an NMOS access transistor (2), a PMOS access transistor (1), an N-type well (3), a first pixel capacitor (4), a first stacked metal capacitor (5), First narrow deep P ⁺ injection capacitor (6), second pixel capacitor (7), second stacked metal capacitor (8), second narrow deep P ⁺ injection capacitor (9) and P-type silicon substrate (10) Composition. The first narrow deep P ⁺ injection capacitor (6), the first stacked metal capacitor (5) and the first pixel capacitor (4) located on the P-type silicon substrate are connected in parallel, and one end is connected to the NMOS access transistor 2 The drain D, the other end is connected to the ground signal wiring GND; the second narrow deep P ⁺ injection capacitor (9), the second stacked metal capacitor (8) and the second pixel capacitor (7) are connected in parallel, and one end is connected to the PMOS The drain D of the access transistor (1) is connected to the power signal wiring VCC at the other end. The source S of the NMOS access transistor (2) and the PMOS access transistor (1) are connected to the source S, and are commonly connected to the column data input signal wiring DATA, and the drain D is connected to the drain D.

Fig. 2 shows the layout structure diagram of the NMOS access transistor and the three parallel capacitors of the embodiment of the present invention, the NMOS access transistor (2) and the first pixel capacitor (4) are arranged on the same plane, and the first stacked metal capacitor (5) covering the first pixel capacitor (4). Located on the left and right of the gate G of the NMOS access transistor (2) are the drain D and the source S of the access transistor respectively, and the pixel upper plate of the first pixel capacitor (4) passes through the contact hole CT, the first The via hole V1 is connected to the second layer metal M2 of the first stacked metal capacitor (5), and is commonly connected to the drain D of the NMOS access transistor, and the lower plate of the pixel of the first pixel capacitor (4) passes through the contact hole CT The first layer of metal M1 connected to the first stacked metal capacitor (5) forms a parallel connection of the first pixel capacitor (4) and the first stacked metal capacitor (5). One end of the first narrow deep P ⁺ injection capacitor (6) is connected to the first layer metal M1 through the contact hole CT, and then connected to the drain D of the NMOS access transistor (2) through the contact hole CT, and the other end of the capacitor is connected through the contact hole CT is connected to the first layer of metal M1, and then connected to the lower plate of the first pixel capacitor (4) through the first through hole V1. So far, the parallel connection of the first pixel capacitor (4), the first narrow deep P+ injection capacitor (6) and the first stacked metal capacitor (5) is formed to increase the unit capacitance value of the storage capacitor. The layout structure diagram of the PMOS access transistor and the three parallel capacitors is the same as the layout structure diagram of the NMOS access transistor and the three parallel capacitors.

3 shows a cross-sectional view of the layout of the stacked metal capacitor according to the embodiment of the present invention. The layout of the first stacked metal capacitor is the same as that of the second stacked metal capacitor. The first layer of metal M1 is connected to the third layer of metal M3 through the first through hole V1 and the second through hole V2, and the second layer of metal M2 is connected to the fourth layer of metal M4 through the second through hole V2 and the third through hole V3. So far, the stacked metal capacitor (5) is constructed. Multi-layer metal plates are stacked vertically. From top to bottom, there is a capacitance between every two layers of metal. The odd-numbered layers of metal are connected together, and the even-numbered layers of metal are connected together. From the cross-section, two The intersection of two comb structures, the preparation of so-called stacked capacitors can obtain greater capacitance per unit chip area.

The above descriptions are only preferred embodiments of the present utility model, but the protection scope of the present utility model is not limited thereto. Any person skilled in the art can make appropriate changes or changes within the technical scope disclosed in the utility model, and such changes or changes should be covered within the protection scope of the utility model.

Claims (5)

1. A device structure that increases the storage capacitance of the LCOS pixel unit circuit of a liquid crystal-on-silicon display panel, is characterized in that comprising a PMOS access transistor (1), an NMOS access transistor (2), an N-type well (3), a first Pixel capacitor (4), the first stacked metal capacitor (5), the first narrow deep P ⁺ injection capacitor (6), the second pixel capacitor (7), the second stacked metal capacitor (8), the first Two narrow-type deep P ⁺ injection capacitors (9) and a P-type silicon substrate (10); the N-type well (3), NMOS access transistor (2), the first narrow-type deep P ⁺ injection capacitor (6 ) and the second narrow deep P ⁺ injection capacitor (9) are placed on the P-type silicon substrate (10), and the PMOS access transistor (1) is placed in the N-type well (3); The gate G of the NMOS access transistor (2) is connected to the first addressing signal line SCAN, and the drain D is connected to the first pixel capacitor (4); the gate G of the PMOS access transistor (1) is connected to the second On the addressing signal line SCAN, the drain D is connected to the second pixel capacitor (7); the drain of the PMOS access transistor (1) is connected to the drain of the NMOS access transistor (2), and the drain of the PMOS access transistor (1) The source of the NMOS access transistor (2) and the source S of the NMOS access transistor (2) are connected to the same column data input line DATA to receive image information; the NMOS access transistor (2) and the PMOS access transistor (1) form a complementary MOS transmission gate ; The first layer of metal (M1), the second layer of metal (M2), the third layer of metal (M3) and the fourth layer of metal (M4) covering the first pixel capacitor (4) form a first stacked type The metal capacitor (5), the first pixel capacitor (4), the first stacked metal capacitor (5) and the first narrow deep P+ injection capacitor (7) have a common terminal, that is, they are connected in parallel; and the NMOS access transistor (2) The first layer metal (M1) of the connected first stacked metal capacitor (5) is connected to the ground signal line GND; the first layer metal (M1) covering the second pixel capacitor (7), the second Layer metal (M2), third layer metal (M3) and fourth layer metal (M4) form the second stacked metal capacitor (8), the second pixel capacitor (7), the second stacked metal capacitor (8 ) and the second narrow-type deep P+ injection capacitor (9) have a common end and are connected in parallel; the first layer of metal M1 in the second stacked metal capacitor (8) connected to the PMOS access transistor (1) is connected to the power supply Signal line VCC; NMOS access transistor (2) and PMOS access transistor (1) form complementary MOS transmission gates. 2. the device structure of enlarging liquid crystal on silicon display panel LCOS pixel unit circuit storage capacitance as claimed in claim 1, is characterized in that, described pixel capacitance is transistor capacitance, and transistor source and drain are connected to this transistor. The main body and the gate of the pixel capacitor are the upper plate of the pixel, and the lower plate of the pixel is below the upper plate of the pixel. The lower plate of the pixel is usually called the OD layer in the technical field. 3. The device structure for enlarging the storage capacitor of the LCOS pixel unit circuit of a liquid crystal on silicon display panel as claimed in claim 2, wherein one end of the first narrow deep P ⁺ injection capacitor is connected to the NMOS access transistor The other end of the drain is connected to the lower plate of the first pixel capacitor; one end of the second narrow deep P ⁺ injection capacitor is connected to the drain of the PMOS access transistor, and the other end is connected to the lower plate of the second pixel capacitor. 4. The device structure for increasing the storage capacitance of the LCOS pixel unit circuit of a liquid crystal on silicon display panel as claimed in any one of claims 1 to 3, wherein the addressing signal line, the ground signal line and the power signal line The horizontal arrangement is formed by the second layer of metal; the column data input signal line is arranged vertically and is formed by the first layer of metal. 5. The device structure for enlarging the storage capacitor of the LCOS pixel unit circuit of a liquid crystal on silicon display panel as claimed in claim 4, wherein the first stacked metal capacitor and the second stacked metal capacitor are One layer of metal (M1) is connected to the third layer of metal (M3) through the first through hole (V1) and the second through hole (V2), and the second layer of metal (M2) is connected through the second through hole (V2) and the third layer of metal (M3). The via (V3) is connected to the fourth metal layer (M4).