CN204557029U - A kind of device architecture increasing LCOS pixel unit circuit memory capacitance - Google Patents
A kind of device architecture increasing LCOS pixel unit circuit memory capacitance Download PDFInfo
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- CN204557029U CN204557029U CN201520277647.9U CN201520277647U CN204557029U CN 204557029 U CN204557029 U CN 204557029U CN 201520277647 U CN201520277647 U CN 201520277647U CN 204557029 U CN204557029 U CN 204557029U
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Abstract
The utility model proposes a kind of device architecture increasing liquid crystal on silicon display panel LCOS pixel unit circuit memory capacitance, belong to the microelectronics technology of information science technology subject.LCOS pixel cell device architecture is arranged in P-type silicon substrate, has N-type trap, PMOS access transistor, nmos access transistor, pixel capacitance, laminated type metal capacitance and the dark P of narrow
+inject electric capacity.The utility model establishes rational pixel cell device architecture, nmos access transistor and PMOS access transistor form complementary MOS transmission gate, effectively reduce the loss of pixel input data, and manufacture High Density Stacked formula metal capacitance by the existing metal level of Appropriate application technique, by the P in the inner dark injection of P-type silicon substrate
+form narrow plate capacitor, and make above-mentioned two kinds of capacitors in parallel with the pixel capacitance of pixel cell, increased the capacitance of holding capacitor thus.
Description
Technical field
The utility model belongs to the microelectronic applications technical field of information science technology subject, particularly relates to a kind of Liquiid crystal on silicon (lcos) display pixel cell device architecture field.
Background technology
Liquiid crystal on silicon (lcos) display (LCOS, Liquid Crystal on Silicon) technology is liquid crystal display (LCD, LiquidCrystal Display) the novel display technique of reflection-type that organically combines of technology and complementary metal oxide semiconductor (CMOS) (CMOS, Complementary Metal OxideSemiconductor) integrated circuit technique.
Usual LCOS pixel unit circuit is by a N-type NMOS N-channel MOS N (NMOS, N-channel MetalOxide Semiconductor) transistor and 1 reservoir capacitor (R.Ishii in series, S.Katayama, H.Oka, S.yamazaki, S.lino " U.Efron, I.David, V.Sinelnikov, B.Apter " A CMOS/LCOS ImageTransceiver Chip for Smart Goggle Applications " " IEEE TRANSACTIONS ON CIRCUITSAND SYSTEMS FOR VIDEO TECHNOLOGY ", 14 volumes, 2nd phase, in February, 2004, P269).LCOS drives silicon substrate by nmos access transistor regular (frame period) to reservoir capacitor input data charge, 5% is less than in order to keep the charge leakage in per frame period on electric capacity, (JSPS the 142nd council compiles to need high-density city electric capacity, Huang Ximin, yellow glow, the melting of Lee is translated, " liquid crystal device handbook ", aircraft industry publishing house, 1992, P442).In cmos semiconductor technique, memory capacitance adopts PIP structure and MOS structure to realize usually, and these memory capacitance are in the layout of in the plane identical with transistor, and when the layout area of pixel arrangement reduces, the electric capacity of memory capacitance just can sharply decline.
Therefore how to set up rational pixel cell device architecture, fully effectively utilize the space of pixel arrangement in layout, preparing the high-density city capacitor meeted the requirements, is the important subject of current LCOS display technique.
Utility model content
The utility model object solves how fully effectively to utilize the space of pixel arrangement in layout, prepares the problem of the high-density city capacitor meeted the requirements.
The purpose of this utility model is achieved in that
Increase a device architecture for liquid crystal on silicon display panel LCOS pixel unit circuit memory capacitance, comprise PMOS access transistor (1), nmos access transistor (2), N-type trap (3), the first pixel capacitance (4), the first laminated type metal capacitance (5), the dark P of the first narrow
+inject electric capacity (6), the second pixel capacitance (7), the second laminated type metal capacitance (8), the dark P of the second narrow
+inject electric capacity (9) and P-type silicon substrate (10); Described N-type trap (3), nmos access transistor (2), the dark P of the first narrow
+inject electric capacity (6) and the dark P of the second narrow
+injecting electric capacity (9) is positioned in P-type silicon substrate (10), and PMOS access transistor (1) is positioned in N-type trap (3); The grid G of nmos access transistor (2) is connected on the first address signal line SCAN, and drain D is connected to the first pixel capacitance (4); The grid G of PMOS access transistor (1) is connected on the second address signal line SCAN, and drain D is connected to the second pixel capacitance (7); The drain electrode of PMOS access transistor (1) is connected with the drain electrode of nmos access transistor (2), and the source electrode of PMOS access transistor (1) and the source S of nmos access transistor (2) are all connected to same column data input line DATA to receive image information; Nmos access transistor (2) and PMOS access transistor (1) form complementary MOS transmission gate; Cover the first layer metal M1 on the first pixel capacitance (4), second layer metal M2, third layer metal M 3 and the 4th layer of metal M 4 and form the first laminated type metal capacitance (5), the dark P+ of the first pixel capacitance (4), the first laminated type metal capacitance (5) and the first narrow injects electric capacity (7) and has common port i.e. parallel connection; The first layer metal M1 of the first laminated type metal capacitance (5) be connected with nmos access transistor (2) is connected to earth signal line GND.Cover the first layer metal M1 on the second pixel capacitance (7), second layer metal M2, third layer metal M 3 and the 4th layer of metal M 4 and form the second laminated type metal capacitance (8), the dark P+ of the second pixel capacitance (7), the second laminated type metal capacitance (8) and the second narrow injects electric capacity (9) and has common port i.e. parallel connection; First layer metal M1 in the second laminated type metal capacitance (8) be connected with PMOS access transistor (1) is connected to power signal line VCC.Nmos access transistor (2) and PMOS access transistor (1) form complementary MOS transmission gate, effectively reduce the loss of pixel input data.The dark P+ of pixel capacitance, laminated type metal capacitance and narrow injects electric capacity and has common port, is increased the unit capacitance values of holding capacitor thus, and promotes the usefulness of LCOS.
Described pixel capacitance is transistor capacitance, and transistor source and drain electrode are connected to the body of this transistor, and the grid of pixel capacitance is pixel top crown, and be pixel bottom crown below pixel top crown, pixel bottom crown is also called OD layer usually in technical field.
The described dark P of the first narrow
+inject the drain electrode that electric capacity one end is connected to nmos access transistor, the other end is connected to the lower step of the first pixel capacitance; The described dark P of the second narrow
+inject the drain electrode that electric capacity one end is connected to PMOS access transistor, the other end is connected to the lower step of the second pixel capacitance.
Described address signal line, earth signal line and power signal line lateral arrangement, formed by the second layer metal in laminated type metal capacitance; Column data input signal cable is longitudinally arranged, is formed by the first layer metal in laminated type metal capacitance.
First layer metal (M1) in described first laminated type metal capacitance and the second laminated type metal capacitance is connected with third layer metal (M3) with the second through hole (V2) by the first through hole (V1), and second layer metal (M2) is connected with the 4th layer of metal (M4) with third through-hole (V3) by the second through hole (V2).
Advantage of the present utility model and beneficial effect:
A kind of device architecture of increase LCOS pixel unit circuit memory capacitance is newly provided, on the layout area that pixel arrangement is limited, High Density Stacked formula metal capacitance is manufactured by the existing metal level of Appropriate application technique, narrow plate capacitor is formed by deeply injecting P+, and make above-mentioned two kinds of capacitors in parallel with the pixel capacitance of pixel cell, increased the unit capacitance values of holding capacitor thus.
Accompanying drawing explanation
Fig. 1 LCOS pixel cell device architecture schematic diagram.
Fig. 2 nmos access transistor and three shunt capacitance layout structure figure.
Fig. 3 shows the sectional view of laminated type metal capacitance layout.
In figure, 1, PMOS access transistor, 2, nmos access transistor, 4, the first pixel capacitance, the 5, first laminated type metal capacitance, the dark P+ of the 6, first narrow injects electric capacity, 7, the second pixel capacitance, 8, the second laminated type metal capacitance, the dark P+ of the 9, second narrow injects electric capacity, and 10, P-type silicon substrate;
CT contact hole
V1 first through hole
V2 second through hole
V3 third through-hole
M1 first layer metal
M2 second layer metal
M3 third layer metal
M4 the 4th layer of metal
G grid
S source electrode
D drains
SCAN address signal line
DATA column data input signal cable
VCC power signal line
GND earth signal line.
Embodiment
Below the utility model is further described in detail:
Increase a device architecture for liquid crystal on silicon display panel LCOS pixel unit circuit memory capacitance, comprise PMOS access transistor (1), nmos access transistor (2), N-type trap (3), the first pixel capacitance (4), the first laminated type metal capacitance (5), the dark P of the first narrow
+inject electric capacity (6), the second pixel capacitance (7), the second laminated type metal capacitance (8), the dark P of the second narrow
+inject electric capacity (9) and P-type silicon substrate (10).
The PMOS access transistor (1) being arranged in the first half is placed on N-type well region (3), its grid G is connected to first layer metal M1 by contact hole CT, address signal line SCAN is connected to again by the first through hole V1, and the nmos access transistor of Lower Half (2) is placed in P-type silicon substrate (6), its grid G is connected to first layer metal M1 by contact hole CT, then is connected to another address signal line SCAN by the first through hole V1.The source S being positioned at first half PMOS access transistor (1) and Lower Half nmos access transistor (2) is connected with source S, drain D is connected with drain D; The source S of access transistor is connected on column data input line DATA by contact hole CT, the drain D of nmos access transistor (2) is connected to first layer metal M1 via two contact hole CT, then is connected to the grid G of the first pixel capacitance (4) by contact hole CT; The drain D of PMOS access transistor (1) is connected to first layer metal M1 via two contact hole CT, then is connected to the grid G of the second pixel capacitance (7) by contact hole CT
First pixel capacitance (4) and the second pixel capacitance (7) are transistor capacitance, and transistor source S and drain D are connected to the body of this transistor.The grid G of pixel capacitance is pixel top crown, it is pixel bottom crown below pixel top crown, pixel bottom crown is also called OD layer usually in technical field, overlaps between pixel bottom crown and pixel top crown, and the size of overlapping region determines its effective capacitance value.
First laminated type metal capacitance (5) is in the layout of on the first pixel capacitance (4) space, second laminated type metal capacitance (8) is in the layout of on the second pixel capacitance (7) space, and laminated type metal capacitance is made up of first layer metal M1, second layer metal M2, third layer metal M 3 and the 4th layer of metal M 4.Wherein first layer metal M1 is connected with third layer metal M 3 by the first through hole V1, the second through hole V2, and second layer metal M2 is connected to the 4th layer of metal M 4 by the second through hole V2, third through-hole V3.
The second pixel capacitance (7) bottom crown in N-type well region (3) is connected to first layer metal M1 by contact hole CT, then is connected to power signal line VCC by the first through hole V1; The first pixel capacitance (4) bottom crown in P-type silicon substrate (10) is connected to first layer metal M1 by contact hole CT, then is connected to earth signal line GND by the first through hole V1.The pixel top crown of the first pixel capacitance (4) is connected to the second layer metal M2 of the first laminated type metal capacitance (5) by contact hole CT, the first through hole V1, jointly be connected to the drain D of nmos access transistor (2), the pixel bottom crown of the first pixel capacitance (4) is connected to the first layer metal M1 of the first laminated type metal capacitance (5) by contact hole CT, the pixel top crown of the second pixel capacitance (7) is by contact hole CT, first through hole V1 is connected to the second layer metal M2 of the second laminated type metal capacitance (8), jointly be connected to the drain D of PMOS access transistor (1), the pixel bottom crown of the second pixel capacitance (7) is connected to the first layer metal M1 of the second laminated type metal capacitance (8) by contact hole CT, the parallel connection of the first pixel capacitance (4) and the first laminated type metal capacitance (5) is formed with this, the parallel connection of the second pixel capacitance (7) and the second laminated type metal capacitance (8), increase the unit capacitance values of holding capacitor.
The dark P of first narrow
+injecting electric capacity (6) is positioned in P-type silicon substrate (10), electric capacity one end is connected to first layer metal M1 by contact hole CT, the drain D of nmos access transistor (2) is connected to again by contact hole CT, the electric capacity other end is connected to first layer metal M1 by contact hole CT, then is connected to the bottom crown of the first pixel capacitance (4) by the first through hole V1.The dark P of second narrow
+injecting electric capacity (9) is positioned in P-type silicon substrate (10), electric capacity one end is connected to first layer metal M1 by contact hole CT, the drain D of PMOS access transistor (1) is connected to again by contact hole CT, the electric capacity other end is connected to first layer metal M1 by contact hole CT, then is connected to the bottom crown of the second pixel capacitance (7) by the first through hole V1.So far the first pixel capacitance (4) is formed, the dark P+ of first narrow injects the parallel connection of electric capacity (6) and the first laminated type metal capacitance (5), second pixel capacitance (7), the dark P+ of second narrow injects the parallel connection of electric capacity (9) and the second laminated type metal capacitance (8), increases the unit capacitance values of memory capacitance.
Fig. 1 shows a kind of device architecture schematic diagram increasing liquid crystal on silicon display panel LCOS pixel unit circuit memory capacitance of the utility model embodiment, and LCOS pixel cell has address signal wiring SCAN, power supply signal wiring VCC, column data input signal wiring DATA, earth signal wiring GND, nmos access transistor (2), PMOS access transistor (1), N-type trap (3), the first pixel capacitance (4), the first laminated type metal capacitance (5), the dark P of the first narrow
+inject electric capacity (6), the second pixel capacitance (7), the second laminated type metal capacitance (8), the dark P of the second narrow
+inject electric capacity (9) and P-type silicon substrate (10) composition.Wherein be positioned at the dark P of the first narrow of P-type silicon substrate
+inject electric capacity (6), the first laminated type metal capacitance (5) and the first pixel capacitance (4) in parallel, one end is connected to the drain D of nmos access transistor 2, and the other end is connected to earth signal wiring GND; The dark P of second narrow
+inject electric capacity (9), the second laminated type metal capacitance (8) and the second pixel capacitance (7) in parallel, one end is connected to the drain D of PMOS access transistor (1), and the other end is connected to power supply signal wiring VCC.Nmos access transistor (2) is connected with source S with the source S of PMOS access transistor (1), and is jointly connected to column data input signal wiring DATA, and drain D is connected with drain D.
Fig. 2 shows nmos access transistor and the three shunt capacitance layout structure figure of the utility model embodiment, on the same plane, the first laminated type metal capacitance (5) covers the top of the first pixel capacitance (4) for nmos access transistor (2) and the first pixel capacitance (4) layout.Be positioned at drain D and source S that the grid G left of nmos access transistor (2) and right are respectively access transistor, the pixel top crown of the first pixel capacitance (4) is by contact hole CT, first through hole V1 is connected to the second layer metal M2 of the first laminated type metal capacitance (5), jointly be connected to the drain D of nmos access transistor, the pixel bottom crown of the first pixel capacitance (4) is connected to the first layer metal M1 of the first laminated type metal capacitance (5) by contact hole CT, the parallel connection of the first pixel capacitance (4) and the first laminated type metal capacitance (5) is formed with this.The dark P of first narrow
+inject electric capacity (6) one end and be connected to first layer metal M1 by contact hole CT, the drain D of nmos access transistor (2) is connected to again by contact hole CT, the electric capacity other end is connected to first layer metal M1 by contact hole CT, then is connected to the bottom crown of the first pixel capacitance (4) by the first through hole V1.So far form the first pixel capacitance (4), the dark P+ of the first narrow injects the parallel connection of electric capacity (6) and the first laminated type metal capacitance (5), increases the unit capacitance values of memory capacitance.PMOS access transistor is identical with three shunt capacitance layout structure figure with nmos access transistor with three shunt capacitance layout structure figure.
Fig. 3 shows the sectional view of the laminated type metal capacitance layout of the utility model embodiment, and the first laminated type metal capacitance layout is identical with the second laminated type metal capacitance layout.First layer metal M1 is connected with third layer metal M 3 by the first through hole V1, the second through hole V2, and second layer metal M2 is connected to the 4th layer of metal M 4 by the second through hole V2, third through-hole V3, so far construction complete laminated type metal capacitance (5).Multimetal offset plate is vertically stacked, from top to bottom, all electric capacity is there is between every double layer of metal, the metal of odd-level is linked together, the metal of even level is coupled together simultaneously, from section, obtain the intersection of two pectinations, preparing so-called stacked capacitor can obtain larger electric capacity on unit chip area.
The foregoing is only preferred implementation of the present utility model, but the utility model protection domain is not limited thereto.Any those skilled in the art, in technical scope disclosed in the utility model, all can carry out suitable change or change to it, and this change or change all should be encompassed within protection domain of the present utility model.
Claims (5)
1. increase a device architecture for liquid crystal on silicon display panel LCOS pixel unit circuit memory capacitance, it is characterized in that comprising PMOS access transistor (1), nmos access transistor (2), N-type trap (3), the first pixel capacitance (4), the first laminated type metal capacitance (5), the dark P of the first narrow
+inject electric capacity (6), the second pixel capacitance (7), the second laminated type metal capacitance (8), the dark P of the second narrow
+inject electric capacity (9) and P-type silicon substrate (10); Described N-type trap (3), nmos access transistor (2), the dark P of the first narrow
+inject electric capacity (6) and the dark P of the second narrow
+injecting electric capacity (9) is positioned in P-type silicon substrate (10), and PMOS access transistor (1) is positioned in N-type trap (3);
The grid G of nmos access transistor (2) is connected on the first address signal line SCAN, and drain D is connected to the first pixel capacitance (4); The grid G of PMOS access transistor (1) is connected on the second address signal line SCAN, and drain D is connected to the second pixel capacitance (7); The drain electrode of PMOS access transistor (1) is connected with the drain electrode of nmos access transistor (2), and the source electrode of PMOS access transistor (1) and the source S of nmos access transistor (2) are all connected to same column data input line DATA to receive image information; Nmos access transistor (2) and PMOS access transistor (1) form complementary MOS transmission gate; Cover the first layer metal (M1) on the first pixel capacitance (4), second layer metal (M2), third layer metal (M3) and the 4th layer of metal (M4) and form the first laminated type metal capacitance (5), the dark P+ of the first pixel capacitance (4), the first laminated type metal capacitance (5) and the first narrow injects electric capacity (7) and has common port i.e. parallel connection; The first layer metal (M1) of the first laminated type metal capacitance (5) be connected with nmos access transistor (2) is connected to earth signal line GND; Cover the first layer metal (M1) on the second pixel capacitance (7), second layer metal (M2), third layer metal (M3) and the 4th layer of metal (M4) and form the second laminated type metal capacitance (8), the dark P+ of the second pixel capacitance (7), the second laminated type metal capacitance (8) and the second narrow injects electric capacity (9) and has common port i.e. parallel connection; First layer metal M1 in the second laminated type metal capacitance (8) be connected with PMOS access transistor (1) is connected to power signal line VCC; Nmos access transistor (2) and PMOS access transistor (1) form complementary MOS transmission gate.
2. the device architecture increasing liquid crystal on silicon display panel LCOS pixel unit circuit memory capacitance as claimed in claim 1, it is characterized in that, described pixel capacitance is transistor capacitance, transistor source and drain electrode are connected to the body of this transistor, the grid of pixel capacitance is pixel top crown, be pixel bottom crown below pixel top crown, pixel bottom crown is also called OD layer usually in technical field.
3. the device architecture increasing liquid crystal on silicon display panel LCOS pixel unit circuit memory capacitance as claimed in claim 2, is characterized in that, the described dark P of the first narrow
+inject the drain electrode that electric capacity one end is connected to nmos access transistor, the other end is connected to the lower step of the first pixel capacitance; The described dark P of the second narrow
+inject the drain electrode that electric capacity one end is connected to PMOS access transistor, the other end is connected to the lower step of the second pixel capacitance.
4. increase the device architecture of liquid crystal on silicon display panel LCOS pixel unit circuit memory capacitance as claimed any one in claims 1 to 3, it is characterized in that, described address signal line, earth signal line and power signal line lateral arrangement, formed by second layer metal; Column data input signal cable is longitudinally arranged, is formed by first layer metal.
5. the device architecture increasing liquid crystal on silicon display panel LCOS pixel unit circuit memory capacitance as claimed in claim 4, it is characterized in that, first layer metal (M1) in described first laminated type metal capacitance and the second laminated type metal capacitance is connected with third layer metal (M3) with the second through hole (V2) by the first through hole (V1), and second layer metal (M2) is connected with the 4th layer of metal (M4) with third through-hole (V3) by the second through hole (V2).
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110021238A (en) * | 2018-01-10 | 2019-07-16 | 佳能株式会社 | Show equipment and picture pick-up device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110021238A (en) * | 2018-01-10 | 2019-07-16 | 佳能株式会社 | Show equipment and picture pick-up device |
| US10985216B2 (en) | 2018-01-10 | 2021-04-20 | Canon Kabushiki Kaisha | Display apparatus and imaging apparatus |
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Granted publication date: 20150812 Termination date: 20160430 |