CN204465968U - The high precision constant current LED drive circuit utilizing digital method to realize - Google Patents
The high precision constant current LED drive circuit utilizing digital method to realize Download PDFInfo
- Publication number
- CN204465968U CN204465968U CN201520115256.7U CN201520115256U CN204465968U CN 204465968 U CN204465968 U CN 204465968U CN 201520115256 U CN201520115256 U CN 201520115256U CN 204465968 U CN204465968 U CN 204465968U
- Authority
- CN
- China
- Prior art keywords
- output
- input
- circuit
- frequency
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Landscapes
- Inverter Devices (AREA)
Abstract
The utility model discloses a kind of high precision constant current LED drive circuit utilizing digital method to realize, as far as possible with adopting digital circuit to replace traditional analog control circuit utilizing analogy method to realize in the LED drive circuit of constant current function in this drive circuit, the precision of this LED drive circuit is made only to be limited by matching degree between two charging current sources and discharging current source, and no longer by comparator imbalance voltage, the impact of reference voltage etc., namely the dependence to analog signal detection circuit is reduced, significantly improve constant current accuracy and the reliability of this LED drive circuit.
Description
Technical field
The utility model relates to a kind of LED drive circuit, and particularly a kind of high precision constant current LED drive circuit utilizing digital method to realize, belongs to the technical field of LED drive circuit.
Background technology
Along with the develop rapidly of Lighting Industry, for LED provides the switch power source driving circuit of electric energy to obtain fast development.Drive in application at LED, LED drives by electric current, and the average current flowing through LED determines the brightness of LED, and obtain stable LED luminance just needs stable average current.
Because the constant current formula correlated variables under DCM pattern is less, LED drive circuit is now under working in DCM pattern mostly.Under DCM pattern, output current average current formula is:
Wherein
for drive circuit exports average current,
for secondary side peak current,
for the demagnetization time,
for the drive circuit works cycle,
for primary edge peak current,
for primary limit coil turn,
for transformer secondary output limit coil turn.Realize the constant current under DCM mode of operation, mainly control
with
product be constant.
As shown in Figure 1, Fig. 1 is that traditional analogy method that utilizes realizes a kind of typical structure of the LED drive circuit of constant current function, in figure, demagnetization testing circuit 115 detects demagnetization time signal 127, described demagnetization detection signal 127 and the reverse signal 128 after reverser 116 is reverse carry out discharge and recharge respectively by closed charging current source 124 and the discharging current source 125 of making of control switch 117 and switch 118 for electric capacity 119, the triangular wave 126 of generation is compared rear generation with reference signal Vref by comparator 120 to output signal simultaneously, this output signal is held with the S of rest-set flip-flop 121 and is connected, the Q end output signal of described rest-set flip-flop 121 controls the closed of outside power tube 112 through overdrive circuit 122.In Fig. 1 circuit, when
with
when ratio is fixed, namely
for constant such as
time, this circuit working in stable state, otherwise automatically can regulate Dead Time namely the turn-on instant in next cycle go to regulate
.
But, mainly there is following shortcoming in the typical scenario shown in Fig. 1: the realization of constant current depends on demagnetization testing circuit 155 to the accuracy of detection of demagnetization time, and be limited by the offset voltage etc. of matcher between described charging current source 124 and discharging current source 125, described comparator 120, simultaneously, along with the change of technique, temperature, operating voltage, export average current and also can produce larger fluctuation.
Summary of the invention
Technical problem to be solved in the utility model is, a kind of LED constant-current drive circuit utilizing digital method to realize is provided, as far as possible with the analog circuit adopted in digital circuit replacement traditional circuit in this circuit, thus the dependence reduced circuit such as analog signal detection, significantly improve constant current accuracy and the reliability of this drive circuit.
For solving the problems of the technologies described above, the technical solution adopted in the utility model is: a kind of high precision constant current LED drive circuit utilizing digital method to realize, and this circuit comprises:
Control driving chip, described control driving chip comprises: demagnetization testing circuit, the described output of demagnetization testing circuit is connected with the first input end of frequency control unit, second input of described frequency control unit is connected with the output of lead-edge-blanking circuit, 3rd input of described frequency control unit is connected with the output of Current-Limiting Comparator, the output of described frequency control unit is connected with the first input end of frequency adjustment unit, second input of described frequency adjustment unit is connected with the output of oscillator, the output of described frequency adjustment unit holds with the CLKB of d type flip flop respectively and the four-input terminal of described frequency control unit is connected, the D end of described d type flip flop is connected with the output of internal electric source, the RB end of described d type flip flop is connected with the output of described Current-Limiting Comparator, the Q end of described d type flip flop is connected with the input of drive circuit, the output of described drive circuit is connected with the input of described lead-edge-blanking circuit and controls the closed of external power pipe, the voltage formed on the current-limiting resistance of series connection with it after the power tube conducting of the input detection outside of described Current-Limiting Comparator,
Described frequency control unit comprises: the first current source, second current source, first switch, second switch, AND circuit, electric capacity, Schmidt trigger, first reverser, second reverser, rest-set flip-flop, first d type flip flop, second d type flip flop and OR circuit, the first input end of described frequency control unit respectively with an input and described first d type flip flop of described AND circuit, the D end of the second d type flip flop connects, the four-input terminal of described frequency control unit is held with another input of described AND circuit and the CLKB of the second d type flip flop respectively and is connected, the output of described AND circuit controls the closed of described first switch, one end, other two ends of described first switch is connected with the output of described first current source, the other end is connected with the input of Schmidt trigger and is connected with the input of described second current source by capacity earth with by described second switch, the input of described first current source is connected with the 3rd input of described frequency control unit, described second current source output ground connection, the output of described Schmidt trigger is held with the S of described rest-set flip-flop by described first reverser and is connected, second input of described frequency control unit is held with the R of described rest-set flip-flop by described second reverser and is connected, the Q end of described rest-set flip-flop controls the closed of described second switch and holds with the CLKB of described first d type flip flop to be connected, described first d type flip flop is connected with the input of described OR circuit respectively with the Q end of the second d type flip flop, the output of described OR circuit is the output of described frequency control unit,
Described frequency adjustment unit comprises: N position up counter, N bit frequency reference cell, N bit digital comparator and 3d flip-flop, second input of described frequency adjustment unit is held with the CLKB of described N position up counter and is connected, the first input end of described frequency adjustment unit is connected with the input of described N bit frequency reference cell, the output of described N position up counter is connected with the negative input end of described N bit digital comparator, the output of described N bit frequency reference cell is connected with described N bit digital comparator positive input terminal, the output of described N bit digital comparator is held with the CLKB of described 3d flip-flop and is connected, the QB end of described 3d flip-flop is held with D and is connected, the Q end output signal of described 3d flip-flop is held with the reset terminal R of described N position up counter and is connected after delay circuit time delay, described output signal clocking after the 3rd reverser is reverse is sent to the CLKB end of described N bit frequency reference cell, the output of described 3rd reverser is the output of described frequency adjustment unit,
Described N bit frequency reference cell comprises: N position forward-backward counter, 4th inverter, upper limiting frequency base modules, lower frequency limit basic mode block and OR circuit, the mode of operation of the input input of described N bit frequency reference cell selects signal to be sent to the input of described N position forward-backward counter, the CLKB end of described N position forward-backward counter is the CLKB end of described N bit frequency reference cell, the output of described N position forward-backward counter exports N bit frequency reference signal as the output of described N bit frequency reference cell, the output of described N bit frequency reference cell is also connected with the input of described upper limiting frequency base modules and lower frequency limit base modules respectively, the output signal of described upper limiting frequency base modules and lower frequency limit base modules produces reset signal through described OR circuit and is sent to described N position forward-backward counter, when described mode of operation selects signal to be high level, upper limiting frequency base modules described in gating, closes described lower frequency limit basic mode block, otherwise, when mode of operation selects signal to be low level, then close upper limiting frequency base modules by described 4th inverter reverse backgating lower frequency limit base modules.
Further, the described high precision constant current LED drive circuit utilizing digital method to realize also comprises following peripheral circuit: rectification circuit, described rectification circuit exports electrochemical capacitor to, charging resistor is in parallel with described electrochemical capacitor after connecting with charging capacitor, armature winding is passed through successively in described charging resistor one end, described power tube, current-limiting resistance ground connection, the other end of described charging resistor is that described control driving chip is powered by interior source current, the secondary winding be coupled with described armature winding and fly-wheel diode and output capacitance form loop, external loading is in parallel with described output capacitance.
Further, in the described high precision constant current LED drive circuit utilizing digital method to realize, described rectification circuit is the bridge rectifier be made up of the first diode, the second diode, the 3rd diode and the 4th diode.
The utility model has the advantages that, as far as possible with adopting digital circuit to replace traditional analog control circuit utilizing analogy method to realize in the LED drive circuit of constant current function in the high precision constant current LED drive circuit that the utility model utilizes digital method to realize, the precision of this LED drive circuit is made only to be limited by matching degree between a charging current source and a discharging current source, and no longer by comparator imbalance voltage, the impact of reference voltage etc., namely the dependence to analog signal detection circuit is reduced, significantly improve constant current accuracy and the reliability of this LED drive circuit.
Accompanying drawing explanation
Fig. 1 is that traditional analogy method that utilizes realizes a kind of typical structure of the LED drive circuit of constant current function;
Fig. 2 is the circuit diagram of the high precision constant current LED drive circuit that the utility model utilizes digital method to realize;
Fig. 3 is the circuit diagram of frequency control unit shown in Fig. 2;
Fig. 4 is the sequential chart when output of frequency control unit shown in Fig. 2 is 0;
Fig. 5 is the sequential chart when output of frequency control unit shown in Fig. 2 is 1;
Fig. 6 is the circuit diagram of the unit of frequency adjustment shown in Fig. 2;
Fig. 7 is that the utility model utilizes analogy method to realize the sequential chart of the Continuity signal generation of the LED drive circuit of constant current function;
Fig. 8 is the circuit diagram of the bit frequency of N shown in Fig. 2 reference cell.
Embodiment
For disclosing the technical solution of the utility model further, be hereby described with reference to the accompanying drawings execution mode of the present utility model:
As Fig. 1, the course of work of conventional constant current LED drive circuit is roughly as follows: the title of this voltage of input exchange signal 85Vac to 265Vac is called line voltage in the utility model
described line voltage, through described rectification circuit, becomes half-wave, then through the filtering of described electrochemical capacitor 105, become approximate DC high pressure, this high direct voltage charges to described charging capacitor 107 by described charging resistor 106, makes vdd voltage increase, and reaches certain value when VDD rises, Traditional control driving chip 114 is started working, general first time conduction module makes described power tube 112 produce first time conducting, after the conducting of described power tube 112, and described line voltage
successively through the armature winding 108 of inductance L transformer can regard as the inductance on a left side, described power tube 112, current-limiting resistance 113 until to form a path.By line voltage described in above-mentioned path
to described induction charging, the linear rising of electric current of above-mentioned path, slope is approximately
.The electric current of above-mentioned path forms the voltage be directly proportional to current value on described current-limiting resistance 113, this voltage signal is held at CS, described Traditional control driving chip 114 detects this voltage, innerly when this voltage reaches certain value produce a cut-off signals and go to control described power tube 112 and close by described Current-Limiting Comparator 123 realization, the linear rising of electric current namely from described armature winding 108 to the path on ground, when reaching certain value, described power tube 112 turns off, and current break is 0 because this path blockade now from described armature winding 108 to the path on ground.Described power tube 112 is called from the process reaching closedown
oN time Ton.
Described power tube 112 closes has no progeny, and the inductance that the secondary winding be coupled with described armature winding 108 can regard as a right starts the process of demagnetizing, and path linear decline from an initial current at described secondary winding place, until linearly drop to 0.The electric current of described secondary winding place path linearly drops to the process of 0 demagnetization process from initial value, this process elapsed-time standards
demagnetization time Tdemag.Demagnetization phenomenon can be detected by the demagnetization testing circuit 114 of described Traditional control driving chip 114 inside.
The purpose of this utility model is: utilize digital method to realize accurately controlling the output current mean value of LED drive circuit, to solve the problem such as precision, flow-route and temperature that LED constant-current control circuit in prior art too much depends on analog signal and testing circuit as far as possible.
Output average current of the present utility model can be expressed as:
Wherein
drive circuit exports average current,
for secondary side peak current,
for the demagnetization time,
for the drive circuit works cycle,
for primary edge peak current,
for primary limit coil turn,
for transformer secondary output limit coil turn.
Utility model thinking of the present utility model is: detect
with
compare here
for ON time, k is configurable constant, and representative value is 2,
the demagnetization time obtained desired by the utility model and the ratio in cycle, namely
with
compare, be in fact exactly
compare with 0.Judge according to comparative result
with
magnitude relationship, unlike the prior art, although the LED drive circuit of the course of work of the present utility model and aforementioned conventional is similar, but, as shown in Figure 2, described frequency control unit 206 Output rusults in figure is digital quantity 1 or 0 instead of analog quantity, and this output digit signals goes to control described frequency adjustment unit 205, and control cycle stepping increases or reduces respectively.If
, namely
, then output digit signals 1, this digital signal 1 removes control cycle step by step modulating.In specific embodiment below, conveniently state, k is taken as representative value 2 without loss of generality.
As an embodiment of the present utility model, Fig. 2 is the circuit diagram of the high precision constant current LED drive circuit that the utility model utilizes digital method to realize, as shown in Figure 2, figure comprises: control driving chip 201, described control driving chip 201 comprises: demagnetization testing circuit 204, the output of described demagnetization testing circuit 204 is connected with the first input end of frequency control circuit 206, second input of described frequency control unit 206 is connected with the output of lead-edge-blanking circuit 210, 3rd input of described frequency control unit 206 is connected with the output of Current-Limiting Comparator 209, the output of described frequency control unit 206 is connected with the first input end of frequency adjustment unit 205, second input of described frequency adjustment unit 205 is connected with the output of oscillator 203, the output of described frequency adjustment unit 205 holds with the CLKB of d type flip flop 207 respectively and the four-input terminal of described frequency control unit 206 is connected, the D end of described d type flip flop 207 is connected with the output of internal electric source 202, the RB end of described d type flip flop 207 is connected with the output of described Current-Limiting Comparator 209, the Q end of described d type flip flop 207 is connected with the input of drive circuit 208, the output of described drive circuit 208 is connected with the input of described lead-edge-blanking circuit 210 and controls the closed of external power pipe 112, the voltage formed on the current-limiting resistance 113 of series connection with it after power tube 112 conducting of the input detection outside of described Current-Limiting Comparator 209.
As shown in Figure 3, described frequency control unit 206 comprises: the first current source 301, second current source 304, first switch 302, second switch 303, AND circuit 313, electric capacity 306, Schmidt trigger 305, first reverser 307, second reverser, rest-set flip-flop 308, first d type flip flop 316, second d type flip flop 317 and OR circuit 318, the first input end of described frequency control unit 206 respectively with an input and described first d type flip flop 316 of described AND circuit 313, the D end of the second d type flip flop 317 connects, the four-input terminal of described frequency control unit 206 is held with another input of described AND circuit 313 and the CLKB of the second d type flip flop 317 respectively and is connected, the output of described AND circuit 313 controls the closed of described first switch 302, one end, other two ends of described first switch 302 is connected with the output of described first current source 301, the other end is connected with the input of Schmidt trigger 305 and passes through electric capacity 306 ground connection and be connected with the input of described second current source 304 by described second switch 303, the input of described first current source 301 is connected with the 3rd input of described frequency control unit 206, described second current source 304 output head grounding, the output of described Schmidt trigger 305 is held with the S of described rest-set flip-flop 308 by described first reverser 307 and is connected, second input of described frequency control unit 206 is held with the R of described rest-set flip-flop 308 by described second reverser and is connected, the Q end of described rest-set flip-flop 308 controls the closed of described second switch 303 and holds with the CLKB of described first d type flip flop 316 to be connected, described first d type flip flop 316 is connected with the input of described OR circuit 318 respectively with the Q end of the second d type flip flop 317, the output of described OR circuit 318 is the output of described frequency control unit 206,
As shown in Figure 6, described frequency adjustment unit 205 comprises: N position up counter 401, N bit frequency reference cell 402, N bit digital comparator 403 and 3d flip-flop 404, second input of described frequency adjustment unit 205 is held with the CLKB of described N position up counter 401 and is connected, the first input end of described frequency adjustment unit 205 is connected with the input of described N bit frequency reference cell 402, the output of described N position up counter 401 is connected with the negative input end of described N bit digital comparator 403, the output of described N bit frequency reference cell 402 is connected with described N bit digital comparator 403 positive input terminal, the output of described N bit digital comparator 403 is held with the CLKB of described 3d flip-flop 404 and is connected, the QB end of described 3d flip-flop 404 is held with D and is connected, the Q end output signal 408 of described 3d flip-flop 404 is held with the reset terminal R of described N position up counter 401 and is connected after delay circuit 406 time delay, described output signal 408 clocking 410 after described 3rd reverser 405 is reverse is sent to the CLKB end of described N bit frequency reference cell 402, the output of described 3rd reverser 405 is the output of described frequency adjustment unit 205.
As shown in Figure 8, described N bit frequency reference cell 402 comprises: N position forward-backward counter 501, 4th inverter 507, upper limiting frequency base modules 502, lower frequency limit basic mode block 503 and OR circuit 504, the mode of operation of the input input of described N bit frequency reference cell 402 selects signal 319 to be sent to the input of described N position forward-backward counter 501, the CLKB end of described N position forward-backward counter 501 is the CLKB end of described N bit frequency reference cell 402, the output of described N position forward-backward counter 501 exports N bit frequency reference signal 506 as the output of described N bit frequency reference cell 402, the output of described N bit frequency reference cell 402 is also connected with the input of described upper limiting frequency base modules 502 and lower frequency limit base modules 503 respectively, the output signal of described upper limiting frequency base modules 502 and lower frequency limit base modules 503 produces reset signal 505 through described OR circuit 504 and is sent to described N position forward-backward counter 501, when described mode of operation selects signal 319 to be high level, upper limiting frequency base modules 502 described in gating, closes described lower frequency limit basic mode block 503, otherwise, when mode of operation selects signal 319 be low level, then close upper limiting frequency base modules 502 by the reverse backgating lower frequency limit base modules 503 of described 4th inverter 507.
In order to set forth the embodiment shown in above Fig. 2 further, be now described as follows in conjunction with the running of each accompanying drawing to circuit shown in Fig. 2:
As shown in Figure 2, during work: after described control driving chip 201 has powered on, described oscillator 203 is started working and is produced the square-like clock signal 214 of certain frequency, described clock signal 214 is transferred to described frequency adjustment unit 205, concrete, as shown in Figure 6, described clock signal 214 sends the CLKB end of described N position up counter 401 to, makes described N position up counter 401 carry out plus coujnt from 0.Time initial, the output of described N bit frequency reference cell 402 is a configurable initial value, conveniently state, be taken as representative value 111 without loss of generality in the present embodiment ... 1N position, when described N position up counter 401 exports equal with the initial value of described N bit frequency reference cell 402, it is low level that the output signal 407 of described N bit digital comparator 403 is overturn by high level, described output signal 407 is connected with the CLKB of described 3d flip-flop 404, the QB end of described 3d flip-flop 404 is held with D and is connected, described output signal 407 trailing edge makes the Q end signal 408 of described 3d flip-flop 404 become high level, the R end that described signal 408 is sent to described N position up counter 401 after the time delay of described delay circuit 406 makes described N position up counter 401 reset, counting is restarted from 0, make the output signal 407 of described N bit digital comparator 403 overturn as high level simultaneously, when counting reaches the benchmark of N bit frequency reference cell 402 again, described output signal 407 signal overturns as low level again, described signal 408 is made to overturn as high level, described signal 408 produces signal 410 after described 3rd reverser 405, described signal 410 gives described N bit frequency reference cell 402 as clock signal transmission, described signal 410 also to be held with the CLKB of described d type flip flop 207 as the output signal of described frequency adjustment unit 205 and is connected, the trailing edge of described signal 410 makes the Q of described d type flip flop 207 hold DRV signal 211 to overturn as high level, described DRV signal 211 drives described power tube 112 by described drive circuit 208 again, described power tube 112 is made to produce first time conducting.Described armature winding 108 electric current flows to ground by described power tube 112, current-limiting resistance 113, when described armature winding 108 electric current reaches peak current, it is low level that the OC signal 212 that described Current-Limiting Comparator 209 exports is overturn by high level, described OC signal 212 is connected with the reset terminal RB of described d type flip flop 207, described DRV signal 211 is resetted, and first time conducting terminates.After this second time conducting and even the principle of n-th conducting are consistent with first time conducting principle.The sequential chart that Continuity signal produces as shown in Figure 7.
After first time conducting produces, described demagnetization testing circuit 204 detects demagnetization time signal 312, as shown in Figure 3, in described frequency control unit 206, described demagnetization time signal 312 produces signal 314 with the output signal 410 of described frequency adjustment unit 205 after described AND circuit 313, described signal 314 is for controlling described first switch 302 conducting during high level, described first current source 301 charges to described electric capacity 306, the elapsed time
after be charged to a certain high level V1 and signal 315 is charged to a certain high level, V1 is lower than after internal power source voltage, described signal 315 will keep this high level, the signal 311 that described signal 315 obtains after described Schmidt trigger 305 processes with the first reverser 307 is held with the S of described rest-set flip-flop 308 and is connected, the R end of described rest-set flip-flop 308 is connected with the LEBB signal 310 of LEB signal 213 after oppositely, described signal 310 is initially high level, after described drive circuit 208 produces Continuity signal, the saltus step suddenly of described signal 310 is low level, making described rest-set flip-flop 308 output signal 309 by low level upset is high level, described second switch 303 is impelled to open, described electric capacity 306 is discharged by described second current source 304, the linear decline from high level V1 of described signal 315, in the present embodiment, the current ratio of described first current source 301 and the second current source 304 is configured to 1:1, when described signal 315 drops to the low transfer point of described Schmidt trigger 305, described signal 311 becomes low level, now described signal 310 has overturn as high level, described signal 309 can overturn as low level, stop electric discharge.When described signal 314 uprises again, described electric capacity 306 is charged again, and process is after this with consistent before.Because described in the present embodiment, the first current source 301 is configured to equal with the electric current of the second current source 304, therefore discharge time is equal with the charging interval, and namely described signal 309 keeps the time of high level to be
.
In addition, described signal 309 is also held with the CLKB of described first d type flip flop 316 and is connected, and as clock signal, the D end of described first d type flip flop 316 is connected with demagnetization time signal 312, when
time, namely
time, when the trailing edge of described signal 309 arrives, described signal 312 has been high level, exports high level, and signal 319 can be made to be high level, and described signal 319 goes to control described frequency adjustment unit 205 again and operating frequency is reduced.Otherwise, when
time, namely
time, described signal 319 meeting output low level controls described frequency adjustment unit 205 and operating frequency is increased.
Extra described second d type flip flop 317 can increase reliability: the CLKB end of described second d type flip flop 317 is connected with signal 410, and the D end of described second d type flip flop 317 is connected with described demagnetization time signal 312.When the trailing edge of described signal 410 arrives, if described demagnetization time signal 312 or high level, then show that drive circuit works is in CCM mode of operation, export high level, and make described signal 319 be high level by described OR circuit 318, described signal 319 goes to control described frequency adjustment unit 205 again and makes frequency reduce.The effect on this road prevents overlong time of demagnetizing, and cause charging saturated, described line voltage V1 reaches supply voltage.Charging interval
and discharge time
in fact be all less than
, now
, described first d type flip flop 316 exports 0, but
and be not less than
but described second d type flip flop 317 can export 1.When
time, described signal 319 is 1, and as shown in Figure 8, described signal 319 controls described N position forward-backward counter 501.When described signal 319 is 1, described signal 319 can control described N position forward-backward counter 501 and do plus coujnt, the stepping of N bit frequency reference signal 506 is increased, thus make described N position up counter 401 need the more clock cycle just can trigger described signal 407 step-down, namely make operating frequency reduce; When
time, described signal 319 is low level, described N position forward-backward counter 501 does subtraction count, described N bit frequency reference signal 506 can progressively reduce, thus make described N position up counter 401 will trigger described signal 407 step-down under the less clock cycle, namely make operating frequency increase.
In order to strengthen practicality of the present utility model, the described N bit frequency reference cell 402 in the utility model embodiment also comprises described upper limiting frequency base modules 502 and lower frequency limit basic mode block 503.When described signal 319 is 1, upper limiting frequency base modules 502 described in described signal 319 meeting gating, close described lower frequency limit basic mode block 503, when described reference frequency signal 506 reaches upper limit reference frequency, signal 505 saltus step is high level, makes described N position forward-backward counter 501 stop counting; Otherwise, when described signal 319 is 0, lower frequency limit base modules 503 described in so-called signal 319 meeting gating, described limit frequency reference module 502 is closed in pass, when described N bit frequency reference signal 506 reaches lower limit reference frequency, the saltus step of described signal 505 is low level, makes N position forward-backward counter 501 stop counting.
More than by description of listed embodiment, basic conception of the present utility model and general principle are set forth.But the utility model is never limited to above-mentioned listed execution mode, every equivalent variations, the improvement done based on the technical solution of the utility model and deliberately become of inferior quality behavior, all should belong to protection range of the present utility model.
Claims (3)
1. utilize the high precision constant current LED drive circuit that digital method realizes, it is characterized in that, this circuit comprises:
Control driving chip (201), described control driving chip (201) comprising: demagnetization testing circuit (204), the output of described demagnetization testing circuit (204) is connected with the first input end of frequency control unit (206), second input of described frequency control unit (206) is connected with the output of lead-edge-blanking circuit (210), 3rd input of described frequency control unit (206) is connected with the output of Current-Limiting Comparator (209), the output of described frequency control unit (206) is connected with the first input end of frequency adjustment unit (205), second input of described frequency adjustment unit (205) is connected with the output of oscillator (203), the output of described frequency adjustment unit (205) holds with the CLKB of d type flip flop (207) respectively and the four-input terminal of described frequency control unit (206) is connected, the D end of described d type flip flop (207) is connected with the output of internal electric source (202), the RB end of described d type flip flop (207) is connected with the output of described Current-Limiting Comparator (209), the Q end of described d type flip flop (207) is connected with the input of drive circuit (208), the output of described drive circuit (208) is connected with the input of described lead-edge-blanking circuit (210) and controls the closed of external power pipe (112), at the upper voltage formed of the current-limiting resistance (113) of series connection with it after power tube (112) conducting of the input detection outside of described Current-Limiting Comparator (209),
Described frequency control unit (206) comprising: the first current source (301), second current source (304), first switch (302), second switch (303), AND circuit (313), electric capacity (306), Schmidt trigger (305), first reverser (307), second reverser, rest-set flip-flop (308), first d type flip flop (316), second d type flip flop (317) and OR circuit (318), the first input end of described frequency control unit (206) respectively with an input and described first d type flip flop (316) of described AND circuit (313), the D end of the second d type flip flop (317) connects, the four-input terminal of described frequency control unit (206) is held with another input of described AND circuit (313) and the CLKB of the second d type flip flop (317) respectively and is connected, the output of described AND circuit (313) controls the closed of described first switch (302), one end, other two ends of described first switch (302) is connected with the output of described first current source (301), the other end is connected with the input of described Schmidt trigger (305) and passes through electric capacity (306) ground connection and be connected with the input of described second current source (304) by described second switch (303), the input of described first current source (301) is connected with the 3rd input of described frequency control unit (206), described second current source (304) output head grounding, the output of described Schmidt trigger (305) is held with the S of described rest-set flip-flop (308) by described first reverser (307) and is connected, second input of described frequency control unit (206) is held with the R of described rest-set flip-flop (308) by described second reverser and is connected, the Q end of described rest-set flip-flop (308) controls the closed of described second switch (303) and holds with the CLKB of described first d type flip flop (316) to be connected, described first d type flip flop (316) is connected with the input of described OR circuit (318) respectively with the Q end of the second d type flip flop (317), the output of described OR circuit (318) is the output of described frequency control unit (206),
Described frequency adjustment unit (205) comprising: N position up counter (401), N bit frequency reference cell (402), N bit digital comparator (403) and 3d flip-flop (404), second input of described frequency adjustment unit (205) is held with the CLKB of described N position up counter (401) and is connected, the first input end of described frequency adjustment unit (205) is connected with the input of described N bit frequency reference cell (402), the output of described N position up counter (401) is connected with the negative input end of described N bit digital comparator (403), the output of described N bit frequency reference cell (402) is connected with described N bit digital comparator (403) positive input terminal, the output of described N bit digital comparator (403) is held with the CLKB of described 3d flip-flop (404) and is connected, the QB end of described 3d flip-flop (404) is held with D and is connected, Q end output signal (408) of described 3d flip-flop (404) holds with the reset terminal R of described N position up counter (401) and is connected after delay circuit (406) time delay, described output signal (408) clocking (410) after the 3rd reverser (405) is reverse is sent to the CLKB end of described N bit frequency reference cell (402), the output of described 3rd reverser (405) is the output of described frequency adjustment unit (205),
Described N bit frequency reference cell (402) comprising: N position forward-backward counter (501), 4th inverter (507), upper limiting frequency base modules (502), lower frequency limit basic mode block (503) and OR circuit (504), the mode of operation of the input input of described N bit frequency reference cell (402) selects signal (319) to be sent to the input of described N position forward-backward counter (501), the CLKB end of described N position forward-backward counter (501) is the CLKB end of described N bit frequency reference cell (402), the output of described N position forward-backward counter (501) exports N bit frequency reference signal (506) as the output of described N bit frequency reference cell (402), the output of described N bit frequency reference cell (402) is also connected with the input of described upper limiting frequency base modules (502) and lower frequency limit base modules (503) respectively, the output signal of described upper limiting frequency base modules (502) and lower frequency limit base modules (503) produces reset signal (505) through described OR circuit (504) and is sent to described N position forward-backward counter (501), when described mode of operation selects signal (319) for high level, upper limiting frequency base modules (502) described in gating, closes described lower frequency limit basic mode block (503), otherwise, when mode of operation selects signal (319) for low level, then close upper limiting frequency base modules (502) by the reverse backgating lower frequency limit base modules (503) of described 4th inverter (507).
2. the high precision constant current LED drive circuit utilizing digital method to realize according to claim 1, it is characterized in that, this circuit also comprises following peripheral circuit: rectification circuit, described rectification circuit exports electrochemical capacitor (105) to, charging resistor (106) is in parallel with described electrochemical capacitor (105) after connecting with charging capacitor (107), described charging resistor (106) one end is successively by armature winding (108), described power tube (112), current-limiting resistance (113) ground connection, the other end of described charging resistor (106) by interior source current (202) for described control driving chip (201) is powered, the secondary winding be coupled with described armature winding (108) and fly-wheel diode (109) and output capacitance (110) form loop, external loading (111) is in parallel with described output capacitance (110).
3. the high precision constant current LED drive circuit utilizing digital method to realize according to claim 2, it is characterized in that, described rectification circuit is the bridge rectifier be made up of the first diode (101), the second diode (103), the 3rd diode (103) and the 4th diode (103).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520115256.7U CN204465968U (en) | 2015-02-25 | 2015-02-25 | The high precision constant current LED drive circuit utilizing digital method to realize |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520115256.7U CN204465968U (en) | 2015-02-25 | 2015-02-25 | The high precision constant current LED drive circuit utilizing digital method to realize |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204465968U true CN204465968U (en) | 2015-07-08 |
Family
ID=53672785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520115256.7U Withdrawn - After Issue CN204465968U (en) | 2015-02-25 | 2015-02-25 | The high precision constant current LED drive circuit utilizing digital method to realize |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204465968U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104640326A (en) * | 2015-02-25 | 2015-05-20 | 苏州智浦芯联电子科技有限公司 | High-accuracy constant-current LED (light emitting diode) driving circuit using digital method |
| CN105655985A (en) * | 2016-03-29 | 2016-06-08 | 昂宝电子（上海）有限公司 | Overvoltage protection system and method for LED lighting |
| CN106602846A (en) * | 2016-12-30 | 2017-04-26 | 陕西海泰电子有限责任公司 | Full-digital constant-voltage constant-current four-quadrant power supply |
| CN106714367A (en) * | 2016-11-16 | 2017-05-24 | 深圳市必易微电子有限公司 | Constant current circuit and constant current controller thereof |
-
2015
- 2015-02-25 CN CN201520115256.7U patent/CN204465968U/en not_active Withdrawn - After Issue
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104640326A (en) * | 2015-02-25 | 2015-05-20 | 苏州智浦芯联电子科技有限公司 | High-accuracy constant-current LED (light emitting diode) driving circuit using digital method |
| CN104640326B (en) * | 2015-02-25 | 2017-03-29 | 苏州智浦芯联电子科技股份有限公司 | The high precision constant current LED drive circuit realized using digital method |
| CN105655985A (en) * | 2016-03-29 | 2016-06-08 | 昂宝电子（上海）有限公司 | Overvoltage protection system and method for LED lighting |
| US10212783B2 (en) | 2016-03-29 | 2019-02-19 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods for overvoltage protection for LED lighting |
| US10243459B2 (en) | 2016-03-29 | 2019-03-26 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods of overvoltage protection for LED lighting |
| US10873263B2 (en) | 2016-03-29 | 2020-12-22 | On-Bright Electronics (Shanghai) Co., Ltd. | Systems and methods of overvoltage protection for LED lighting |
| CN106714367A (en) * | 2016-11-16 | 2017-05-24 | 深圳市必易微电子有限公司 | Constant current circuit and constant current controller thereof |
| CN106714367B (en) * | 2016-11-16 | 2018-11-09 | 深圳市必易微电子有限公司 | Constant-current circuit and its constant-current controller |
| CN106602846A (en) * | 2016-12-30 | 2017-04-26 | 陕西海泰电子有限责任公司 | Full-digital constant-voltage constant-current four-quadrant power supply |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204465968U (en) | The high precision constant current LED drive circuit utilizing digital method to realize | |
| CN104219840B (en) | LED switch color temperature regulation controller and LED drive circuit | |
| CN106129509B (en) | Integrated battery of charge-discharge controller | |
| CN104753146A (en) | Energy feed type variable-constant-current and positive-negative-pulse fast charging device and method | |
| CN105991034A (en) | Power conversion device with power-saving and high conversion efficiency mechanism | |
| CN104010421B (en) | Constant current output control device for LED drive circuit | |
| CN105226768A (en) | A kind of equalization methods of intelligent battery and intelligent battery | |
| CN103378636A (en) | Mobile power source control chip and mobile power source with same | |
| CN105356730A (en) | Error amplification device and driving circuit comprising same | |
| CN103401406A (en) | Ripple reducing circuit for light-load pulse hopping mode of DC-DC (Direct Current-Direct Current) converter | |
| CN109787482A (en) | Control chip and control method, constant pressure and flow device and isolation flyback PWM system | |
| CN103415120B (en) | Power source management driving chip and application circuit thereof | |
| CN104640326A (en) | High-accuracy constant-current LED (light emitting diode) driving circuit using digital method | |
| CN204090236U (en) | LED switch color-temperature regulating controller and LED drive circuit | |
| CN103889114B (en) | A kind of LED dimming driving circuit | |
| CN107147286A (en) | Current over-zero detection method, circuit and the control method of Switching Power Supply inductance | |
| CN103138356B (en) | The charging circuit of a kind of lighting and secondary cell thereof | |
| CN103269059B (en) | A kind of switching circuit improving overvoltage protection precision | |
| CN206948183U (en) | The current over-zero detection circuit of Switching Power Supply inductance | |
| CN104411035B (en) | A kind of LED drive circuit powered without assists winding | |
| CN203858288U (en) | Zero-cross detection circuit and power factor correction circuit | |
| CN203206529U (en) | A LED driving circuit sampling inductive current in a complete period | |
| CN105449996A (en) | Minimum demagnetization time control method and device | |
| CN201134763Y (en) | Off-line current type PWM power source control circuit | |
| CN202250550U (en) | Energy balance type charging igniting circuit of igniter of motorcycle |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Suzhou City, Jiangsu province 215000 Industrial Park Suzhou Xinping Street No. 388 Suzhou innovation park off the 23 building 3 layer 09, 10 unit Patentee after: SUZHOU INTELLI-CHIPLINK ELECTRONICS TECHNOLOGY CO., LTD. Address before: Suzhou City, Jiangsu province 215000 Industrial Park Suzhou Xinping Street No. 388 Suzhou innovation park off the 23 building 3 layer 09, 10 unit Patentee before: Suzhou Zhipu Xinlian Electronic Technology Co., Ltd. |
|
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20150708 Effective date of abandoning: 20170329 |