CN204465684U - A kind of four full HD recording and broadcasting systems in tunnel - Google Patents
A kind of four full HD recording and broadcasting systems in tunnel Download PDFInfo
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- CN204465684U CN204465684U CN201520063775.3U CN201520063775U CN204465684U CN 204465684 U CN204465684 U CN 204465684U CN 201520063775 U CN201520063775 U CN 201520063775U CN 204465684 U CN204465684 U CN 204465684U
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Abstract
The utility model discloses a kind of four full HD recording and broadcasting systems in tunnel, it comprises video and closes road module and core processor, described video closes road module and comprises fpga chip, serial FLASH chip, FPGA peripheral circuit and four road video interface circuits, and described video interface circuit comprises HDMI, USB interface, S-Video interface and video decoding chip; Described core processor comprises SOC, audio coding decoding chip, Ethernet chip, RS232 chip, output interface and NAND FLASH chip.The video interface type variation of the utility model recording and broadcasting system, can support the input of HDMI, USB interface, S-video interface, greatly can meet the demand of user like this, and can provide the commercial value of equipment self.The utility model can be widely used in video equipment field.
Description
Technical field
The utility model relates to recorded broadcast equipment, particularly relates to a kind of four full HD recording and broadcasting systems in tunnel.
Background technology
Explanation of nouns:
HDMI: HDMI (High Definition Multimedia Interface).
S-Video:S terminal exports.
VGA:Video Graphics Array, i.e. Video Graphics Array.
The abbreviation of SOC:System on Chip, is called systems-on-a-chip.
LINE IN interface: audio input interface.
LINE OUT interface: audio output interface.
SATA interface: Serial Advanced Technology Attachment, the abbreviation of serial ATA interface.
SD-CARD interface: safe digital card interface.
Bnc interface: bayonet nut connector, the one of Coaxial Cable joint.
DDR2: second generation double data rate Synchronous Dynamic Random Access Memory.
DDR3: third generation double data rate Synchronous Dynamic Random Access Memory.
At present, on major part market, full HD recorded broadcast equipment on sale is only provided with HDMI standard interface and carrys out receiving video signals, video interface type is single, therefore, if user needs to adopt USB interface and S-video interface to carry out receiving video signals when carrying out recorded broadcast, then need to buy other recorded broadcast equipment, so then greatly increase the cost of purchase of equipment, and purchase multiple stage recorded broadcast equipment also can take more placing space.
Utility model content
In order to solve the problems of the technologies described above, the purpose of this utility model is to provide a kind of four full HD recording and broadcasting systems in tunnel being provided with HDMI, USB interface and S-video interface.
The technical scheme that the utility model adopts is: a kind of four full HD recording and broadcasting systems in tunnel, and it comprises video and closes road module and core processor, and described video closes road module and comprises fpga chip, serial FLASH chip, FPGA peripheral circuit, first HDMI, first USB interface, one S-Video interface, second HDMI, second USB interface, 2nd S-Video interface, 3rd HDMI, 3rd USB interface, Three S's-Video interface, 4th HDMI, 4th USB interface, 4th S-Video interface, first video decoding chip, second video decoding chip, 3rd video decoding chip, 4th video decoding chip, described serial FLASH chip, FPGA peripheral circuit, first video decoding chip, second video decoding chip, 3rd video decoding chip and the 4th video decoding chip are all connected with fpga chip, described first HDMI, first USB interface and a S-Video interface are all connected with the first video decoding chip, described second HDMI, second USB interface and the 2nd S-Video interface are all connected with the second video decoding chip, described 3rd HDMI, 3rd USB interface and Three S's-Video interface are all connected with the 3rd video decoding chip, described 4th HDMI, 4th USB interface and the 4th S-Video interface are all connected with the 4th video decoding chip,
Described core processor comprises SOC, audio coding decoding chip, Ethernet chip, RS232 chip, output interface and NAND FLASH chip, described SOC is connected with fpga chip by parallel data bus line, described audio coding decoding chip, Ethernet chip, RS232 chip and NAND FLASH chip are all connected with SOC, and described audio coding decoding chip, Ethernet chip and RS232 chip are all connected with output interface.
Further, it also comprises ARM chip, and described ARM chip is connected with fpga chip, SOC, the first video decoding chip, the second video decoding chip, the 3rd video decoding chip and the 4th video decoding chip respectively.
Further, described output interface comprises microphone interface, LINE IN interface, LINE OUT interface, RS232 interface and Ethernet interface, described microphone interface, LINE IN interface and LINE OUT interface are all connected with audio coding decoding chip, described RS232 interface is connected with RS232 chip, and described Ethernet interface is connected with Ethernet chip.
Further, it also comprises interfacing expansion module, described interfacing expansion module comprises RS485 chip, RS485 interface, the 5th HDMI, SATA interface, SD-CARD interface, bnc interface, USB interface and reset key, described reset key is connected with ARM chip, described 5th HDMI, SATA interface, SD-CARD interface, bnc interface and USB interface are all connected with SOC, and described RS485 interface is by RS485 chip and then be connected with SOC.
Further, described fpga chip is also connected to a DDR2 chip, the 2nd DDR2 chip, the 3rd DDR2 chip and the 4th DDR2 chip.
Further, described SOC is also connected to a DDR3 chip, the 2nd DDR3 chip, the 3rd DDR3 chip and the 4th DDR3 chip.
Further, described first video decoding chip and the second video decoding chip are all arranged on the left side of fpga chip, described 3rd video decoding chip and the 4th video decoding chip are all arranged on the right side of fpga chip, a described DDR2 chip and the 2nd DDR2 chip are all arranged on the bottom side of fpga chip, and described 3rd DDR2 chip and the 4th DDR2 chip are all arranged on the top side of fpga chip.
Further, it also comprises the power module for powering for fpga chip and SOC.
Further, described power module comprises charging module, switch module, storage battery, current/voltage detection module and controller, the output of described charging module is by switch module and then be connected with the input of storage battery, described controller is connected with switch module, and described controller is by current/voltage detection module and then be connected with storage battery.
Further, described charging module is wireless charging module, described wireless charging module comprises electric energy receiving coil, the output of described electric energy receiving coil is connected with rectification circuit, filter circuit and signal amplification circuit in turn, and the output of described signal amplification circuit is by switch module and then be connected with the input of storage battery.
The beneficial effects of the utility model are: the video interface type variation of the utility model recording and broadcasting system, it is not only provided with HDMI, but also be provided with USB interface and S-Video interface, can obtain thus, recording and broadcasting system of the present utility model can not only support the input of the four full HD video HDMI in tunnel, also support USB interface and the input of S-Video interface simultaneously, so then greatly can meet the demand of user, without the need to buying multiple stage recorded broadcast equipment, thus the placing space of the purchase cost of the equipment of saving and the equipment of saving.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, embodiment of the present utility model is described further:
Fig. 1 is the structured flowchart of a kind of four full HD recording and broadcasting systems in tunnel of the utility model;
Fig. 2 is a specific embodiment structured flowchart of power module in a kind of four full HD recording and broadcasting systems in tunnel of the utility model;
Fig. 3 is a specific embodiment structured flowchart of charging module in a kind of four full HD recording and broadcasting systems in tunnel of the utility model;
Fig. 4 is the four direction schematic diagram of fpga chip.
Embodiment
As Figure 1-4, a kind of four full HD recording and broadcasting systems in tunnel, it comprises video and closes road module and core processor, and described video closes road module and comprises fpga chip, serial FLASH chip, FPGA peripheral circuit, first HDMI, first USB interface, one S-Video interface, second HDMI, second USB interface, 2nd S-Video interface, 3rd HDMI, 3rd USB interface, Three S's-Video interface, 4th HDMI, 4th USB interface, 4th S-Video interface, first video decoding chip, second video decoding chip, 3rd video decoding chip, 4th video decoding chip, described serial FLASH chip, FPGA peripheral circuit, first video decoding chip, second video decoding chip, 3rd video decoding chip and the 4th video decoding chip are all connected with fpga chip, described first HDMI, first USB interface and a S-Video interface are all connected with the first video decoding chip, described second HDMI, second USB interface and the 2nd S-Video interface are all connected with the second video decoding chip, described 3rd HDMI, 3rd USB interface and Three S's-Video interface are all connected with the 3rd video decoding chip, described 4th HDMI, 4th USB interface and the 4th S-Video interface are all connected with the 4th video decoding chip,
Described core processor comprises SOC, audio coding decoding chip, Ethernet chip, RS232 chip, output interface and NAND FLASH chip, described SOC is connected with fpga chip by parallel data bus line, described audio coding decoding chip, Ethernet chip, RS232 chip and NAND FLASH chip are all connected with SOC, and described audio coding decoding chip, Ethernet chip and RS232 chip are all connected with output interface.
For above-mentioned recording and broadcasting system, its course of work is: the vision signal utilizing HDMI, USB interface or S-Video interface to receive is sent to fpga chip, described fpga chip carries out image procossing to the four tunnel vision signals received, and synthesize a road frame of video to the frame of video of four tunnel vision signals, then fpga chip Jiang Gai mono-tunnel frame of video is transferred to SOC with the form identical with each road vision signal by parallel data bus line; Described SOC then comprises the Images uniting process of 7 kinds of forms such as single-image, picture-in-picture, picture out picture to the vision signal received.Can obtain thus, the utility model can support that the video interface of number of different types carrys out receiving video signals.
Be further used as preferred embodiment, it also comprises ARM chip, and described ARM chip is connected with fpga chip, SOC, the first video decoding chip, the second video decoding chip, the 3rd video decoding chip and the 4th video decoding chip respectively.Described ARM chip is mainly used in fpga chip and SOC are produced to reset signal and carry out parameter configuration to segment chip.
Be further used as preferred embodiment, described output interface comprises microphone interface, LINE IN interface, LINE OUT interface, RS232 interface and Ethernet interface, described microphone interface, LINE IN interface and LINE OUT interface are all connected with audio coding decoding chip, described RS232 interface is connected with RS232 chip, and described Ethernet interface is connected with Ethernet chip.
Be further used as preferred embodiment, it also comprises interfacing expansion module, described interfacing expansion module comprises RS485 chip, RS485 interface, the 5th HDMI, SATA interface, SD-CARD interface, bnc interface, USB interface and reset key, described reset key is connected with ARM chip, described 5th HDMI, SATA interface, SD-CARD interface, bnc interface and USB interface are all connected with SOC, and described RS485 interface is by RS485 chip and then be connected with SOC.
Be further used as preferred embodiment, described fpga chip is also connected to a DDR2 chip, the 2nd DDR2 chip, the 3rd DDR2 chip and the 4th DDR2 chip.
Be further used as preferred embodiment, described SOC is also connected to a DDR3 chip, the 2nd DDR3 chip, the 3rd DDR3 chip and the 4th DDR3 chip.
Preferably, described fpga chip employing model is that the chip of EP4CE40F23C8N realizes, described first video decoding chip, the second video decoding chip, the 3rd video decoding chip and the 4th video decoding chip all adopt the chip of ADV7441ABSTZ-170 to realize, and a described DDR2 chip, the 2nd DDR2 chip, the 3rd DDR2 chip and the 4th DDR2 chip all adopt model to be that the chip of MT47H32M16HR-25EL:G realizes;
Described SOC employing model is that the chip of TMS320DM8148BCYE1 realizes, described audio coding decoding chip employing model is that the chip of TLV320AIC3106IRGZT realizes, described Ethernet chip employing model is that the chip of AR8031-AL1A realizes, described NAND FLASH chip employing model is that the chip of MT29F2G16ABAEAWP:E realizes, described RS232 chip employing model is that the chip of MAX3232ESE realizes, a described DDR3 chip, 2nd DDR3 chip, 3rd DDR3 chip and the 4th DDR3 chip all adopt model to be that the chip of K4B2G1646Q-BCK0 realizes.
Be further used as preferred embodiment, it also comprises the power module for powering for fpga chip and SOC.
Be further used as preferred embodiment, as shown in Figure 2, described power module comprises charging module, switch module, storage battery, current/voltage detection module and controller, the output of described charging module is by switch module and then be connected with the input of storage battery, described controller is connected with switch module, and described controller is by current/voltage detection module and then be connected with storage battery.Described switch module can be relay, and described current/voltage detection module is for detecting the current/voltage of storage battery, and described controller is mainly used for the current/voltage according to the storage battery detected, thus controls relay.Described storage battery is that fpga chip and SOC are powered.
The operation principle of described power module is: the current/voltage of described current/voltage detection module to storage battery detects, thus obtain the current and voltage data of storage battery, then the current and voltage data of acquisition is sent to controller, described controller according to obtain current and voltage data thus judge that storage battery is the need of charging, when judged result is for needs, then output voltage signal makes relay closes, thus making electric connection between charging module and storage battery, such charging module then can charge for storage battery; When judged result is not for needing, then not output voltage signal, such relay just can be in the state of disconnection, does not then realize electric connection between such charging module and storage battery.And for the judgement of above-mentioned controller and control, it can adopt prior art to realize, and does not therefore elaborate herein.
Be further used as preferred embodiment, as shown in Figure 3, described charging module is wireless charging module, described wireless charging module comprises electric energy receiving coil, the output of described electric energy receiving coil is connected with rectification circuit, filter circuit and signal amplification circuit in turn, and the output of described signal amplification circuit is by switch module and then be connected with the input of storage battery.Adopt the mode of wireless charging to come for charge in batteries, can break like this as storage battery carries out the position limitation that charges, the operation for user brings great convenience.
Be further used as preferred embodiment, described first video decoding chip and the second video decoding chip are all arranged on the left side of fpga chip, described 3rd video decoding chip and the 4th video decoding chip are all arranged on the right side of fpga chip, a described DDR2 chip and the 2nd DDR2 chip are all arranged on the bottom side of fpga chip, and described 3rd DDR2 chip and the 4th DDR2 chip are all arranged on the top side of fpga chip.And for the direction of fpga chip, it as shown in Figure 4.
Obtained by above-mentioned, compared with prior art, the recording and broadcasting system of this practicality has the diversified advantage of video interface type, its HDMI video input that four tunnels not only can be supported full HD, and support four tunnel USB interface and the input of S-Video interface, great convenience can not only be brought for the operation of user like this, and cost, placing space can also be saved, and the commercial value of recorded broadcast equipment can also be improved widely.
Finally it should be noted that, the utility model only relates to structural improvement, do not relate to the improvement on software approach, although the content that the fpga chip in the utility model, SOC, ARM chip and controller relate to process and control, but it can adopt prior art means to realize, in data processing method, there is not any improvement, therefore, the utility model does not relate to the improvement in the methods such as data processing, does not namely relate to the improvement on any software.
More than that better enforcement of the present utility model is illustrated, but the utility model is created and is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to the utility model spirit, and these equivalent distortion or replacement are all included in the application's claim limited range.
Claims (10)
1. the four full HD recording and broadcasting systems in tunnel, is characterized in that: it comprises video and closes road module and core processor, and described video closes road module and comprises fpga chip, serial FLASH chip, FPGA peripheral circuit, first HDMI, first USB interface, one S-Video interface, second HDMI, second USB interface, 2nd S-Video interface, 3rd HDMI, 3rd USB interface, Three S's-Video interface, 4th HDMI, 4th USB interface, 4th S-Video interface, first video decoding chip, second video decoding chip, 3rd video decoding chip, 4th video decoding chip, described serial FLASH chip, FPGA peripheral circuit, first video decoding chip, second video decoding chip, 3rd video decoding chip and the 4th video decoding chip are all connected with fpga chip, described first HDMI, first USB interface and a S-Video interface are all connected with the first video decoding chip, described second HDMI, second USB interface and the 2nd S-Video interface are all connected with the second video decoding chip, described 3rd HDMI, 3rd USB interface and Three S's-Video interface are all connected with the 3rd video decoding chip, described 4th HDMI, 4th USB interface and the 4th S-Video interface are all connected with the 4th video decoding chip,
Described core processor comprises SOC, audio coding decoding chip, Ethernet chip, RS232 chip, output interface and NAND FLASH chip, described SOC is connected with fpga chip by parallel data bus line, described audio coding decoding chip, Ethernet chip, RS232 chip and NAND FLASH chip are all connected with SOC, and described audio coding decoding chip, Ethernet chip and RS232 chip are all connected with output interface.
2. a kind of four full HD recording and broadcasting systems in tunnel according to claim 1, it is characterized in that: it also comprises ARM chip, described ARM chip is connected with fpga chip, SOC, the first video decoding chip, the second video decoding chip, the 3rd video decoding chip and the 4th video decoding chip respectively.
3. a kind of four full HD recording and broadcasting systems in tunnel according to claim 2, it is characterized in that: described output interface comprises microphone interface, LINE IN interface, LINE OUT interface, RS232 interface and Ethernet interface, described microphone interface, LINE IN interface and LINE OUT interface are all connected with audio coding decoding chip, described RS232 interface is connected with RS232 chip, and described Ethernet interface is connected with Ethernet chip.
4. a kind of four full HD recording and broadcasting systems in tunnel according to claim 3, it is characterized in that: it also comprises interfacing expansion module, described interfacing expansion module comprises RS485 chip, RS485 interface, the 5th HDMI, SATA interface, SD-CARD interface, bnc interface, USB interface and reset key, described reset key is connected with ARM chip, described 5th HDMI, SATA interface, SD-CARD interface, bnc interface and USB interface are all connected with SOC, and described RS485 interface is by RS485 chip and then be connected with SOC.
5. a kind of four full HD recording and broadcasting systems in tunnel according to claim 4, is characterized in that: described fpga chip is also connected to a DDR2 chip, the 2nd DDR2 chip, the 3rd DDR2 chip and the 4th DDR2 chip.
6. a kind of four full HD recording and broadcasting systems in tunnel according to claim 5, is characterized in that: described SOC is also connected to a DDR3 chip, the 2nd DDR3 chip, the 3rd DDR3 chip and the 4th DDR3 chip.
7. a kind of four full HD recording and broadcasting systems in tunnel according to claim 6, it is characterized in that: described first video decoding chip and the second video decoding chip are all arranged on the left side of fpga chip, described 3rd video decoding chip and the 4th video decoding chip are all arranged on the right side of fpga chip, a described DDR2 chip and the 2nd DDR2 chip are all arranged on the bottom side of fpga chip, and described 3rd DDR2 chip and the 4th DDR2 chip are all arranged on the top side of fpga chip.
8. a kind of four full HD recording and broadcasting systems in tunnel according to claim 1, is characterized in that: it also comprises the power module for powering for fpga chip and SOC.
9. a kind of four full HD recording and broadcasting systems in tunnel according to claim 8, it is characterized in that: described power module comprises charging module, switch module, storage battery, current/voltage detection module and controller, the output of described charging module is by switch module and then be connected with the input of storage battery, described controller is connected with switch module, and described controller is by current/voltage detection module and then be connected with storage battery.
10. a kind of four full HD recording and broadcasting systems in tunnel according to claim 9, it is characterized in that: described charging module is wireless charging module, described wireless charging module comprises electric energy receiving coil, the output of described electric energy receiving coil is connected with rectification circuit, filter circuit and signal amplification circuit in turn, and the output of described signal amplification circuit is by switch module and then be connected with the input of storage battery.
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| CN201520063775.3U CN204465684U (en) | 2015-01-29 | 2015-01-29 | A kind of four full HD recording and broadcasting systems in tunnel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110312158A (en) * | 2018-03-27 | 2019-10-08 | 北京市博汇科技股份有限公司 | A kind of monitoring method and device of embedded more pictures |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110312158A (en) * | 2018-03-27 | 2019-10-08 | 北京市博汇科技股份有限公司 | A kind of monitoring method and device of embedded more pictures |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Four-path full high-definition recording and broadcasting system Effective date of registration: 20190422 Granted publication date: 20150708 Pledgee: Guangzhou Bank Co., Ltd. East Branch of Huanshi City Pledgor: Guang Zhou Hai Noboru computer Science and Technology Ltd. Registration number: 2019440000160 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20200506 Granted publication date: 20150708 Pledgee: Guangzhou Bank Co., Ltd. East Branch of Huanshi City Pledgor: GUANGZHOU HISON COMPUTER TECHNOLOGY Co.,Ltd. Registration number: 2019440000160 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Four-path full high-definition recording and broadcasting system Effective date of registration: 20200512 Granted publication date: 20150708 Pledgee: Guangzhou Bank Co., Ltd. East Branch of Huanshi City Pledgor: GUANGZHOU HISON COMPUTER TECHNOLOGY Co.,Ltd. Registration number: Y2020440000109 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20210610 Granted publication date: 20150708 Pledgee: Guangzhou Bank Co.,Ltd. East Branch of Huanshi City Pledgor: GUANGZHOU HISON COMPUTER TECHNOLOGY Co.,Ltd. Registration number: Y2020440000109 |