CN204423040U - A kind of dynamic controller - Google Patents
A kind of dynamic controller Download PDFInfo
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- CN204423040U CN204423040U CN201520045497.9U CN201520045497U CN204423040U CN 204423040 U CN204423040 U CN 204423040U CN 201520045497 U CN201520045497 U CN 201520045497U CN 204423040 U CN204423040 U CN 204423040U
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Abstract
The utility model relates to a kind of dynamic controller, is applied to dynamic electro-hydraulic servo static/dynamic universal testing machine, to realize the every experiment work of electro-hydraulic servo static/dynamic universal testing machine complete independently.A kind of dynamic controller, comprise board, the FPGA programmable gate array that described board is provided with DSP micro treatment module, eeprom memory, some signaling interfaces and is connected with described DSP micro treatment module, described DSP micro treatment module comprises spi bus bridge, an I/O interface, quadrature decoder interface and I
2c interface, described spi bus bridge, a described I/O interface are connected with described some signaling interfaces respectively with described quadrature decoder interface, described I
2c interface is connected with described eeprom memory, and described FPGA programmable gate array comprises the 2nd I/O interface be connected with described some signaling interfaces.
Description
Technical field
The utility model relates to a kind of dynamic controller, is applied to dynamic electro-hydraulic servo static/dynamic universal testing machine.
Background technology
Electro-hydraulic servo static/dynamic universal testing machine comprises dynamic electro-hydraulic servo static/dynamic universal testing machine, and dynamic electro-hydraulic servo static/dynamic universal testing machine can carry out low cycle fatigue test, programmed control torture test; Electro-hydraulic servo static/dynamic universal testing machine also comprises static electro-hydraulic servo static/dynamic universal testing machine, and static electro-hydraulic servo static/dynamic universal testing machine can carry out the mechanical property test of experiment under constant speed, constant strain, constant stress controlled and various routine.Electro-hydraulic servo static/dynamic universal testing machine is material property testing equipment best in the world at present, can be widely used in the fields such as space flight, aviation, boat, vehicle, military project, engineering machinery.
Common electro-hydraulic servo static/dynamic universal testing machine comprises box controller and card insert type controller (card insert type controller being provided with pci bus bridge or PCIE bus bridge), electro-hydraulic servo static/dynamic universal testing machine need connect computing machine just can complete every experiment work, but, at the severe industry spot of complexity (such as hot environment, hyperbaric environment, low temperature environment and environment under low pressure one of them), external computer cannot normally work.
Summary of the invention
Problem to be solved in the utility model is just to provide a kind of dynamic controller, to realize the every experiment work of electro-hydraulic servo static/dynamic universal testing machine complete independently.
For solving the problem, the utility model provides following technical scheme: a kind of dynamic controller, comprise board, the FPGA programmable gate array that described board is provided with DSP micro treatment module, eeprom memory, some signaling interfaces and is connected with described DSP micro treatment module, described DSP micro treatment module comprises spi bus bridge, an I/O interface, quadrature decoder interface and I
2c interface, described spi bus bridge, a described I/O interface are connected with described some signaling interfaces respectively with described quadrature decoder interface, described I
2c interface is connected with described eeprom memory, and described FPGA programmable gate array comprises the 2nd I/O interface be connected with described some signaling interfaces.
Further, described some signaling interfaces comprise for Input Forces simulating signal the first signaling interface, for input deformation simulative signal secondary signal interface, for inputting the 3rd signaling interface of shift simulation signal and the 4th signaling interface for power output, distortion, shift simulation signal, described first signaling interface, described secondary signal interface, described 3rd signaling interface and described 4th signaling interface and described spi bus bridging connect.
Further, described quadrature decoder interface, a described I/O interface, described 2nd I/O interface are connected with described 4th signaling interface respectively.
Further, be connected by D/A change-over circuit between described 2nd I/O interface with described 4th signaling interface.
Further, described first signaling interface, described secondary signal interface and described 3rd signaling interface are connected by respective independently A/D change-over circuit with described spi bus bridge respectively.
Further, RAM is provided with between described FPGA programmable gate array and described DSP micro treatment module.
Further, ARM microprocessor is connected with between described RAM and described FPGA programmable gate array.
Further, described board is also provided with the CAN bridge be connected with described ARM microprocessor.
Further, described board is also provided with the man-machine interface be connected with described ARM microprocessor.
Further, described board is also provided be connected with described DSP micro treatment module extend out RAM storer.
The beneficial effects of the utility model:
The board of the utility model dynamic controller comprises DSP micro treatment module, FPGA programmable gate array, eeprom memory and some signaling interfaces, (electric signal comprises power simulating signal to electric signal, deformation simulative signal, shift simulation signal, DI signal, orthogonal intersection code signal, wherein, power simulating signal, after deformation simulative signal and shift simulation signal demand are converted to AD signal by A/D change-over circuit, just can be transferred to DSP micro treatment module, DI signal and orthogonal intersection code signal are digital signal, can directly be transferred to DSP micro treatment module) be transferred to DSP micro treatment module by some signaling interfaces, the electric signal that the analysis of DSP micro treatment module receives and generate corresponding control command (control command comprises DA signal, DO signal), by the DA signal of generation, (DA signal is converted to power simulating signal by D/A change-over circuit to DSP micro treatment module, deformation simulative signal and shift simulation signal) be transferred to electro-hydraulic servo static/dynamic universal testing machine by some signaling interfaces, DSP micro treatment module by generate DO Signal transmissions to FPGA programmable gate array, DO signal is transferred to electro-hydraulic servo static/dynamic universal testing machine by some signaling interfaces by FPGA programmable gate array, electro-hydraulic servo static/dynamic universal testing machine is according to the power simulating signal received, deformation simulative signal, shift simulation signal and DO signal, to have realized every experiment work.This just means, dynamic controller replaces external microcomputer (i.e. microcomputer, certainly, except microcomputer also can be also mainframe computer), the carrying out of the every experiment work of automatic control electric liquid servo static/dynamic universal testing machine.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of a kind of dynamic controller in the utility model.
Embodiment
With reference to Fig. 1, a kind of dynamic controller, comprise board 1, some signaling interfaces that board 1 comprises DSP micro treatment module 2, FPGA programmable gate array 3, eeprom memory 4 and is connected with electro-hydraulic servo static/dynamic universal testing machine, FPGA programmable gate array 3, eeprom memory 4 are connected with DSP micro treatment module 2 respectively with some signaling interfaces, FPGA programmable gate array 3, except being connected with DSP micro treatment module 2, is also connected with some signaling interfaces.
With reference to Fig. 1, some signaling interfaces comprise for Input Forces simulating signal the first signaling interface 10, for input deformation simulative signal secondary signal interface 20, for inputting the 3rd signaling interface 30 of shift simulation signal and the 4th signaling interface 40 for power output, distortion, shift simulation signal.Wherein, an A/D change-over circuit 101 is connected with between first signaling interface 10 and DSP micro treatment module 2, the power simulating signal at the first signaling interface 10 place is converted to after AD signal (digital signal) through an A/D change-over circuit 101, is transferred to DSP micro treatment module 2; The 2nd A/D change-over circuit 201 is connected with between secondary signal interface 20 and DSP micro treatment module 2, the deformation simulative signal at secondary signal interface 20 place is converted to after AD signal (digital signal) through the 2nd A/D change-over circuit 201, is transferred to DSP micro treatment module 2; The 3rd A/D change-over circuit 301 is connected with between 3rd signaling interface 30 and DSP micro treatment module 2, the shift simulation signal at the 3rd signaling interface 30 place is converted to after AD signal (digital signal) through the 3rd A/D change-over circuit 301, is transferred to DSP micro treatment module 2; D/A change-over circuit 401 is connected with between 4th signaling interface 40 and DSP micro treatment module 2, the DA signal (digital signal) that DSP micro treatment module 2 generates is converted to after power, distortion, shift simulation signal through D/A change-over circuit 401, is transferred to the 4th signaling interface 40.4th signaling interface 40 is also connected with FPGA programmable gate array 3, and the DO signal that DSP micro treatment module 2 generates is transferred to the 4th signaling interface 40 by FPGA programmable gate array 3.
Spi bus bridge 21, an I/O interface 22, quadrature decoder interface 23 and I is comprised with reference to Fig. 1, DSP micro treatment module 2
2c interface 24, one A/D change-over circuit 101, the 2nd A/D change-over circuit 201, the 3rd A/D change-over circuit 301 are connected with DSP micro treatment module 2 respectively by spi bus bridge 21 with D/A change-over circuit 401, to realize electrical signal transfer between electro-hydraulic servo static/dynamic universal testing machine and DSP micro treatment module 2 (simulating signal namely on electro-hydraulic servo static/dynamic universal testing machine passes to electro-hydraulic servo static/dynamic universal testing machine after the digital signal passed on DSP micro treatment module 2, DSP micro treatment module 2 is converted to simulating signal after being converted to digital signal).One I/O interface 22 is connected with the 4th signaling interface 40, and the DI signal at the 4th signaling interface place is directly passed to DSP micro treatment module 2 by an I/O interface 22.Quadrature decoder interface 23 is connected with the 4th signaling interface 40, and the orthogonal intersection code signal at the 4th signaling interface place is directly passed to DSP micro treatment module 2 by quadrature decoder interface 23.Associated control parameters in eeprom memory 4 is by I
2c interface 24 is transferred to DSP micro treatment module 2.
Comprise with reference to Fig. 1, FPGA programmable gate array 3 the DO signal that the 2nd I/O interface 31, the DSP micro treatment module 2 that is connected with the 4th signaling interface 40 generates and be transferred to the 4th signaling interface 40 by FPGA programmable gate array 3.
With reference to Fig. 1, the course of work of the present embodiment comprises:
1, after electro-hydraulic servo static/dynamic universal testing machine runs, DSP micro treatment module 2 obtains the associated control parameters in eeprom memory 4;
2, DSP micro treatment module 2 gathers electro-hydraulic servo static/dynamic universal testing machine generative power simulating signal, deformation simulative signal, shift simulation signal, DI signal and orthogonal intersection code signal;
3, DSP micro treatment module 2 generates corresponding DA signal and DO signal according to the electric signal collected, and by DA signal and DO Signal transmissions to electro-hydraulic servo static/dynamic universal testing machine, completes every experiment work to realize electro-hydraulic servo static/dynamic universal testing machine.
With reference to Fig. 1, in the present embodiment, board 1 is also provided be connected with DSP micro treatment module 2 extend out RAM storer 7, before the associated control parameters that DSP micro treatment module 2 obtains in eeprom memory 4, internal processes first can copy to and extend out in RAM storer 7 by DSP micro treatment module 2.
With reference to Fig. 1, the dynamic controller of this enforcement can also be connected with microcomputer, every experiment work is completed to realize electro-hydraulic servo static/dynamic universal testing machine, namely in the present embodiment, board 1 is also provided with RAM 5, ARM microprocessor 6, CAN bridge 8 and man-machine interface 9, wherein, RAM 5 is connected with DSP micro treatment module 2, to store corresponding data (described data comprise power simulating signal, deformation simulative signal, shift simulation signal, DI signal and orthogonal intersection code signal) on DSP micro treatment module 2; RAM 5, CAN bridge 8 are connected with ARM microprocessor 6 respectively with man-machine interface 9, after ARM microprocessor 6 reads the interior corresponding data of RAM 5, be transferred to microcomputer by CAN bridge 8, also can be transferred to microcomputer by man-machine interface 9.RAM 5 is connected with FPGA programmable gate array 3 respectively with ARM microprocessor 6, at microcomputer, steering order is transferred to ARM microprocessor 6, ARM microprocessor 6 passes through RAM 5 by DA signal transmission to DSP micro treatment module 2, meanwhile, ARM microprocessor 6 by RAM 5 by DO signal transmission to FPGA programmable gate array 3 (DO signal also can be directly passed to FPGA programmable gate array 3 by ARM microprocessor 6), complete every experiment work to realize electro-hydraulic servo static/dynamic universal testing machine.
In the present embodiment, CAN bridge can form multimachine LAN backbone, namely a microcomputer is by keeping real-time communication with multiple CAN bridge, complete every experiment work (different electro-hydraulic servo static/dynamic universal testing machines can complete identical experiment work, also can complete different experiment works) to realize multiple stage electro-hydraulic servo static/dynamic universal testing machine simultaneously.
In the present embodiment, man-machine interface is knob and liquid crystal display.
The above, be only embodiment of the present utility model, but protection domain of the present utility model is not limited thereto, and those of ordinary skill in the art should be understood that the content that the utility model includes but not limited to accompanying drawing and describes in embodiment above.Any amendment not departing from function and structure principle of the present utility model all will comprise within the scope of the appended claims.
Claims (10)
1. a dynamic controller, it is characterized in that: comprise board, the FPGA programmable gate array that described board is provided with DSP micro treatment module, eeprom memory, some signaling interfaces and is connected with described DSP micro treatment module, described DSP micro treatment module comprises spi bus bridge, an I/O interface, quadrature decoder interface and I
2c interface, described spi bus bridge, a described I/O interface are connected with described some signaling interfaces respectively with described quadrature decoder interface, described I
2c interface is connected with described eeprom memory, and described FPGA programmable gate array comprises the 2nd I/O interface be connected with described some signaling interfaces.
2. a kind of dynamic controller as claimed in claim 1, it is characterized in that: described some signaling interfaces comprise for Input Forces simulating signal the first signaling interface, for input deformation simulative signal secondary signal interface, for inputting the 3rd signaling interface of shift simulation signal and the 4th signaling interface for power output, distortion, shift simulation signal, described first signaling interface, described secondary signal interface, described 3rd signaling interface and described 4th signaling interface and described spi bus bridging connect.
3. a kind of dynamic controller as claimed in claim 2, is characterized in that: described quadrature decoder interface, a described I/O interface, described 2nd I/O interface are connected with described 4th signaling interface respectively.
4. a kind of dynamic controller as claimed in claim 3, is characterized in that: be connected by D/A change-over circuit between described 2nd I/O interface with described 4th signaling interface.
5. a kind of dynamic controller as claimed in claim 2, is characterized in that: described first signaling interface, described secondary signal interface and described 3rd signaling interface are connected by respective independently A/D change-over circuit with described spi bus bridge respectively.
6. a kind of dynamic controller as described in one of claim 1 to 5, is characterized in that: be provided with RAM between described FPGA programmable gate array and described DSP micro treatment module.
7. a kind of dynamic controller as claimed in claim 6, is characterized in that: be connected with ARM microprocessor between described RAM and described FPGA programmable gate array.
8. a kind of dynamic controller as claimed in claim 7, is characterized in that: described board is also provided with the CAN bridge be connected with described ARM microprocessor.
9. a kind of dynamic controller as claimed in claim 7, is characterized in that: described board is also provided with the man-machine interface be connected with described ARM microprocessor.
10. a kind of dynamic controller as described in one of claim 1 to 5, is characterized in that: described board is also provided be connected with described DSP micro treatment module extend out RAM storer.
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| CN201520045497.9U CN204423040U (en) | 2015-01-22 | 2015-01-22 | A kind of dynamic controller |
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| CN201520045497.9U CN204423040U (en) | 2015-01-22 | 2015-01-22 | A kind of dynamic controller |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106406196A (en) * | 2016-12-21 | 2017-02-15 | 北京市佛力系统公司 | Modularized electro-hydraulic servo structure test control system |
| CN109164739A (en) * | 2018-09-07 | 2019-01-08 | 天津福云天翼科技有限公司 | A kind of electrohydraulic servo-controlling system |
| CN112147918A (en) * | 2019-06-26 | 2020-12-29 | 中车株洲电力机车研究所有限公司 | Asynchronous data interaction method and system based on ARM + FPGA + DSP architecture |
-
2015
- 2015-01-22 CN CN201520045497.9U patent/CN204423040U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106406196A (en) * | 2016-12-21 | 2017-02-15 | 北京市佛力系统公司 | Modularized electro-hydraulic servo structure test control system |
| CN109164739A (en) * | 2018-09-07 | 2019-01-08 | 天津福云天翼科技有限公司 | A kind of electrohydraulic servo-controlling system |
| CN109164739B (en) * | 2018-09-07 | 2023-10-24 | 天津福云天翼科技有限公司 | Electrohydraulic servo control system |
| CN112147918A (en) * | 2019-06-26 | 2020-12-29 | 中车株洲电力机车研究所有限公司 | Asynchronous data interaction method and system based on ARM + FPGA + DSP architecture |
| CN112147918B (en) * | 2019-06-26 | 2022-02-11 | 中车株洲电力机车研究所有限公司 | Asynchronous data interaction method and system based on ARM + FPGA + DSP architecture |
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