CN204405771U - The test macro of feed line automatization system - Google Patents

The test macro of feed line automatization system Download PDF

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Publication number
CN204405771U
CN204405771U CN201520138789.7U CN201520138789U CN204405771U CN 204405771 U CN204405771 U CN 204405771U CN 201520138789 U CN201520138789 U CN 201520138789U CN 204405771 U CN204405771 U CN 204405771U
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CN
China
Prior art keywords
signal
bus controller
submodule
connecting line
kind connecting
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Expired - Fee Related
Application number
CN201520138789.7U
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Chinese (zh)
Inventor
范志杰
张磐
吴攀
王蔚
凌万水
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SHANGHAI WISCOM SUNEST ELECTRIC POWER TECHNOLOGY Co Ltd
State Grid Corp of China SGCC
State Grid Tianjin Electric Power Co Ltd
Original Assignee
SHANGHAI WISCOM SUNEST ELECTRIC POWER TECHNOLOGY Co Ltd
State Grid Corp of China SGCC
State Grid Tianjin Electric Power Co Ltd
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Priority to CN201520138789.7U priority Critical patent/CN204405771U/en
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Abstract

The utility model provides a kind of test macro of feed line automatization system, comprises some submodules and bus controller; Realized the transmission of communication signal by first kind connecting line between described bus controller and each described submodule; Realized the transmission of control signal by Equations of The Second Kind connecting line between described bus controller and each described submodule; Each described submodule all at least in order to: respond the communication signal come through the transmission of described first kind connecting line, generate according to this communication signal and to export in ac current signal that a drive test tries out and the ac voltage signal that a drive test is tried out one of at least; Respond the control signal come through described Equations of The Second Kind connecting line transmission, carry out operating and feedback of status according to this control signal.

Description

The test macro of feed line automatization system
Technical field
The utility model relates to field of feeder automation, particularly relates to a kind of test macro of feed line automatization system.
Background technology
In electric system, various places Utilities Electric Co. all generally adopts the system having FA (Feeder Automation), i.e. feed line automatization system.When certain point breaks down in distribution network, same power supply area can be caused to have a power failure, when situation is serious, can large-area power-cuts be caused.At this moment FA system will excise fault zone as early as possible, restores electricity then to non-faulting region.
FA system all will carry out various functional test to it before reality drops into application, and testing apparatus requires independently to export 8 channel AC current signals and 8 channel AC voltage signals.Require the amplitude of these signals, phase place independently to control and with main MCU electrical isolation.The concrete signal of isolation that needs has: voltage, current output signal, voltage, electric current back production signal, output relay control signal, range control signal etc.
Realize the isolation of so multi signal, more difficult.So multichannel signal operation is placed on a MCU and performs simultaneously, and burden seems too heavy.
Utility model content
The technical problems to be solved in the utility model is the isolation how realizing multi signal, and alleviates the burden of a MCU.
In order to solve this technical matters, the utility model provides a kind of test macro of feed line automatization system, comprises some submodules and bus controller;
Realized the transmission of communication signal by first kind connecting line between described bus controller and each described submodule;
Realized the transmission of control signal by Equations of The Second Kind connecting line between described bus controller and each described submodule;
Each described submodule all at least in order to:
Respond the communication signal come through the transmission of described first kind connecting line, generate according to this communication signal and to export in ac current signal that a drive test tries out and the ac voltage signal that a drive test is tried out one of at least;
Respond the control signal come through described Equations of The Second Kind connecting line transmission, carry out operating and feedback of status according to this control signal.
Optionally, each described submodule is all further in order to generate according to the waveform character value comprised in described signal of communication and to export in described ac current signal and ac voltage signal one of at least.
Optionally, described first kind connecting line comprises RS485 bidirectional serial data lines, and the RS485 communication port of all described submodules is all connected to the RS485 communication port of described bus controller by described RS485 bidirectional serial data lines;
Each described submodule all further in order to:
By the RS485 differential signal that the response of described RS485 communication port comes through described RS485 bidirectional serial data lines transmission, generate according to the waveform character value comprised in this RS485 differential signal and export described ac current signal and ac voltage signal one of at least.
Optionally, described Equations of The Second Kind connecting line comprises signal lines, each CK port of described bus controller is connected with a described submodule respectively by a described signal lines, described bus controller also in order to the detection signal that response comes through described signal lines transmission, judges whether connexon module.
Optionally, described Equations of The Second Kind connecting line comprises look-at-me line, and each INT port of described bus controller is connected with a described submodule respectively by a described look-at-me line,
Described submodule also in order to when an exception occurs, feeds back a look-at-me by described look-at-me line
Described bus controller also in order to the look-at-me that response comes through described look-at-me line transmission, exports corresponding action control signal according to the rule preset.
Optionally, described Equations of The Second Kind connecting line comprises reset signal line, the CLR port of described bus controller is connected with some described submodules respectively by some described reset signal lines, described submodule also in order to the reset signal that response comes through described reset signal line transmission, makes described ac current signal and ac voltage signal zero.
Optionally, described Equations of The Second Kind connecting line comprises reseting signal line, the RST port of described bus controller is connected with some described submodules respectively by some described reseting signal lines, and described submodule also in order to the reset signal that response comes through described reseting signal line transmission, resets.
Optionally, described Equations of The Second Kind connecting line comprises chip selection signal line and commencing signal line, each CS port of described bus controller is connected with a described submodule respectively by a described chip selection signal line, and the STA port of described bus controller is connected with some described submodules respectively by some described commencing signal lines;
Described submodule also in order to the specific chip selection signal that response comes through described chip selection signal line transmission, is defined as selected submodule, and then:
The commencing signal that selected submodule response comes through described commencing signal line transmission, activates running, thus generates and export described ac current signal and ac voltage signal.
Optionally, described Equations of The Second Kind connecting line comprises clock cable, the CLK interface of described bus controller is connected with some described submodules respectively by some described clock cables, and described bus controller is in order to be sent to each described submodule by described clock cable respectively by same clock signal.
The utility model by the workload allocations of a MCU to multiple submodule, each submodule can configure a MCU, waveform computing can be gone, range has switched, export the inter-related tasks such as control, signal back production, closed-loop control, each submodule all can be generated and to export in ac current signal that a drive test tries out and the ac voltage signal that a drive test is tried out one of at least, so just realize the isolation of multi signal, and alleviate the burden of a MCU.But during multimode co-operation, the deficiency of its serial communication also can bring problem, for this reason, the utility model further increases control signal, finally, adopt the method for serial communication+control signal, effective address signal isolating problem and core MCU bear heavier problem.
Accompanying drawing explanation
Fig. 1 is the system architecture schematic diagram of the test macro of feed line automatization system in the utility model one embodiment;
Fig. 2 is the bus signals figure of the test macro of feed line automatization system in the utility model one embodiment.
Embodiment
Below with reference to Fig. 1 and Fig. 2, the test macro of the feed line automatization system that the utility model provides is described in detail, it is the utility model optional embodiment, can think, those skilled in the art, in the scope not changing the utility model spirit and content, can modify to it and polish.
Present embodiments provide a kind of test macro of feed line automatization system, comprise some submodules and bus controller; In the present embodiment, the quantity of described submodule is eight; Each described submodule configures a submodule MCU, and described bus controller can configure a main MCU;
Realized the transmission of communication signal by first kind connecting line between described bus controller and each described submodule;
Realized the transmission of control signal by Equations of The Second Kind connecting line between described bus controller and each described submodule;
Each described submodule all at least in order to:
Respond the communication signal come through the transmission of described first kind connecting line, generate according to this communication signal and to export in ac current signal that a drive test tries out and the ac voltage signal that a drive test is tried out one of at least;
Respond the control signal come through described Equations of The Second Kind connecting line transmission, carry out operating and feedback of status according to this control signal.
For described first kind connecting line and communication signal:
Each described submodule is all further in order to generate according to the waveform character value comprised in described signal of communication and to export in described ac current signal and ac voltage signal one of at least.
Described first kind connecting line comprises RS485 bidirectional serial data lines, and the RS485 communication port of all described submodules is all connected to the RS485 communication port of described bus controller by described RS485 bidirectional serial data lines; In the present embodiment, some RS485 bidirectional serial data lines are by being connected to the RS485 communication port of described bus controller after divider parallel connection.
Each described submodule all further in order to:
By the RS485 differential signal that the response of described RS485 communication port comes through described RS485 bidirectional serial data lines transmission, generate according to the waveform character value comprised in this RS485 differential signal and export described ac current signal and ac voltage signal one of at least.
For described Equations of The Second Kind connecting line and control signal:
In the present embodiment, described Equations of The Second Kind connecting line comprises detection (CK) signal wire, each CK port of described bus controller is connected with a described submodule respectively by described detection (CK) signal wire, described bus controller also in order to detection (CK) signal that response comes through the transmission of described detection (CK) signal wire, judges whether connexon module.
The action principle detecting (CK) signal can configure as follows: bus controller side is provided with pull-up resistor, and submodule side is provided with shorting stub over the ground.During without submodule, this signal is high level, and after submodule inserts bus, this signal is forced to draw as low level by submodule.Bus controller is by this level state, and whether recognin module exists.
In the present embodiment, described Equations of The Second Kind connecting line comprises interruption (INT) signal wire, and each INT port of described bus controller is connected with a described submodule respectively by described interruption (INT) signal wire;
Described submodule also in order to when an exception occurs, interrupts (INT) signal by described interruption (INT) signal wire feedback one;
Interruption (INT) signal that described bus controller also transmits through described interruption (INT) signal wire in order to response and comes, corresponding action control signal is exported according to the rule preset, such as stop the output of described communication signal, or provide other corresponding actions as the case may be.
Interrupt the effect of (INT) signal wire to be: when certain submodule occurs abnormal, can INT=0 be made, interrupt the output of described ac current signal and ac voltage signal, then report to bus controller.Bus controller provides corresponding actions as the case may be.
In the present embodiment, described Equations of The Second Kind connecting line comprises clearing (CLR) signal wire, the CLR port of described bus controller is connected with some described submodules respectively by some described clearing (CLR) signal wires, described submodule also in order to clearing (CLR) signal that response comes through the transmission of described clearing (CLR) signal wire, makes described ac current signal and ac voltage signal zero.The action principle resetting (CLR) signal is: when bus controller needs output waveform signals to make zero, make CLR=0, exports and resets.
In the present embodiment, described Equations of The Second Kind connecting line comprises reseting signal line, the RST port of described bus controller is connected with some described submodules respectively by some described reseting signal lines, and described submodule also in order to the reset signal that response comes through described reseting signal line transmission, resets.
In the present embodiment, described Equations of The Second Kind connecting line comprises sheet choosing (CS) signal wire and beginning (STA) signal wire, each CS port of described bus controller is connected with a described submodule respectively by one described choosing (CS) signal wire, and the STA port of described bus controller is connected with some described submodules respectively by some described beginning (CS) signal wires;
Described submodule also in order to specific sheet choosing (CS) signal that response comes through described choosing (CS) signal wire transmission, is defined as selected submodule, and then:
Beginning (STA) signal that selected submodule response comes through the transmission of described beginning (STA) signal wire, activates running, thus generates and export described ac current signal and ac voltage signal.
In the present embodiment, described Equations of The Second Kind connecting line comprises clock (CLK) signal wire, the CLK interface of described bus controller is connected with some described submodules respectively by some described clock (CLK) signal wires, and described bus controller is in order to be sent to each described submodule by described clock (CLK) signal wire respectively by same clock (CLK) signal.
Wave form output flow process can be described as: CS1=0 → bus controller sends module 1 waveform character value to RS485 → CS1=1, CS2=0 → bus controller sends module 2 waveform character value to RS485 ... CS7=1, CS8=0 → bus controller is sent module 8 waveform character value and is exported → send CLK to RS485 → STA=0 startup, submodule upgrades primary reflection graphic data to digital to analog converter at each CLK rising edge, realizes wave form output.If output waveform is identical, then can choose multiple chip selection signal simultaneously.
The tester bus that the present embodiment relates to has following beneficial effect:
1. conveniently mount, remove submodule, expansion is convenient;
2. mutual electrical isolation between submodule, submodule and bus controller electrical isolation, improve security of system grade;
3. adopt bi-directional serial data communication (RS485), reduce isolation cost, simplify signal wire between module;
4. adopt CS signal, prevent bus collision;
5. adopt INT signal, improve master controller response speed;
6. adopt CLK signal, ensure submodule data synchronization updating;
7. adopt CLR signal, facilitate output signal one key to reset;
8. adopt RST signal, when submodule crashes, conveniently reset submodule;
9. adopt STA signal, ensure that output waveform is synchronous;
10. adopt CK signal, whether recognin module exists;
In sum, the utility model by the workload allocations of a MCU to multiple submodule, each submodule can configure a MCU, waveform computing can be gone, range has switched, export the inter-related tasks such as control, signal back production, closed-loop control, each submodule all can be generated and to export in ac current signal that a drive test tries out and the ac voltage signal that a drive test is tried out one of at least, so just realize the isolation of multi signal, and alleviate the burden of a MCU.But during multimode co-operation, the deficiency of its serial communication also can bring problem, for this reason, the utility model further increases control signal, finally, adopt the method for serial communication+control signal, effective address signal isolating problem and core MCU bear heavier problem.

Claims (8)

1. a test macro for feed line automatization system, is characterized in that: comprise some submodules and bus controller;
Realized the transmission of communication signal by first kind connecting line between described bus controller and each described submodule;
Realized the transmission of control signal by Equations of The Second Kind connecting line between described bus controller and each described submodule.
2. the test macro of feed line automatization system as claimed in claim 1, it is characterized in that: described first kind connecting line comprises RS485 bidirectional serial data lines, the RS485 communication port of all described submodules is all connected to the RS485 communication port of described bus controller by described RS485 bidirectional serial data lines.
3. the test macro of feed line automatization system as claimed in claim 1, it is characterized in that: described Equations of The Second Kind connecting line comprises signal lines, each CK port of described bus controller is connected with a described submodule respectively by a described signal lines.
4. the test macro of feed line automatization system as claimed in claim 1, it is characterized in that: described Equations of The Second Kind connecting line comprises look-at-me line, each INT port of described bus controller is connected with a described submodule respectively by a described look-at-me line.
5. the test macro of feed line automatization system as claimed in claim 1, is characterized in that: described Equations of The Second Kind connecting line comprises reset signal line, and the CLR port of described bus controller is connected with some described submodules respectively by some described reset signal lines.
6. the test macro of feed line automatization system as claimed in claim 1, is characterized in that: described Equations of The Second Kind connecting line comprises reseting signal line, and the RST port of described bus controller is connected with some described submodules respectively by some described reseting signal lines.
7. the test macro of feed line automatization system as claimed in claim 1, it is characterized in that: described Equations of The Second Kind connecting line comprises chip selection signal line and commencing signal line, each CS port of described bus controller is connected with a described submodule respectively by a described chip selection signal line, and the STA port of described bus controller is connected with some described submodules respectively by some described commencing signal lines.
8. the test macro of feed line automatization system as claimed in claim 1, is characterized in that: described Equations of The Second Kind connecting line comprises clock cable, and the CLK interface of described bus controller is connected with some described submodules respectively by some described clock cables.
CN201520138789.7U 2015-03-11 2015-03-11 The test macro of feed line automatization system Expired - Fee Related CN204405771U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107742371A (en) * 2017-10-19 2018-02-27 前海哆啦阿梦(深圳)数据服务有限公司 Charging, storage all-in-one for shared charger baby
CN111537608A (en) * 2020-05-08 2020-08-14 中国航空制造技术研究院 Ultrasonic detection device
CN112505444A (en) * 2020-10-20 2021-03-16 上海金智晟东电力科技有限公司 Feeder automation field test system and method based on state fitting

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107742371A (en) * 2017-10-19 2018-02-27 前海哆啦阿梦(深圳)数据服务有限公司 Charging, storage all-in-one for shared charger baby
CN111537608A (en) * 2020-05-08 2020-08-14 中国航空制造技术研究院 Ultrasonic detection device
CN112505444A (en) * 2020-10-20 2021-03-16 上海金智晟东电力科技有限公司 Feeder automation field test system and method based on state fitting

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CF01 Termination of patent right due to non-payment of annual fee
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Granted publication date: 20150617

Termination date: 20190311