CN204347842U - A kind of main equipment is to the authenticate device of its slave - Google Patents

Abstract

The utility model discloses the authenticate device of a kind of main equipment to its slave, comprise key generation system, configure the first certification integrated circuit and the first telecommunication circuit in the host and be configured in slave C _iin the second certification integrated circuit and second communication circuit; First certification integrated circuit comprises first memory, digital random number generator, the first pseudo-random function chip, ECC (elliptic curve cipher) algorithm circuit and authentication output results contrast unit; First telecommunication circuit is connected with first memory, digital random number generator and ECC algorithm circuit respectively; Second certification integrated circuit comprises second memory, the second pseudo-random function chip and exports digital signing circuit; Second communication circuit is respectively with second memory, the second pseudo-random function chip with export digital signing circuit and be connected; First telecommunication circuit is connected by network with the second logical unit.The utility model has the advantage that counting yield is high, cost is low and security is high.

Description

A kind of main equipment is to the authenticate device of its slave

Technical field

The utility model relates to electronic equipments safety authenticate device, and particularly a kind of main equipment is to the authenticate device of its slave.

Background technology

Electronic equipment and electronic components have been widely used in many fields, the electronic communication equipments such as such as computer, smart mobile phone, network devices, electronic equipment and the electronic components thereof such as the B ultrasonic in health care, Magnetic resonance imaging, hyperbaric oxygen chamber.Usually, the famous brand electronic equipment that quality is pure to win a high reputation and accessory thereof, compare the favor being subject to consumer.Meanwhile, the famous brand name product utilizing poor material to make personation also becomes the main target of fake producer day by day.In order to ensure the interests of electronic equipment and accessory business and consumer thereof, electronic equipment and accessory thereof that relevant industries are all using anti-counterfeiting technology to protect oneself, prevent personation.

Modern anti-counterfeiting technology generally can be divided into two classes, namely based on the mode of the specific physical property of product and the mode based on digital technology.The first makes product identification or software package by special manufacturing step or special material, and its anti-fraud functional realization is better than this hypothesis of personator based on the manufacturing technology of rightful manufacturers.The second depends on cryptographic system; These cryptographic system security properties only depend on maintaining secrecy of key, instead of be based upon manufacturer be technically better than in the theory of personator; Its false proof protection level to depend primarily in cryptographic system use the length of key, by the length expanding key, imitated being difficult to of personator is realized.Usually, slave belongs to low-end electronic product, there is limited computing power and storage space, consideration is needed to realize anti-fraud functional efficiency, and substantially only consider in existing anti-counterfeiting technology that a main equipment is to the certification of a slave, and many main equipments usually configure multiple slave, sometimes need to carry out certification to several slave simultaneously.So, how above-mentioned disappearance problem is improved, be those skilled in the art for solve technical difficulties place.

Utility model content

The purpose of this utility model is to overcome the shortcoming of prior art with not enough, provides a kind of counting yield is high, cost is low main equipment to the authenticate device of its slave, and can realize the main equipment once multiple slave of certification.

The purpose of this utility model is achieved through the following technical solutions: a kind of main equipment, to the authenticate device of its slave, comprises key generation system, configures the first certification integrated circuit and the first telecommunication circuit in the host and be configured in slave C _iin the second certification integrated circuit and second communication circuit;

The first certification integrated circuit that described main equipment configures comprises first memory, digital random number generator, the first pseudo-random function chip, ECC (elliptic curve cipher) algorithm circuit and authentication output results contrast unit; First telecommunication circuit is connected with first memory, digital random number generator and ECC algorithm circuit respectively; First memory is connected with the first pseudo-random function chip, ECC algorithm circuit and authentication output results contrast unit respectively; The output terminal of digital random number generator is connected with the first pseudo-random function chip; The output terminal of described first pseudo-random function chip connects the input end of ECC algorithm circuit, and the output terminal of described ECC algorithm circuit connects the input end of authentication output results contrast unit;

The the second certification integrated circuit configured in described slave comprises

Second memory, the second pseudo-random function chip and output digital signing circuit; Second communication circuit is respectively with second memory, the second pseudo-random function chip with export digital signing circuit and be connected, second memory is respectively with the second pseudo-random function chip with exports digital signing circuit and is connected, the output terminal connection output digital signing circuit of the second pseudo-random function chip;

Described key generation system is connected with first memory and second memory respectively, and the first telecommunication circuit is connected by network with the second logical unit.

Preferably, the first memory in main equipment first certification integrated circuit stores the common parameter (q, P) of elliptic curve cryptography, slave C _ithe PKI PK corresponding with between main equipment _iand record slave C _ithe data D of current state _iand mark τ _i; First memory comprises common parameter basic point P output terminal, common parameter q output terminal, slave C _ithe PKI PK corresponding with between main equipment _ithe data D of output terminal, record slave current state _iinput end and output terminal and data D _imark τ _iinput end and output terminal;

Second memory in slave second certification integrated circuit stores the common parameter q of elliptic curve cryptography, slave C _ithe inverse element 1/sk of private key _ioutput terminal, second memory comprises the private key inverse element 1/sk of common parameter q output terminal, slave _ithe mark output terminal of output terminal, slave status data output terminal and slave status data;

First telecommunication circuit and second communication circuit include record slave C _ithe data D of current state _iinput end and output terminal, data D _imark τ _iinput end and output terminal, digital signature y _1iinput end and output terminal and challenge information c _iinput end and output terminal;

The record slave C of the first telecommunication circuit _ithe data D of current state _iinput end connects the record slave C of second communication circuit by networking _ithe data D of current state _ioutput terminal, the data D of the first telecommunication circuit _imark τ _iinput end connects the data D of second communication circuit by networking _imark τ _ioutput terminal; First telecommunication circuit from digital signature y _1iinput end connects the digital signature y of second communication circuit by networking _1ioutput terminal; The challenge information c of the first telecommunication circuit _ioutput terminal is by the challenge information c of networking and second communication circuit _iinput end connects;

The challenge information c of the first telecommunication circuit _iinput end connects random number generator output terminal, the digital signature output terminal y of the first telecommunication circuit _1ibe connected with ECC algorithm circuit, the record slave C of the first telecommunication circuit _ithe data D of current state _ithe data D of the record slave current state of output terminal and first memory _iinput end connects, the data D of the first telecommunication circuit _imark τ _ithe data D of output terminal and first memory _imark τ _iinput end connects;

The challenge information c of second communication circuit _ioutput terminal is connected with the second pseudo-random function chip; The digital signature y of second communication circuit _1iinput end is connected with output digital signing circuit output terminal; The record slave C of second communication circuit _ithe data D of current state _iinput end connects the record slave C of second memory _ithe data D of current state _ioutput terminal; The data D of second communication circuit _imark τ _iinput end connects the data D of second memory _imark τ _ioutput terminal.

Further, authenticate device comprises one and is configured in slave C _iin the second certification integrated circuit, the number of the slave that authentication authorization and accounting device will authenticate is one;

The first pseudo-random function chip internal in main equipment first certification integrated circuit is embedded with seed key K, the first NOR gate circuit and the first AES encryption algorithm chip, the data D of one of them input end of the first NOR gate circuit and first memory _imark τ _ioutput terminal connects, the mark of the corresponding slave current status data stored in input first memory, and another input end is connected with random number generator, the random number c as corresponding slave challenge information that input random number generator generates _i; One of them input end of described first AES encryption algorithm chip is connected with the output terminal of the first NOR gate circuit, another input end input seed key K, and the output terminal of the first AES encryption algorithm chip connects ECC algorithm circuit;

In main equipment first certification integrated circuit, ECC algorithm circuit comprises the first scale subtraction gate circuit, the first mould remainder circuit, the first dot product musical instruments used in a Buddhist or Taoist mass and second point multiplier;

The output terminal that first scale subtraction gate circuit minuend input end connects the first AES encryption algorithm chip in the first pseudo-random function core connects, and described first scale subtraction gate circuit subtracting input connects the record slave C of first memory _ithe data D of current state _ioutput terminal, the corresponding slave C of the record stored in input first memory _ithe data D of current state _i;

The output terminal of the first scale subtraction gate circuit connects one of them input end of the first mould remainder circuit; Another input end of first mould remainder circuit connects the common parameter q output terminal of first memory;

The output terminal of the first mould remainder circuit connects one of them input end of the first dot product musical instruments used in a Buddhist or Taoist mass; Another input end of first dot product musical instruments used in a Buddhist or Taoist mass connects the basic point P output terminal of the common parameter of first memory; The output terminal of the first dot product musical instruments used in a Buddhist or Taoist mass connects the first data input pin of first memory;

One of them input end of second point multiplier connects the slave C of first memory _ithe PKI PK corresponding with between main equipment _ioutput terminal, inputs and to be generated by key generation system and by the corresponding slave private key sk stored in first memory _ipKI PK corresponding in the host _i; Another input end of second point multiplier connects the digital signature y of the first telecommunication circuit _1ioutput terminal; The output terminal of second point multiplier connects the input end of authentication output results contrast unit;

The not circuit that described authentication output results contrast unit comprises NOR gate circuit and is connected with NOR gate circuit output terminal; One of them input end of NOR gate circuit connects the first data output end of first memory; Another input end of NOR gate circuit connects the output terminal of second point multiplier.

Further, described authenticate device comprises L and is configured in each slave C respectively _iin the second certification integrated circuit, the number of the slave that authentication authorization and accounting device will authenticate is L, wherein i ∈ [1, L];

First memory comprises L+1 data storage cell, i-th data cell stores slave C _ithe PKI PK corresponding with between main equipment _i, record slave C _ithe data D of current state _iand mark τ _i, the common parameter (q, P) of L+1 data cell stores elliptic curve cryptography;

First pseudo-random function chip internal is embedded with the chip of seed key K, a L the first NOR gate circuit and L AES encryption algorithm, the record slave C of i-th data storage cell wherein in i-th one of them input end of the first NOR gate circuit connection first memory _ithe data D of current state _ioutput terminal, another input end is connected with random number generator, and one of them input end of i-th the first AES encryption algorithm chip is connected with the output terminal of i-th the first NOR gate circuit, another input end input seed key K;

ECC algorithm circuit comprises a L-subtraction circuit, a L-scale adding circuit, one (L+1)-the first point multiplication circuit, a L-point adding circuit and a L-second point mlultiplying circuit;

L-subtraction circuit comprises L scale subtracter and L mould remainder circuit, wherein one of them input end of i-th scale subtracter connects i-th the first AES encryption algorithm chip output terminal, and another input end connects the record slave C of i-th data storage cell _ithe data D of current state _i, one of them input end of i-th mould remainder circuit connects the output terminal of i-th scale subtracter, and another input end connects the common parameter q output terminal of L+1 data storage cell; The output terminal of L mould remainder circuit connects each input end of L-scale adding circuit respectively; The output terminal of i-th mould remainder circuit connects the second data input pin of i-th data storage cell;

(L+1) the-the first point multiplication circuit comprises L+1 the first dot product musical instruments used in a Buddhist or Taoist mass, wherein one of them input end of L+1 the first dot product musical instruments used in a Buddhist or Taoist mass connects the output terminal of L-scale adding circuit, another input end connects the common parameter basic point P output terminal of L+1 data storage cell, and output terminal connects the 3rd data input pin of L+1 data storage cell; One of them input end of i-th the first dot product musical instruments used in a Buddhist or Taoist mass connects the second data output end of i-th data storage cell, another input end connects the common parameter basic point P output terminal of L+1 data storage cell, and output terminal connects the 4th data input pin of i-th data storage cell;

L-second point mlultiplying circuit comprises L second point multiplier, and wherein one of them input end of i-th second point multiplier connects the slave C of i-th data storage cell _ithe PKI PK corresponding with between main equipment _ioutput terminal, another input end connects the digital signature y of the first telecommunication circuit _1ioutput terminal, output terminal connects the 5th data input pin of i-th data storage cell; The output terminal of each second point multiplier connects L-point adding circuit respectively simultaneously;

Authentication output results contrast unit comprises L+1 NOR gate circuit, each NOR gate circuit output terminal is connected to not circuit, wherein one of them input end of L+1 NOR gate circuit connects the 3rd data output end of L+1 data storage cell, and another input end connects the output terminal of L-point adding circuit in ECC algorithm circuit; One of them input end of i-th NOR gate circuit connects the 4th data output end of i-th data storage cell, and another input end connects the 5th data output end of i-th data storage cell.

Further, described L-scale adding circuit comprises L-1 scale totalizer, wherein one of them input end of the 1st scale totalizer connects the output terminal of the 1st mould remainder circuit, another input end connects the 2nd mould remainder circuit output end, xth one of them input end of scale totalizer connects xth-1 the first scale adder output, another input end connects a (x+1)th mould remainder circuit output end, wherein x ∈ [2, L-1].

Further, described L-point adding circuit comprises L-1 some totalizer, wherein one of them input end of the 1st some totalizer connects the output terminal of the 1st second point multiplier, another input end connects the 2nd second point multiplier outputs, xth one of them input end of some totalizer connects xth-1 first adder output, another input end connects a (x+1)th second point multiplier outputs, wherein x ∈ [2, L-1].

Further, the number of described random number generator is one, and the random number generator that in the first pseudo-random function chip, each first NOR gate circuit input end connects is same.

Further, the number of described random number generator is L, and in the first pseudo-random function chip, i-th the first NOR gate circuit input end connects the output terminal of i-th random number generator.

Further, slave C _isecond pseudo-random function chip internal of the second certification integrated circuit is embedded with seed key K, the second NOR gate circuit and the second AES encryption algorithm chip, the data D of one of them input end of the second NOR gate circuit and second memory _imark τ _ioutput terminal connects, the challenge information c of another input end and second communication circuit _ioutput terminal connects; One of them input end of described second AES encryption algorithm chip is connected with the output terminal of the second NOR gate circuit, and another input end input seed key K, the output terminal of the second AES encryption algorithm chip connects the input end exporting digital signing circuit.

Further, the output digital signing circuit in described slave second certification integrated circuit comprises the second scale subtraction gate circuit, scalar multilication gate circuit and the second mould remainder circuit;

The minuend input end of the second scale subtraction gate circuit connects the output terminal of the second AES encryption algorithm chip, and subtracting input connects the data D of second memory _imark τ _ioutput terminal connects;

One of them input end of second scalar multilication gate circuit connects the output terminal of subtraction gate circuit, and another input end connects the slave C of second memory _ithe inverse element 1/sk of private key _ioutput terminal;

One of them input end of second mould remainder circuit connects the output terminal of the second scalar multilication gate circuit, and another input end connects the common parameter q output terminal of second memory; The output terminal of the second mould remainder circuit, as the output terminal exporting digital signing circuit, is connected with the digital signature input end of second communication unit in slave second certification integrated circuit.

The utility model has following advantage and effect relative to prior art:

(1) the utility model is configured in slave second certification integrated circuit when not needing the public key operation of execution point multiplication, the random shared key corresponding with main equipment can be generated by the second certification integrated circuit according to the data of challenge information, record slave current state and mark thereof, then export the response message corresponding with the data of record slave current state by the output digital signing circuit of the second integrated circuit.When the generation of random shared key, first certification integrated circuit (IC) apparatus and the second certification integrated circuit (IC) apparatus all only need the chip of the pseudo-random function calling band seed key, without the need to sending the random shared key that a side generates to the opposing party by network, while saving Internet resources, ensure the security of random shared key.Challenge-response mode is utilized between main equipment and slave, based on the digital signature identification slave in response message, to stop the use of personation slave, improve the antiforge function of the slave of main equipment, stronger stopped to palm off slave and can authenticate the possibility passed through.The utility model authenticate device has the advantage that counting yield is high, cost is low and security is high.

(2) the ECC algorithm circuit in the utility model main equipment first certification integrated circuit can support the multiple slave of main equipment certification simultaneously, verifies in multiple slave whether there is fake products.

(3) the utility model authenticate device is used for main equipment with when once carrying out certification for multiple slave, and in each first pseudo-random function chip, each first xor operation unit input end can all be connected with same random number output terminal with the random number input end of the first communication unit.Therefore the random number generator in main equipment first certification integrated circuit sends to the challenge information of the second communication unit of each slave second certification integrated circuit can be identical, therefore by broadcast transmission challenge information to slave, decrease communications cost.

Accompanying drawing explanation

Fig. 1 is the utility model structural representation.

Fig. 2 is utility model first certification integrated circuit structure schematic diagram.

Fig. 3 is the utility model second certification integrated circuit structure schematic diagram.

Fig. 4 is the schematic diagram of the utility model second certification integrated circuit.

The schematic diagram of the first certification integrated circuit when Fig. 5 is a certification slave in the utility model embodiment 1.

The schematic diagram of the first certification integrated circuit when Fig. 6 is the multiple slave of certification in the utility model embodiment 2.

Embodiment

Below in conjunction with embodiment and accompanying drawing, the utility model is described in further detail, but embodiment of the present utility model is not limited thereto.

Embodiment 1

As shown in Figure 1, present embodiment discloses the authenticate device of a kind of main equipment to its slave, comprise key generation system, configure the first certification integrated circuit and the first telecommunication circuit in the host and be configured in slave C _iin the second certification integrated circuit and second communication circuit; First certification integrated circuit of main equipment reads and reads record slave C by the second certification integrated circuit of slave _ithe data D of current state _iand mark τ _i, and to corresponding slave C _isend challenge information c _i, slave C _iutilize the data D of private key and record slave current state _iand mark τ _igenerate about challenge information c _isigning messages y _1ias response, main equipment is according to slave C _ipKI PK _iy can be verified _iwhether be about (τ _i, D _i, c _i) effective signature, realize slave C _icertification, wherein i=1 ..., L.First certification integrated circuit of the present embodiment main equipment and each slave C _ithe second certification integrated circuit by arranging the first telecommunication circuit on the master and being arranged on each slave C _ion second communication circuit communicate.First certification integrated circuit is provided with and carries out the communications component interface be connected and the power interface be connected with power supply with the first telecommunication circuit; Second certification integrated circuit is provided with and carries out the communications component interface be connected and the power interface be connected with power supply with second communication circuit.

In the present embodiment, the main equipment of the first certification integrated circuit can be mobile phone, video camera, MP3 player, personal digital assistant, games system, audio frequency and/or video system or other amusement equipment; It can be computer, computer system, network or computing equipment, duplicating machine, scanner or other digital imagery or reproducing device; It can be medical treatment device or equipment or diagnostor; It can be automobile and automotive system or some other electronics or computer equipment.

The slave having the second certification integrated circuit (IC) apparatus in the present embodiment can be the accessory after sale of main equipment or battery, and these accessories can be earphone, headphone, loudspeaker, docking station, game console, charger, microphone etc.; Can be the assembly of computing machine or computer system, the network equipment, peripherals, USB or other memory storage; Can be auto parts, parts or annex; Or some miscellaneous parts, annex or assembly, and perform required or desired parts, annex or the assembly of some certifications.

As shown in Figure 2, the first certification integrated circuit configured in the present embodiment main equipment comprises first memory, digital random number generator, the first pseudo-random function chip, ECC (elliptic curve cipher) algorithm circuit and authentication output results contrast unit; First telecommunication circuit is connected with first memory, digital random number generator and ECC algorithm circuit respectively; First memory is connected with the first pseudo-random function chip, ECC algorithm circuit and authentication output results contrast unit respectively; The output terminal of random number generator is connected with the first pseudo-random function chip; The output terminal of the first pseudo-random function chip connects the input end of ECC algorithm circuit, and the output terminal of ECC algorithm circuit connects the input end of authentication output results contrast unit.

As shown in Figure 3, the second certification integrated circuit configured in the slave of the present embodiment comprises second memory, the second pseudo-random function chip and exports digital signing circuit; Second communication circuit is respectively with second memory, the second pseudo-random function chip with export digital signing circuit and be connected, second memory is respectively with the second pseudo-random function chip with exports digital signing circuit and is connected, the output terminal connection output digital signing circuit of the second pseudo-random function chip;

Key generation system is connected with first memory and second memory respectively, and the first telecommunication circuit is connected by network with the second logical unit.

The ECC algorithm circuit selected according to main equipment of key generation system in the present embodiment, the common parameter (q, P) of elliptic curve cryptography, the basic point P namely on elliptic curve and the Prime Orders q of correspondence thereof, to each slave C _idistribute different private key sk _i, and calculate slave C _ithe PKI PK corresponding with between main equipment _i=sk _ip and private key are about the inverse element 1/sk of Prime Orders q _i, then by q and 1/sk _ibe deposited into corresponding slave C _iin the second memory of the second certification integrated circuit; By the common parameter (q, P) of elliptic curve cryptography, slave C _ithe PKI PK corresponding with between main equipment _iin first memory stored in the first certification integrated circuit in main equipment.Simultaneously according to COS and the properties of product of slave manufacturer configuration, generate the data D of record slave current state _iand mark τ _i, simultaneously by (τ _i, D _i) be kept in second memory.

In the present embodiment, first memory comprises common parameter basic point P output terminal, common parameter q output terminal, slave C _ithe PKI PK corresponding with between main equipment _ithe data D of output terminal, record slave current state _iinput end and output terminal and data D _imark τ _iinput end and output terminal.Second memory comprises the private key inverse element 1/sk of common parameter q output terminal, slave _ithe mark output terminal of output terminal, slave status data output terminal and slave status data;

First telecommunication circuit of the present embodiment and second communication circuit include record slave C _ithe data D of current state _iinput end and output terminal, data D _imark τ _iinput end and output terminal, digital signature y _1iinput end and output terminal and challenge information c _iinput end and output terminal;

The record slave C of the first telecommunication circuit _ithe data D of current state _iinput end connects the record slave C of second communication circuit by networking _ithe data D of current state _ioutput terminal, the data D of the first telecommunication circuit _imark τ _iinput end connects the data D of second communication circuit by networking _imark τ _ioutput terminal; First telecommunication circuit from digital signature y _1iinput end connects the digital signature y of second communication circuit by networking _1ioutput terminal; The challenge information c of the first telecommunication circuit _ioutput terminal is by the challenge information c of networking and second communication circuit _iinput end connects;

The challenge information c of the first telecommunication circuit _iinput end connects random number generator output terminal, the digital signature output terminal y of the first telecommunication circuit _1ibe connected with ECC algorithm circuit, the record slave C of the first telecommunication circuit _ithe data D of current state _ithe data D of the record slave current state of output terminal and first memory _iinput end connects, the data D of the first telecommunication circuit _imark τ _ithe data D of output terminal and first memory _imark τ _iinput end connects;

The challenge information c of second communication circuit _ioutput terminal is connected with the second pseudo-random function chip; The digital signature y of second communication circuit _1iinput end is connected with output digital signing circuit output terminal; The record slave C of second communication circuit _ithe data D of current state _iinput end connects the record slave C of second memory _ithe data D of current state _ioutput terminal; The data D of second communication circuit _imark τ _iinput end connects the data D of second memory _imark τ _ioutput terminal.

As shown in Figure 4, slave C in the present embodiment _isecond pseudo-random function chip internal of the second certification integrated circuit is embedded with seed key K, the second NOR gate circuit and the second AES encryption algorithm chip;

The data D of one of them input end of the second NOR gate circuit and second memory _imark τ _ioutput terminal connects, the challenge information c of another input end and second communication circuit _ioutput terminal connects.Encrypting plaintext is obtained by the second NOR gate circuit

One of them input end of second AES encryption algorithm chip is connected with the output terminal of the second NOR gate circuit, and another input end input seed key K, the output terminal of the second AES encryption algorithm chip connects the input end exporting digital signing circuit.The present embodiment second AES encryption algorithm chip is based on the pseudo-random function of symmetric encipherment algorithm AES utilize seed key K to binary character string be encrypted, get random shared key the second pseudo-random function chip of the present embodiment is according to challenge information c _iwith Data Identification τ _igenerate the random shared key of main equipment and slave

As shown in Figure 4, the output digital signing circuit in the present embodiment slave second certification integrated circuit comprises the second scale subtraction gate circuit, scalar multilication gate circuit and the second mould remainder circuit;

The minuend input end of the second scale subtraction gate circuit connects the output terminal of the second AES encryption algorithm chip, and subtracting input connects the data D of second memory _imark τ _ioutput terminal connects.Namely minuend is the random shared key that the second AES encryption algorithm chip exports subtrahend is slave status data y _0i=D _i, got by the second scale subtraction gate circuit with y _0idifference

One of them input end of scalar multilication gate circuit connects the output terminal of subtraction gate circuit, and another input end connects the slave C of second memory _ithe inverse element 1/sk of private key _ioutput terminal.Namely input respectively at the input end of scalar multilication gate circuit with private key inverse element 1/sk _i, the inverse element of private key is got by scalar multilication gate circuit with long-pending ${\hat{z}}_i-s{\hat{k}}_i\·{\hat{y}}_i.$

One of them input end of second mould remainder circuit connects the output terminal of the second scalar multilication gate circuit, and another input end connects the common parameter q output terminal of second memory; The output terminal of the second mould remainder circuit, as the output terminal exporting digital signing circuit, is connected with the digital signature input end of second communication unit in slave second certification integrated circuit.The digital signature exporting digital signing circuit is got by the second mould remainder circuit as corresponding challenge information c _iresponse message y _1i.

The number L of the slave that the present embodiment authenticate device will authenticate is 1, i.e. L=i=1, then authenticate device comprises one and is configured in slave C _iin the second certification integrated circuit.As shown in Figure 5, when the present embodiment main equipment certification slave, the particular circuit configurations of the present embodiment main equipment first certification integrated circuit is as follows:

The first pseudo-random function chip internal in the present embodiment main equipment first certification integrated circuit is embedded with seed key K, the first NOR gate circuit and the first AES encryption algorithm chip.

The data D of one of them input end of the first NOR gate circuit and first memory _imark τ _ioutput terminal connects, the mark of the corresponding slave current status data stored in input first memory, and another input end is connected with random number generator, the random number c as corresponding slave challenge information that input random number generator generates _i.

One of them input end of first AES encryption algorithm chip is connected with the output terminal of the first NOR gate circuit, and another input end input seed key K, the output terminal of the first AES encryption algorithm chip connects ECC algorithm circuit.First certification integrated circuit generates main equipment and slave C by the first pseudo-random function chip _ibetween random shared key

In main equipment first certification integrated circuit, ECC algorithm circuit comprises the first scale subtraction gate circuit, the first mould remainder circuit, the first dot product musical instruments used in a Buddhist or Taoist mass and second point multiplier;

The output terminal that first scale subtraction gate circuit minuend input end connects the first AES encryption algorithm chip in the first pseudo-random function core connects, and the first scale subtraction gate circuit subtracting input connects the record slave C of first memory _ithe data D of current state _ioutput terminal, the corresponding slave C of the record stored in input first memory _ithe data D of current state _i.By the first scale subtraction gate circuit for the first pseudo-random function the random shared key exported in core with slave status data y _0i=D _isubtraction, gets with y _0idifference ${\hat{y}}_i=r_{{\mathrm{\τ}}_i}-y_{0i}.$

The output terminal of the first scale subtraction gate circuit connects one of them input end of the first mould remainder circuit; Another input end of first mould remainder circuit connects the common parameter q output terminal of first memory.Got by the first mould remainder circuit $h_i=(r_{{\mathrm{\τ}}_i}-D_i)\mathrm{mod}q;$

The output terminal of the first mould remainder circuit connects one of them input end of the first dot product musical instruments used in a Buddhist or Taoist mass; Another input end of first dot product musical instruments used in a Buddhist or Taoist mass connects the basic point P output terminal of the common parameter of first memory; H is got by the first dot product musical instruments used in a Buddhist or Taoist mass _ip, the output terminal of the first dot product musical instruments used in a Buddhist or Taoist mass connects the first data input pin of first memory, by the h that the first multiplier gets _ip is stored in first memory as the first data.

One of them input end of second point multiplier connects the slave C of first memory _ithe PKI PK corresponding with between main equipment _ioutput terminal, inputs and to be generated by key generation system and by the corresponding slave private key sk stored in first memory _ipKI PK corresponding in the host _i; Another input end of second point multiplier connects the digital signature y of the first telecommunication circuit _1ioutput terminal; The output terminal of second point multiplier connects the input end of authentication output results contrast unit; Corresponding slave C is got by second point multiplier _idigital signature y _1iwith corresponding slave private key sk _ipKI PK corresponding in the host _ithe scalar multilication result y of output point _1ipK _i.

The not circuit that authentication output results contrast unit comprises NOR gate circuit and is connected with NOR gate circuit output terminal; One of them input end of NOR gate circuit connects the first data output end of first memory, in this input end, namely input the first data h that first memory stores _ip.Another input end of NOR gate circuit connects the output terminal of second point multiplier.Y is inputted respectively at two input ends of NOR gate circuit _1ipK _iand h _ip, verifies y by NOR gate circuit _1ipK _i=h _iwhether the equation of P is set up.

The specific works process of the present embodiment authenticate device is as follows:

(1) key generation process: the ECC algorithm circuit that key generation system is selected according to main equipment, obtains the Prime Orders q of basic point P on elliptic curve and correspondence thereof, to slave C _idistribute private key sk _i, and calculate corresponding PKI PK _i=sk _ip and private key are about the inverse element 1/sk of Prime Orders q _i, then by q and 1/sk _istored in the second memory of slave second certification integrated circuit in this equipment, and by system common parameter (q, P) and PKI PK _istored in the first memory of the first certification integrated circuit in main equipment.Only there is a slave in the present embodiment, therefore L=i=1.

(2) slave sends verify data process: according to COS and the properties of product of slave manufacturer configuration, generate the data D of record slave current state in slave _iand mark τ _i, (τ simultaneously _i, D _i) be kept in the second memory of slave second certification integrated circuit.As slave C _iwhen loading main equipment, main equipment starts the certification to slave; Slave C _ithe data D of record slave current state that will be stored in second memory by second communication circuit of the second memory of the second certification integrated circuit _iand mark τ _ibe sent in first telecommunication circuit of the first certification integrated circuit of main equipment.

(3) data read process of slave: the first certification integrated circuit of main equipment is received from slave C by the first telecommunication circuit _isecond communication circuit send data (τ _i, D _i), and the data received are kept in the first memory of main equipment first certification integrated circuit.

(4) the generation process of transmitting of main equipment challenge information: when the first telecommunication circuit has received the data (τ that the second communication circuit from slave sends _i, D _i) after, by its operation stored in the operation triggered digital random number generator of first memory, the output terminal be connected with the first pseudo-random function chip with the first telecommunication circuit by digital random number generator, digital random number generator exports a random integers c _i, and sending to the first telecommunication circuit and the first pseudo-random function chip respectively, the first telecommunication circuit is by c _islave C is sent to as challenge information _i.

(5) slave receives challenge information and generates random shared key process: slave C _ithe challenge information c of the first telecommunication circuit transmission is received by second communication circuit _i, slave C _ithe challenge information c that second NOR gate circuit of the second pseudo-random function chip of the second certification integrated circuit inputs according to second communication circuit _iwith the mark τ of second memory input _iexport encrypted cipher text then by the pseudo-random function of the second AES encryption algorithm chip based on symmetric encipherment algorithm AES utilize seed key K to binary character string be encrypted, export random shared key

(6) slave generates digital signature procedure: slave C _ithe output digital signing circuit of the second certification integrated circuit is according to the input random shared key from the second pseudo-random function chip module with the input (D from second memory _i, q, 1/sk _i), export signature y _1i.Particularly, the second scale subtraction gate circuit by exporting digital signing circuit exports two and is input to with y _0i=D _idifference scalar multilication gate circuit is according to input with private key inverse element export the long-pending of them second mould remainder circuit exports input about the remainder y of mould q _1i, namely export corresponding data (τ _i, D _i) and challenge information c _idigital signature, wherein digital signature here $y_{1i}=(r_{{\mathrm{\τ}}_i}-D_i)/{\mathrm{sk}}_i\mathrm{mod}q.$

(7) slave sends response message process: the second certification integrated circuit of slave passes through second communication circuit by digital signature y _1ias response message corresponding in current challenge-response authentication mode, sent to the first telecommunication circuit of main equipment by second communication circuit.

(8) generative process of shared key in main equipment: the random integers c that the first NOR gate circuit in the first pseudo-random function chip transmits according to random number generator _i, from first memory, read in corresponding slave C _idata Identification τ _i, the XOR result of these two inputs is exported by the first NOR gate circuit as encrypted cipher text; Then by the pseudo-random function of the first AES encryption algorithm chip based on symmetric encipherment algorithm AES utilize seed key K to binary character string be encrypted, export slave C _ithe random shared key used in signature and will send the first scale subtraction gate circuit in ECC algorithm circuit to.

(9) scale difference and dot product computation process in ECC algorithm circuit: the random shared key that the first scale subtraction gate circuit in ECC algorithm circuit transmits according to the first pseudo-random function chip module the first scale subtraction gate circuit in ECC algorithm circuit module inputs corresponding slave C from first memory _ithe data D of record slave current state _i, export the difference of these two inputs in ECC algorithm circuit, mould remainder unit reads common parameter q from first memory, inputs this difference export the remainder of this difference about mould q and by h _isend the first dot product musical instruments used in a Buddhist or Taoist mass to; First dot product musical instruments used in a Buddhist or Taoist mass is according to input h _iwith the basic point P read in from first memory, export result of calculation h _ip, also preserves this result of calculation in a first memory as the first data.

(10) reception of main equipment response message and dot product computation process thereof: to slave C _isend challenge information c _iafter, main equipment receives slave C by the first telecommunication circuit _ithe response message y that second certification integrated circuit sends _1i.The response message y that first telecommunication circuit will receive _1isend to the second point multiplier of the ECC algorithm circuit in the first certification integrated circuit.Second point multiplier in ECC algorithm circuit is according to input y _1iwith from first memory, read in slave PKI PK _i, export result of calculation Q '=y to the NOR gate circuit in authentication output results contrast unit module _1ipK _i.

(11) verification process of slave: the output h about ECC algorithm circuit first dot product musical instruments used in a Buddhist or Taoist mass in (10) that in ECC algorithm circuit, second point multiplier exports Q ' and stores from first memory _ip these two inputs, the NOR gate circuit in authentication output results contrast unit module exports about Q ' and h to not circuit _ithe XOR result of P, carries out inverse and exports final authentication result.If the final authentication result exported is high level, show slave C _iresponse message y _1imeet equation h _ip=y _1ipK _i, the legal C of this slave of main equipment certification _ieffectively; Otherwise main equipment thinks that this slave is fake products, refusal accepts.

Embodiment 2

The present embodiment also discloses the authenticate device of a kind of main equipment to its slave, and wherein the difference of the present embodiment and embodiment 1 is, the present embodiment authenticate device comprises multiple the second certification integrated circuit be configured in respectively in each slave; Be applicable to main equipment simultaneously for multiple slave C ₁..., C _lcarry out certification, L is the number of slave, wherein i=1,2 ... L, L>1.Each slave C in the present embodiment _iidentical with in embodiment 1 of second integrated circuit of configuration and second communication circuit.The difference of the present embodiment and embodiment 1 is configuration the second certification integrated circuit in the host.The second certification integrated circuit particular circuit configurations is in the host configured as follows in the present embodiment:

As shown in Figure 6, first memory comprises L+1 data storage cell, i-th data cell stores slave C _ithe PKI PK corresponding with between main equipment _i, record slave C _ithe data D of current state _iand mark τ _i, the common parameter (q, P) of L+1 data cell stores elliptic curve cryptography.The record slave C stored in each data storage cell of first memory _ithe data D of current state _iand mark τ _iautomatically remove after each certification completes.

First pseudo-random function chip internal is embedded with seed key K, a L the first NOR gate circuit and L AES encryption algorithm chip;

I-th one of them input end of the first NOR gate circuit connects the record slave C of i-th data storage cell in first memory _ithe data D of current state _ioutput terminal, another input end is connected with random number generator; The random integers c that i-th the first NOR gate circuit in first pseudo-random function chip transmits according to random number generator _i, from first memory i-th data storage cell, read in corresponding slave C _idata Identification τ _i, the XOR result of these two inputs is exported by i-th the first NOR gate circuit as encrypted cipher text.

One of them input end of i-th the first AES encryption algorithm chip is connected with the output terminal of i-th the first NOR gate circuit, another input end input seed key K; I-th the first AES encryption algorithm chip is based on the pseudo-random function of symmetric encipherment algorithm AES utilize seed key K to binary character string be encrypted, export slave C _ithe random shared key used in signature

Each the first AES encryption algorithm chip of first pseudo-random function chip has identical seed key K in the present embodiment, and this seed key K is identical with the seed key K that the second pseudo-random function chip internal in the second certification integrated circuit is embedded with.Slave C is calculated by i-th the first NOR gate circuit in the first pseudo-random function chip and the first AES encryption algorithm chip _iand the shared key between main equipment.

In the present embodiment, ECC algorithm circuit comprises a L-subtraction circuit, a L-scale adding circuit, one (L+1)-the first point multiplication circuit, a L-point adding circuit and a L-second point mlultiplying circuit;

L-subtraction circuit comprises L scale subtracter and L mould remainder circuit, wherein one of them input end of i-th scale subtracter connects i-th the first AES encryption algorithm chip output terminal, and another input end connects the record slave C of i-th data storage cell _ithe data D of current state _i; By the record slave C of i-th scale subtracter to input _ithe data D of current state _iexport with i-th the first AES encryption algorithm chip in the first pseudo-random function chip the difference calculating them, obtain corresponding difference value one of them input end of i-th mould remainder circuit connects the output terminal of i-th scale subtracter, and another input end connects the common parameter q output terminal of L+1 data storage cell; Obtained by i-th mould remainder circuit the output terminal of i-th mould remainder circuit connects the second data input pin of i-th data storage cell, by the data h that i-th mould remainder circuit obtains _ibe stored in i-th data storage cell of first memory as the second data.The output terminal of L mould remainder circuit connects each input end of L-scale adding circuit respectively; H is obtained by L-scale adding circuit ₁+ ... h _l;

(L+1) the-the first point multiplication circuit comprises L+1 the first dot product musical instruments used in a Buddhist or Taoist mass, wherein one of them input end of L+1 the first dot product musical instruments used in a Buddhist or Taoist mass connects the output terminal of L-scale adding circuit, another input end connects the common parameter basic point P output terminal of L+1 data storage cell, obtains Q=(h by L+1 the first dot product musical instruments used in a Buddhist or Taoist mass ₁+ ... h _l) P; L+1 the first dot product musical instruments used in a Buddhist or Taoist mass output terminal connects the 3rd data input pin of first memory L+1 data storage cell, by L+1 the result Q=(h that the first dot product musical instruments used in a Buddhist or Taoist mass exports ₁+ ... h _l) P is stored in L+1 data storage cell of first memory as the 3rd data; One of them input end of i-th the first dot product musical instruments used in a Buddhist or Taoist mass connects the second data output end of i-th data storage cell, and another input end connects the common parameter basic point P output terminal of L+1 data storage cell, exports h by i-th the first dot product musical instruments used in a Buddhist or Taoist mass _ip, i-th the first dot product musical instruments used in a Buddhist or Taoist mass output terminal connects the 4th data input pin of i-th data storage cell, by i-th the first dot product musical instruments used in a Buddhist or Taoist mass Output rusults h _ip is stored in i-th data storage cell as the 4th data.

L-second point mlultiplying circuit comprises L second point multiplier, and wherein one of them input end of i-th second point multiplier connects the slave C of i-th data storage cell _ithe PKI PK corresponding with between main equipment _ioutput terminal, another input end connects the digital signature y of the first telecommunication circuit _1ioutput terminal, obtains y by i-th second point multiplier _1ipK _i, i-th second point multiplier outputs connects the 5th data input pin of first memory i-th data storage cell, by the Output rusults y of i-th second point multiplier _1ipK _ibe stored in first memory i-th data storage cell as the 5th data; The output terminal of each second point multiplier connects L-point adding circuit respectively simultaneously; Q ' is got by L-point adding circuit:

$Q^{\′}=\underset{i=1}{\overset{L}{\mathrm{\Σ}}}{y}_{1i}{\mathrm{PK}}_i.$

Authentication output results contrast unit comprises L+1 NOR gate circuit, each NOR gate circuit output terminal is connected to not circuit, wherein one of them input end of L+1 NOR gate circuit connects the 3rd data output end of L+1 data storage cell, another input end connects the output terminal of L-point adding circuit in ECC algorithm circuit, inputs Q=(h respectively at two input ends of L+1 NOR gate circuit ₁+ ... h _l) P and Q '; One of them input end of i-th NOR gate circuit connects the 4th data output end of i-th data storage cell, another input end connects the 5th data output end of i-th data storage cell, inputs the 4th data h of first memory i-th data cell stores at two input ends of i-th NOR gate circuit respectively _ip and the 5th data y _1ipK _i.By i-th NOR gate circuit checking the 4th data h _ip and the 5th data y _1ipK _iwhether equal.

The not circuit that authentication output results contrast unit L+1 NOR gate circuit output terminal connects in the present embodiment connects the control end of 1 to L NOR gate circuit, the duty of 1 to L NOR gate circuit is controlled by L+1 NOR gate circuit, when the not circuit that L+1 NOR gate circuit output terminal connects exports as low level, namely, when Q and Q ' is unequal, triggers 1 to L NOR gate circuit and start working.

As shown in Figure 6, in the present embodiment, L-scale adding circuit comprises L-1 scale totalizer, wherein one of them input end of the 1st scale totalizer connects the output terminal of the 1st mould remainder circuit, another input end connects the 2nd mould remainder circuit output end, gets h by 1 scale totalizer ₁+ h ₂, xth one of them input end of scale totalizer connects xth-1 the first scale adder output, and another input end connects a (x+1)th mould remainder circuit output end, and wherein x ∈ [2, L-1], gets h by an xth scale totalizer ₁+ ... h _x+1.H is got eventually through L-1 scale totalizer ₁+ ... h _l.

As shown in Figure 6, the present embodiment L-point adding circuit comprises L-1 some totalizer, wherein one of them input end of the 1st some totalizer connects the output terminal of the 1st second point multiplier, and another input end connects the 2nd second point multiplier outputs, gets y by the 1st some totalizer ₁₁pK ₁+ y ₁₂pK ₂, xth one of them input end of some totalizer connects xth-1 first adder output, and another input end connects a (x+1)th second point multiplier outputs, wherein x ∈ [2, L-1], gets y by an xth point totalizer ₁₁pK ₁+ ... y _1x+1pK _x+1, get Q ' eventually through L-point adding circuit:

$Q^{\′}=\underset{i=1}{\overset{L}{\mathrm{\Σ}}}{y}_{1i}{\mathrm{PK}}_i.$

As shown in Figure 6, in the present embodiment, the number of random number generator is L, and wherein in the first pseudo-random function chip, i-th the first NOR gate circuit input end connects the output terminal of i-th random number generator.

The number of certain random number generator also can be one, and the random number generator that namely in the first pseudo-random function chip, each first NOR gate circuit input end connects is same.I.e. challenge information c ₁=c ₂=... ,=c _l=c, only substitutes L-digital random number generator with a digital random number generator.When all L slave data and mark all received by the first telecommunication circuit, last arrive slave data store complete, then trigger the operation of this digital random number generator, export a random integers c.First telecommunication circuit is to all L slave S ₁..., S _lbroadcast transmission c is as their challenge information.

The specific works process of the present embodiment authenticate device is as follows:

(1) the parameters for authentication setting procedure of main equipment: key generation system is selected according to main equipment and realized ECC algorithm circuit, obtains the Prime Orders q of basic point P on elliptic curve and correspondence thereof, distributes different private key sk to each slave _i, calculate corresponding PKI PK _i=sk _ip; Then, system common parameter (q, P) is stored in L+1 data storage cell of first memory, slave C _ipKI PK _istored in i-th data storage cell of storer, wherein i=1 ..., L.

(2) slave sends verify data process: according to COS and the properties of product of slave manufacturer configuration, at each slave C _ithe middle data D generating record slave current state _iand mark τ _i, (τ simultaneously _i, D _i) be kept at slave C _iin the second memory of the second certification integrated circuit.As slave C _iwhen loading main equipment, main equipment starts the certification to slave; Each slave C _ithe data D of record slave current state that will be stored in second memory by second communication circuit of the second memory of the second certification integrated circuit _iand mark τ _ibe sent in first telecommunication circuit of the first certification integrated circuit of main equipment.

(3) data read process of slave: the first certification integrated circuit of main equipment receives by the first telecommunication circuit the data that the second communication circuit from each slave sends, and by slave C _idata (the τ that corresponding second communication circuit sends _i, D _i) be kept in i-th data storage cell of the first memory of main equipment first certification integrated circuit, i=1 ..., L.

(4) the generation process of transmitting of main equipment challenge information: when the 1st data cell of first memory stores from slave C all respectively to L data cell ₁..., C _lrecord slave current state data and mark after, the operation of triggered digital random number generator.By the output terminal be connected with the first pseudo-random function chip with the first telecommunication circuit, i-th digital random number generator wherein in digital random number generator exports a random integers c _i, i=1 ..., L, the first telecommunication circuit is by c _islave C is sent to as challenge information _i, i=1 ..., L.

(5) slave receives challenge information and generates random shared key process: each slave receives the corresponding challenge information of main equipment first telecommunication circuit transmission by second communication circuit, slave C _ithe challenge information c that second NOR gate circuit of the second pseudo-random function chip of the second certification integrated circuit inputs according to second communication circuit _iwith the mark τ of second memory input _iexport encrypted cipher text then by the pseudo-random function of the second AES encryption algorithm chip based on symmetric encipherment algorithm AES utilize seed key K to binary character string be encrypted, export random shared key

(6) slave generates digital signature procedure: the output digital signing circuit of each slave second certification integrated circuit is according to the input random shared key from the second pseudo-random function chip module with the input (D from second memory _i, q, 1/sk _i), export signature y _1i.Particularly, each slave exports two be input to by exporting the second scale subtraction gate circuit of digital signing circuit with y _0i=D _idifference scalar multilication gate circuit is according to input with private key inverse element export the long-pending of them second mould remainder circuit exports input about the remainder y of mould q _1i, namely export corresponding data (τ _i, D _i) and challenge information c _idigital signature, wherein digital signature here

(7) slave sends response message process: the second certification integrated circuit of each slave using response message corresponding in current challenge-response authentication mode for digital signature, sends to the first telecommunication circuit of main equipment by second communication circuit by second communication circuit.

(8) generative process of main equipment shared key: the random integers c that i-th NOR gate circuit in the first pseudo-random function chip module transmits according to i-th random number generator in digital random number generator _i, from first memory, the data cell reads in corresponding slave C _idata Identification τ _i, export the XOR result of these two inputs then i-th AES encryption algorithm chip is based on the pseudo-random function of symmetric encipherment algorithm AES utilize symmetric key K to binary character string be encrypted, export slave C _ithe random shared key used in signature and will send i-th scale subtraction gate circuit of L-subtraction circuit in ECC algorithm circuit to, i=1 ..., L.

(9) scale difference and dot product computation process in ECC algorithm circuit:

(9-1) according to the random shared key that the first pseudo-random function chip transmits in ECC algorithm circuit, i-th scale subtracter of L-subtraction circuit, i-th data cell from first memory reads in corresponding slave C _idata D _i, export the difference of these two inputs i-th mould remainder circuit reads in common parameter q from L+1 data storage cell of first memory, according to this difference of input, exports the remainder of this difference about mould q by h _ias in the second data preservation in a first memory i-th data cell, its Output rusults is sent to each input end of L-scale adding circuit by each mould remainder circuit respectively simultaneously, obtains h by L-scale adding circuit ₁+ ... h _l.

(9-2) L+1 the first dot product musical instruments used in a Buddhist or Taoist mass of (L+1)-point multiplication circuit utilizes L-scale adding circuit Output rusults, reads common parameter basic point P, export result of calculation Q=(h from first memory L+1 data storage cell ₁+ ... h _l) P, and by Q=(h ₁+ ... h _l) P preserves in a first memory in L+1 data storage cell as the 3rd data.

(9-3) the point multiplication calculation process of the corresponding difference of each slave: (L+1)-the first point multiplication circuit i-th the first dot product musical instruments used in a Buddhist or Taoist mass reads the second data h from i-th data storage cell of first memory _i, read common parameter basic point P from L+1 data storage cell, export h by i-th the first dot product musical instruments used in a Buddhist or Taoist mass _ip, and will h be exported _ip is stored in i-th data storage cell as defeated 4th data of the 4th data.

(10) reception of main equipment response message and dot product computation process thereof:

(10-1) to slave C _isend challenge information c _iafter, main equipment receives the response message of each slave by the first telecommunication circuit.When the first telecommunication circuit receives L slave C ₁..., C _lresponse message (y ₁₁..., y _1L) after, it is sent to the ECC algorithm circuit module in the first certification integrated circuit.In ECC algorithm circuit module, L-second point mlultiplying circuit is according to input (y ₁₁..., y _1L) and slave PKI (PK ₁..., PK _l), export result of calculation (y ₁₁pK ₁..., y _1LpK _l) send first memory and L-point adding circuit to.Particularly, in ECC algorithm circuit L-second point mlultiplying circuit i-th second point multiplier according to input y _1icorresponding slave C is read in i-th data storage cell in first memory _ipKI PK _i, export result of calculation y _1ipK _i, and using it as in the 5th data preservation in a first memory i-th data storage cell, i=1 ..., L.The Output rusults of each second point multiplier is sent to each input end of L-point adding circuit respectively simultaneously.

(10-2) L-point adding circuit exports about L input y ₁₁pK ₁..., y _1LpK _lwith Q ',

$Q^{\′}=\underset{i=1}{\overset{L}{\mathrm{\Σ}}}{y}_{1i}{\mathrm{PK}}_i.$

(11) the overall verification process of slave: the Output rusults Q ' of authentication output results contrast unit L+1 NOR gate circuit to the middle ECC algorithm circuit L-point adding circuit of step (10-2) and the 3rd data xor operation of L+1 data storage cell reading from first memory, whether the Output rusults checking Q '=Q equation of the not circuit connected by L+1 NOR gate circuit output terminal is set up, not circuit exports high level, shows all response message (y of L slave ₁₁..., y _1L) be all effective, this L of main equipment certification slave is all effectively legal, completes current certification, and removes the temporary authentication data of preserving in first memory; Otherwise main equipment thinks that this L slave exists fake products, and operating procedure (12) searches personation slave wherein.

(12) personator's identification process of overall authentification failure is caused: the not circuit output low level connected when L+1 NOR gate circuit output terminal in the authentication output results contrast unit module in step (11), then triggering in authentication output results contrast unit module from the 1st NOR gate circuit to the operation of L NOR gate circuit, exporting about inputting ((h ₁p,y ₁₁pK ₁) ..., (h _lp,y _1LpK _l)) recognition result.Particularly, during i-th NOR gate circuit in authentication output results contrast unit module runs, from first memory, i-th data cell reads in the 4th data h _ip and the 5th data y _1ipK _i, i-th NOR gate circuit exports the XOR result of these two inputs to its output terminal not circuit, if the output of i-th not circuit is low level, this shows h _ip ≠ y _1ipK _i, corresponding data (τ _i, D _i) and response message y _1islave C _iinvalid, main equipment certification slave C _ifor fake products, refusal accepts; Otherwise, slave C _ieffective.According to triggering from the 1st not circuit to the Output rusults of L not circuit in authentication output results contrast unit module, identifiable design goes out to cause the personation slave of overall authentification failure, i=1 ..., L.

Claims (10)

1. main equipment is to an authenticate device for its slave, it is characterized in that, comprises key generation system, configures the first certification integrated circuit and the first telecommunication circuit in the host and be configured in slave C _iin the second certification integrated circuit and second communication circuit;

The first certification integrated circuit that described main equipment configures comprises first memory, digital random number generator, the first pseudo-random function chip, ECC (elliptic curve cipher) algorithm circuit and authentication output results contrast unit; First telecommunication circuit is connected with first memory, digital random number generator and ECC algorithm circuit respectively; First memory is connected with the first pseudo-random function chip, ECC algorithm circuit and authentication output results contrast unit respectively; The output terminal of digital random number generator is connected with the first pseudo-random function chip; The output terminal of described first pseudo-random function chip connects the input end of ECC algorithm circuit, and the output terminal of described ECC algorithm circuit connects the input end of authentication output results contrast unit;

The the second certification integrated circuit configured in described slave comprises

Second memory, the second pseudo-random function chip and output digital signing circuit; Second communication circuit is respectively with second memory, the second pseudo-random function chip with export digital signing circuit and be connected, second memory is respectively with the second pseudo-random function chip with exports digital signing circuit and is connected, the output terminal connection output digital signing circuit of the second pseudo-random function chip;

Described key generation system is connected with first memory and second memory respectively, and the first telecommunication circuit is connected by network with the second logical unit.

2. main equipment according to claim 1 is to the authenticate device of its slave, it is characterized in that, the first memory in main equipment first certification integrated circuit stores the common parameter (q, P) of elliptic curve cryptography, slave C _ithe PKI PK corresponding with between main equipment _iand record slave C _ithe data D of current state _iand mark τ _i; First memory comprises common parameter basic point P output terminal, common parameter q output terminal, slave C _ithe PKI PK corresponding with between main equipment _ithe data D of output terminal, record slave current state _iinput end and output terminal and data D _imark τ _iinput end and output terminal;

Second memory in slave second certification integrated circuit stores the common parameter q of elliptic curve cryptography, slave C _ithe inverse element 1/sk of private key _ioutput terminal, second memory comprises the private key inverse element 1/sk of common parameter q output terminal, slave _ithe mark output terminal of output terminal, slave status data output terminal and slave status data;

First telecommunication circuit and second communication circuit include record slave C _ithe data D of current state _iinput end and output terminal, data D _imark τ _iinput end and output terminal, digital signature y _1iinput end and output terminal and challenge information c _iinput end and output terminal;

The record slave C of the first telecommunication circuit _ithe data D of current state _iinput end connects the record slave C of second communication circuit by networking _ithe data D of current state _ioutput terminal, the data D of the first telecommunication circuit _imark τ _iinput end connects the data D of second communication circuit by networking _imark τ _ioutput terminal; First telecommunication circuit from digital signature y _1iinput end connects the digital signature y of second communication circuit by networking _1ioutput terminal; The challenge information c of the first telecommunication circuit _ioutput terminal is by the challenge information c of networking and second communication circuit _iinput end connects;

The challenge information c of the first telecommunication circuit _iinput end connects random number generator output terminal, the digital signature output terminal y of the first telecommunication circuit _1ibe connected with ECC algorithm circuit, the record slave C of the first telecommunication circuit _ithe data D of current state _ithe data D of the record slave current state of output terminal and first memory _iinput end connects, the data D of the first telecommunication circuit _imark τ _ithe data D of output terminal and first memory _imark τ _iinput end connects;

The challenge information c of second communication circuit _ioutput terminal is connected with the second pseudo-random function chip; The digital signature y of second communication circuit _1iinput end is connected with output digital signing circuit output terminal; The record slave C of second communication circuit _ithe data D of current state _iinput end connects the record slave C of second memory _ithe data D of current state _ioutput terminal; The data D of second communication circuit _imark τ _iinput end connects the data D of second memory _imark τ _ioutput terminal.

3. main equipment according to claim 2 is to the authenticate device of its slave, it is characterized in that,

Authenticate device comprises one and is configured in slave C _iin the second certification integrated circuit, the number of the slave that authentication authorization and accounting device will authenticate is one;

The first pseudo-random function chip internal in main equipment first certification integrated circuit is embedded with seed key K, the first NOR gate circuit and the first AES encryption algorithm chip, the data D of one of them input end of the first NOR gate circuit and first memory _imark τ _ioutput terminal connects, the mark of the corresponding slave current status data stored in input first memory, and another input end is connected with random number generator, the random number c as corresponding slave challenge information that input random number generator generates _i; One of them input end of described first AES encryption algorithm chip is connected with the output terminal of the first NOR gate circuit, another input end input seed key K, and the output terminal of the first AES encryption algorithm chip connects ECC algorithm circuit;

In main equipment first certification integrated circuit, ECC algorithm circuit comprises the first scale subtraction gate circuit, the first mould remainder circuit, the first dot product musical instruments used in a Buddhist or Taoist mass and second point multiplier;

The output terminal that first scale subtraction gate circuit minuend input end connects the first AES encryption algorithm chip in the first pseudo-random function core connects, and described first scale subtraction gate circuit subtracting input connects the record slave C of first memory _ithe data D of current state _ioutput terminal, the corresponding slave C of the record stored in input first memory _ithe data D of current state _i;

The output terminal of the first scale subtraction gate circuit connects one of them input end of the first mould remainder circuit; Another input end of first mould remainder circuit connects the common parameter q output terminal of first memory;

The output terminal of the first mould remainder circuit connects one of them input end of the first dot product musical instruments used in a Buddhist or Taoist mass; Another input end of first dot product musical instruments used in a Buddhist or Taoist mass connects the basic point P output terminal of the common parameter of first memory; The output terminal of the first dot product musical instruments used in a Buddhist or Taoist mass connects the first data input pin of first memory;

One of them input end of second point multiplier connects the slave C of first memory _ithe PKI PK corresponding with between main equipment _ioutput terminal, inputs and to be generated by key generation system and by the corresponding slave private key sk stored in first memory _ipKI PK corresponding in the host _i; Another input end of second point multiplier connects the digital signature y of the first telecommunication circuit _1ioutput terminal; The output terminal of second point multiplier connects the input end of authentication output results contrast unit;

The not circuit that described authentication output results contrast unit comprises NOR gate circuit and is connected with NOR gate circuit output terminal; One of them input end of NOR gate circuit connects the first data output end of first memory; Another input end of NOR gate circuit connects the output terminal of second point multiplier.

4. main equipment according to claim 2 is to the authenticate device of its slave, it is characterized in that, described authenticate device comprises L and is configured in each slave C respectively _iin the second certification integrated circuit, the number of the slave that authentication authorization and accounting device will authenticate is L, wherein i ∈ [1, L];

First memory comprises L+1 data storage cell, i-th data cell stores slave C _ithe PKI PK corresponding with between main equipment _i, record slave C _ithe data D of current state _iand mark τ _i, the common parameter (q, P) of L+1 data cell stores elliptic curve cryptography;

First pseudo-random function chip internal is embedded with the chip of seed key K, a L the first NOR gate circuit and L AES encryption algorithm, the record slave C of i-th data storage cell wherein in i-th one of them input end of the first NOR gate circuit connection first memory _ithe data D of current state _ioutput terminal, another input end is connected with random number generator, and one of them input end of i-th the first AES encryption algorithm chip is connected with the output terminal of i-th the first NOR gate circuit, another input end input seed key K;

ECC algorithm circuit comprises a L-subtraction circuit, a L-scale adding circuit, one (L+1)-the first point multiplication circuit, a L-point adding circuit and a L-second point mlultiplying circuit;

L-subtraction circuit comprises L scale subtracter and L mould remainder circuit, wherein one of them input end of i-th scale subtracter connects i-th the first AES encryption algorithm chip output terminal, and another input end connects the record slave C of i-th data storage cell _ithe data D of current state _i, one of them input end of i-th mould remainder circuit connects the output terminal of i-th scale subtracter, and another input end connects the common parameter q output terminal of L+1 data storage cell; The output terminal of L mould remainder circuit connects each input end of L-scale adding circuit respectively; The output terminal of i-th mould remainder circuit connects the second data input pin of i-th data storage cell;

(L+1) the-the first point multiplication circuit comprises L+1 the first dot product musical instruments used in a Buddhist or Taoist mass, wherein one of them input end of L+1 the first dot product musical instruments used in a Buddhist or Taoist mass connects the output terminal of L-scale adding circuit, another input end connects the common parameter basic point P output terminal of L+1 data storage cell, and output terminal connects the 3rd data input pin of L+1 data storage cell; One of them input end of i-th the first dot product musical instruments used in a Buddhist or Taoist mass connects the second data output end of i-th data storage cell, another input end connects the common parameter basic point P output terminal of L+1 data storage cell, and output terminal connects the 4th data input pin of i-th data storage cell;

L-second point mlultiplying circuit comprises L second point multiplier, and wherein one of them input end of i-th second point multiplier connects the slave C of i-th data storage cell _ithe PKI PK corresponding with between main equipment _ioutput terminal, another input end connects the digital signature y of the first telecommunication circuit _1ioutput terminal, output terminal connects the 5th data input pin of i-th data storage cell; The output terminal of each second point multiplier connects L-point adding circuit respectively simultaneously;

Authentication output results contrast unit comprises L+1 NOR gate circuit, each NOR gate circuit output terminal is connected to not circuit, wherein one of them input end of L+1 NOR gate circuit connects the 3rd data output end of L+1 data storage cell, and another input end connects the output terminal of L-point adding circuit in ECC algorithm circuit; One of them input end of i-th NOR gate circuit connects the 4th data output end of i-th data storage cell, and another input end connects the 5th data output end of i-th data storage cell.

5. main equipment according to claim 4 is to the authenticate device of its slave, it is characterized in that,

Described L-scale adding circuit comprises L-1 scale totalizer, wherein one of them input end of the 1st scale totalizer connects the output terminal of the 1st mould remainder circuit, another input end connects the 2nd mould remainder circuit output end, xth one of them input end of scale totalizer connects xth-1 the first scale adder output, another input end connects a (x+1)th mould remainder circuit output end, wherein x ∈ [2, L-1].

6. main equipment according to claim 4 is to the authenticate device of its slave, it is characterized in that,

Described L-point adding circuit comprises L-1 some totalizer, wherein one of them input end of the 1st some totalizer connects the output terminal of the 1st second point multiplier, another input end connects the 2nd second point multiplier outputs, xth one of them input end of some totalizer connects xth-1 first adder output, another input end connects a (x+1)th second point multiplier outputs, wherein x ∈ [2, L-1].

7. main equipment according to claim 4 is to the authenticate device of its slave, it is characterized in that, the number of described random number generator is one, and the random number generator that in the first pseudo-random function chip, each first NOR gate circuit input end connects is same.

8. main equipment according to claim 4 is to the authenticate device of its slave, it is characterized in that, the number of described random number generator is L, and in the first pseudo-random function chip, i-th the first NOR gate circuit input end connects the output terminal of i-th random number generator.

9. main equipment according to claim 2 is to the authenticate device of its slave, it is characterized in that, slave C _isecond pseudo-random function chip internal of the second certification integrated circuit is embedded with seed key K, the second NOR gate circuit and the second AES encryption algorithm chip, the data D of one of them input end of the second NOR gate circuit and second memory _imark τ _ioutput terminal connects, the challenge information c of another input end and second communication circuit _ioutput terminal connects; One of them input end of described second AES encryption algorithm chip is connected with the output terminal of the second NOR gate circuit, and another input end input seed key K, the output terminal of the second AES encryption algorithm chip connects the input end exporting digital signing circuit.

10. main equipment according to claim 9 is to the authenticate device of its slave, it is characterized in that, the output digital signing circuit in described slave second certification integrated circuit comprises the second scale subtraction gate circuit, scalar multilication gate circuit and the second mould remainder circuit;

The minuend input end of the second scale subtraction gate circuit connects the output terminal of the second AES encryption algorithm chip, and subtracting input connects the data D of second memory _imark τ _ioutput terminal connects;

One of them input end of second scalar multilication gate circuit connects the output terminal of subtraction gate circuit, and another input end connects the slave C of second memory _ithe inverse element 1sk of private key _ioutput terminal;

One of them input end of second mould remainder circuit connects the output terminal of the second scalar multilication gate circuit, and another input end connects the common parameter q output terminal of second memory; The output terminal of the second mould remainder circuit, as the output terminal exporting digital signing circuit, is connected with the digital signature input end of second communication unit in slave second certification integrated circuit.