CN204314650U - A kind of digital galactophore owner control circuit - Google Patents
A kind of digital galactophore owner control circuit Download PDFInfo
- Publication number
- CN204314650U CN204314650U CN201420390447.XU CN201420390447U CN204314650U CN 204314650 U CN204314650 U CN 204314650U CN 201420390447 U CN201420390447 U CN 201420390447U CN 204314650 U CN204314650 U CN 204314650U
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- China
- Prior art keywords
- chip
- connects
- operational amplifier
- utility
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000001228 spectrum Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 29
- 230000008901 benefit Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 1
Classifications
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- Y02P90/265—
Landscapes
- Regulating Braking Force (AREA)
Abstract
The utility model discloses a kind of digital galactophore owner control circuit, comprise one first chip, it connects the 5th chip that carries out digital independent and storage, described first chip connects the 6th chip that carries out AEC control, described first chip connects one and controls the 7th chip of filament, and described first chip also connects and carries out pressure controlled 8th chip.The utility model proposes the design of a kind of new governor circuit, one piece of circuit board is integrated with the functions such as spectrum assignment, grid control, the control of rim brake backpedalling brake, flat panel detector control, thus reduces machine volume, and reduce complete machine cost.
Description
Technical field
The utility model relates to a kind of governor circuit, more precisely a kind of digital galactophore owner control circuit.
Background technology
Current digital galactophore machine often inside a system containing polylith control chip, perform different functions, as controlled exposure, controlling the vibration of grid, controlling flat panel detector etc.Such design causes system bus communication busy, and peak period often there will be conflict, and is unfavorable for controlling complete machine cost.
Utility model content
The purpose of this utility model is to provide a kind of digital galactophore owner control circuit, and it can solve the above-mentioned shortcoming that prior art is produced.
The utility model is by the following technical solutions:
A kind of digital galactophore owner control circuit, comprise one first chip, it connects the 5th chip that carries out digital independent and storage, described first chip connects the 6th chip that carries out AEC control, described first chip connects one and controls the 7th chip of filament, and described first chip also connects and carries out pressure controlled 8th chip.
Also comprise one the 91 operational amplifier, the output terminal of described 91 operational amplifier connects the other end ground connection of described two or five electric capacity of one the 25 electric capacity, two ends one the 26 electric capacity in parallel of described two or five electric capacity, the reverse input end of described 91 operational amplifier connects its output terminal, the input end in the same way of described 91 operational amplifier connects the output terminal of one the 92 operational amplifier, the output terminal of described 92 operational amplifier, the positive source of described 92 operational amplifier connects the direct current of a 12V, and the power cathode ground connection of described 92 operational amplifier, also comprise the first potentiometer, one end series connection one the 1 resistance and the one or two resistance of described potentiometer, the other end ground connection of described one or two resistance, the positive source of described 92 operational amplifier and connect one the 1 resistance between input end in the same way, the input end in the same way of described 92 operational amplifier also connects the output terminal of one the 1 diode, the output head grounding of described one one diode.
The utility model has the advantages that: the utility model proposes the design of a kind of new governor circuit, one piece of circuit board is integrated with the functions such as spectrum assignment, grid control, the control of rim brake backpedalling brake, flat panel detector control, thus reduce machine volume, and reduce complete machine cost.
Accompanying drawing explanation
Below in conjunction with embodiment and accompanying drawing, the utility model is described in detail, wherein:
Fig. 1 is the circuit diagram of the first chip of the present utility model.
Fig. 2 is the circuit diagram of the second chip of the present utility model.
Fig. 3 is the circuit diagram of the 3rd chip of the present utility model.
Fig. 4 is the circuit diagram of the 4th chip of the present utility model.
Fig. 5 is the circuit diagram of the 5th chip of the present utility model.
Fig. 6 is the circuit diagram of the 6th chip of the present utility model.
Fig. 7 is the circuit diagram of the 7th and eight chips of the present utility model.
Fig. 8 is the circuit diagram of the 9th chip of the present utility model.
Fig. 9 is the circuit diagram of the tenth chip of the present utility model.
Figure 10 is the circuit diagram of twelve-core sheet of the present utility model.
Figure 11 is the circuit diagram of the 13 chip of the present utility model.
Figure 12 is the circuit diagram of the 14 chip of the present utility model.
Figure 13 is the circuit diagram of the 15 chip of the present utility model.
Figure 14 is the circuit diagram of the 16 chip of the present utility model.
Figure 15 is the circuit diagram of the 17 chip of the present utility model.
Figure 16 is the circuit diagram of the 18 chip of the present utility model.
Figure 17,18 is circuit diagrams of the 19 chip of the present utility model.
Figure 19 is the circuit diagram of 20,21 and two twelve-core sheets of the present utility model.
Figure 20 is the circuit diagram of the 23 chip of the present utility model.
Figure 21 is the circuit diagram of the 24 chip of the present utility model.
Figure 22 is the circuit diagram of the 26 chip of the present utility model.
Figure 23 is the circuit diagram of the 27 chip of the present utility model.
Figure 24 is the circuit diagram of the 28 chip of the present utility model.
Figure 25 is the circuit diagram of CN10 of the present utility model.
Figure 26 is the circuit diagram of CN12 of the present utility model.
Figure 27 is the circuit diagram of CN13 of the present utility model.
Figure 28 is the circuit diagram of PC4 of the present utility model.
Figure 29 is the circuit diagram of PC1 of the present utility model.
Figure 30 is the circuit diagram of PC2 of the present utility model.
Embodiment
Embodiment of the present utility model is set forth further below in conjunction with accompanying drawing:
As shown in the figure, a kind of digital galactophore owner control circuit, comprise one first chip U1, it connects the 5th chip U5 that carries out digital independent and storage, described first chip connects a 6th chip U6 carrying out AEC control, and described first chip connects the 7th chip U7 that controls filament, and described first chip also connects and carries out pressure controlled 8th chip U8.
The utility model also comprises one the 91 operational amplifier U9A, the output terminal of described 91 operational amplifier connects the other end ground connection of described two or five electric capacity of one the 25 electric capacity C25, two ends one the 26 electric capacity C26 in parallel of described two or five electric capacity, the reverse input end of described 91 operational amplifier connects its output terminal, the input end in the same way of described 91 operational amplifier connects the output terminal of one the 92 operational amplifier U9B, the output terminal of described 92 operational amplifier, the positive source of described 92 operational amplifier connects the direct current of a 12V, and the power cathode ground connection of described 92 operational amplifier, also comprise the first potentiometer VR1, one end series connection one the 1 resistance R11 and the one or two resistance R12 of described potentiometer, the other end ground connection of described one or two resistance, the positive source of described 92 operational amplifier and connect one the 1 resistance R14 between input end in the same way, the input end in the same way of described 92 operational amplifier also connects the output terminal of one the 1 diode Q112, the output head grounding of described one one diode.
The model of the first chip is ATMEGA2560.
U1, as the core control portions of whole circuit, carries out digital independent and storage by U5, is realized the control of AEC by U6, the control of filament is realized by U7, realized the control of kV by U8, realized and the information interaction in flat panel detector and the external world by serial ports, and there is the functions such as key scan.
The utility model proposes the design of a kind of new governor circuit, one piece of circuit board is integrated with the functions such as spectrum assignment, grid control, the control of rim brake backpedalling brake, flat panel detector control, thus reduces machine volume, and reduce complete machine cost.
This technology to be applied in the novel digital galactophore machine system of my company and to have introduced to the market, and this circuit working is reliable and stable in actual applications, achieves good economic benefit.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all do within spirit of the present utility model and principle any amendment, equivalent to replace and improvement etc., all should be included within protection domain of the present utility model.
Claims (2)
1. a digital galactophore owner control circuit, it is characterized in that, comprise one first chip, it connects the 5th chip that carries out digital independent and storage, described first chip connects the 6th chip that carries out AEC control, described first chip connects one and controls the 7th chip of filament, and described first chip also connects and carries out pressure controlled 8th chip.
2. digital galactophore owner control circuit according to claim 1, it is characterized in that, also comprise one the 91 operational amplifier, the output terminal of described 91 operational amplifier connects the other end ground connection of described two or five electric capacity of one the 25 electric capacity, two ends one the 26 electric capacity in parallel of described two or five electric capacity, the reverse input end of described 91 operational amplifier connects its output terminal, the input end in the same way of described 91 operational amplifier connects the output terminal of one the 92 operational amplifier, the output terminal of described 92 operational amplifier, the positive source of described 92 operational amplifier connects the direct current of a 12V, and the power cathode ground connection of described 92 operational amplifier, also comprise the first potentiometer, one end series connection one the 1 resistance and the one or two resistance of described potentiometer, the other end ground connection of described one or two resistance, the positive source of described 92 operational amplifier and connect one the 1 resistance between input end in the same way, the input end in the same way of described 92 operational amplifier also connects the output terminal of one the 1 diode, the output head grounding of described one one diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420390447.XU CN204314650U (en) | 2014-07-15 | 2014-07-15 | A kind of digital galactophore owner control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420390447.XU CN204314650U (en) | 2014-07-15 | 2014-07-15 | A kind of digital galactophore owner control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204314650U true CN204314650U (en) | 2015-05-06 |
Family
ID=53136955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420390447.XU Expired - Lifetime CN204314650U (en) | 2014-07-15 | 2014-07-15 | A kind of digital galactophore owner control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204314650U (en) |
-
2014
- 2014-07-15 CN CN201420390447.XU patent/CN204314650U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210907 Address after: 315832 Room 101, first floor, zone a, No. 88, Kangda Road, Meishan free trade port, Ningbo, Zhejiang Patentee after: Kangda Intercontinental Medical Devices Co.,Ltd. Address before: 201318 floor 2, building 5, No. 3377, Kangxin Road, Pudong New Area, Shanghai Patentee before: SHANGHAI KANGDA MEDICAL SCIENCE & TECHNOLOGY Co.,Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20150506 |