CN204302728U - Analog input card - Google Patents
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- CN204302728U CN204302728U CN201420821148.7U CN201420821148U CN204302728U CN 204302728 U CN204302728 U CN 204302728U CN 201420821148 U CN201420821148 U CN 201420821148U CN 204302728 U CN204302728 U CN 204302728U
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Abstract
The utility model discloses a kind of analog input card, comprising: high voltage isolated power supply circuit, High Pressure Difference divisional processing circuit, isolation Acquisition Circuit, low-voltage signal treatment circuit, processor, controller local area network drive circuit.Analog input card of the present utility model passes through High Pressure Difference divisional processing circuit realiration to the collection of external equipment high-voltage signal, and the high-voltage signal collected is carried out step-down, by isolation Acquisition Circuit isolated high-voltage difference processing circuit and low-voltage signal treatment circuit, thus the high-voltage signal avoiding external equipment is to the strong jamming of rear portion circuit, improve the stability of whole analog input card, analog input card reliability of the present utility model is high, and antijamming capability is strong.
Description
Technical field
The utility model relates to field of track traffic, particularly relates to analog input card.
Background technology
In the control system of train network, need to gather electric current, the voltage analog of external equipment, then be transformed to digital quantity and carry out subsequent treatment, wherein, analog input card is the important component part of remote input output module, is responsible for the Gather and input of analog quantity.
At present, the analog input card of the network control system of Train gathers the voltage of external equipment generally all between 0-15V, cannot meet the demand that other countries' high voltage gathers.
Utility model content
The utility model provides a kind of analog input card, cannot meet the problem of high voltage collection in order to solve analog input card of the prior art.
The utility model provides a kind of analog input card, comprising: high voltage isolated power supply circuit, High Pressure Difference divisional processing circuit, isolation Acquisition Circuit, low-voltage signal treatment circuit, processor, controller local area network drive circuit;
The output of described high voltage isolated power supply circuit is connected with the energization input of described High Pressure Difference divisional processing circuit, and described high voltage isolated power supply is used for powering to described High Pressure Difference divisional processing circuit;
The output of described High Pressure Difference divisional processing circuit is connected with the input of described isolation Acquisition Circuit, described High Pressure Difference divisional processing circuit is used for carrying out step-down to the high voltage analog signal of the external equipment collected, generate the first low-voltage analog signal, and export described first low-voltage analog signal to described isolation Acquisition Circuit;
The output of described isolation Acquisition Circuit is connected with the input of described low-voltage signal treatment circuit, described isolation Acquisition Circuit is for isolating described High Pressure Difference divisional processing circuit and described low-voltage signal treatment circuit, and linear process is carried out to described first low-voltage analog signal, generate the second low-voltage analog signal, export to described low-voltage signal treatment circuit;
The output of described low-voltage signal treatment circuit is connected with the input of described processor, described low-voltage signal treatment circuit is for reducing described second low-voltage analog signal, generate the 3rd low-voltage analog signal, meet the input voltage of processor to make described 3rd low-voltage analog signal;
The output of described processor is connected with the input of described controller local area network drive circuit, described processor is for receiving described 3rd low-voltage analog signal, generate standardized digital signal, and described standardized digital signal is delivered to controller local area network drive circuit;
The output of described controller local area network drive circuit is connected with Controller Area Network BUS.
Analog input card as above, preferably, described high voltage isolated power supply circuit comprises: the first resistance, the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the first control chip, the 6th electric capacity and the first counnter attack diode;
Between the first input end that described first resistance, the first electric capacity, the second electric capacity, the 3rd Capacitance parallel connection are arranged on described high voltage isolated power supply circuit and the second input;
The first end of described 4th electric capacity is connected between described second electric capacity and described 3rd electric capacity, second end of described 4th electric capacity is connected with the first end of described 5th electric capacity, and the second end of described 5th electric capacity is connected between described second electric capacity and described 3rd electric capacity;
The first end of described 4th electric capacity is connected with the first input end of described first control chip, and the second end of described 5th electric capacity is connected with the second input of described first control chip;
Between the first output that described 6th electric capacity and described first counnter attack diodes in parallel are arranged on described first control chip and the second output;
Described first counnter attack diode is connected with the energization input of described High Pressure Difference divisional processing circuit, the impact that described first counnter attack diode produces the energization input of described High Pressure Difference divisional processing circuit for Anti-surging and voltage jump.
Analog input card as above, preferably, described High Pressure Difference divisional processing circuit comprises: the second resistance, the first operational amplifier, the 3rd resistance, the second operational amplifier, the 4th resistance, the 3rd operational amplifier, the 5th resistance, the 6th resistance, four-operational amplifier, the 7th resistance;
The first input end of described High Pressure Difference divisional processing circuit is connected with the in-phase input end of described first operational amplifier by described second resistance, the output of described first operational amplifier is connected with the inverting input of described second operational amplifier by described 3rd resistance, the output of described second operational amplifier is connected with the in-phase input end of described 3rd operational amplifier by described 4th resistance, and the output of described 3rd operational amplifier is connected with the input of described isolation Acquisition Circuit by described 5th resistance;
Described second operational amplifier also comprises the first feedback resistance, and the two ends of described first feedback resistance connect inverting input and the output of described second operational amplifier respectively;
Second input of described High Pressure Difference divisional processing circuit is connected with the in-phase input end of described four-operational amplifier by the 6th resistance, and the output of described four-operational amplifier is connected with the in-phase input end of described second operational amplifier by the 7th resistance.
Analog input card as above, preferably, is also provided with the second counnter attack diode, the 8th resistance and the 9th resistance between the first input end of described High Pressure Difference divisional processing circuit and the second input;
Described second counnter attack diode, for preventing the voltage gathering external equipment excessive, produces voltge surge to the input of described High Pressure Difference divisional processing circuit;
The first end of described 8th resistance is connected with the first input end of described High Pressure Difference divisional processing circuit, second end of described 8th resistance is connected with the first end of described 9th resistance, and the second end of described 9th resistance is connected with the second input of described High Pressure Difference divisional processing circuit;
The 7th electric capacity is provided with between second end of described 8th resistance and the second end of described second resistance, the first end of described 7th electric capacity is connected with the second end of described second resistance, second end ground connection of described 7th electric capacity, the second end of described 8th resistance is connected with the second end of described 7th electric capacity.
Analog input card as above, preferably, described isolation Acquisition Circuit comprises the 5th operational amplifier, the second control chip, the tenth resistance, the 8th electric capacity, the 6th operational amplifier;
The inverting input of described 5th operational amplifier is connected with the first input end of described second control chip, the output of described 5th operational amplifier is connected with the second input of described second control chip by described tenth resistance, the 8th electric capacity is provided with between the inverting input of described 5th operational amplifier and the output of described 5th operational amplifier, between the inverting input that the first end of described 8th electric capacity is connected to described 5th operational amplifier and the first input end of described second control chip, second end of described 8th electric capacity is connected between the output of described 5th operational amplifier and described tenth resistance,
First output of described second control chip is connected with the inverting input of described 6th operational amplifier, second output of described second control chip is connected with the in-phase input end of described 6th operational amplifier, and the output of described 6th operational amplifier is connected with the input of described low-voltage signal treatment circuit;
Described 6th operational amplifier also comprises the second feedback resistance and the 9th electric capacity, described second feedback resistance and described 9th electric capacity parallel with one another, between the anti-phase defeated input being connected to described 6th operational amplifier and output.
Analog input card as above, preferably, described low-voltage signal treatment circuit comprises the 7th operational amplifier, the 11 resistance, the 12 resistance, the 13 resistance, the 14 resistance and the 8th operational amplifier;
The inverting input of described 7th operational amplifier is connected with the output of described 6th operational amplifier by described 11 resistance, the in-phase input end of described 7th operational amplifier is connected to ground by described 12 resistance, and the output of described 7th operational amplifier is connected with the inverting input of described 8th operational amplifier by described 13 resistance;
The in-phase input end of described 8th operational amplifier is connected to ground by described 14 resistance, and the output of described 8th operational amplifier is connected with described processor;
Described 7th operational amplifier also comprises the 3rd feedback resistance and the tenth electric capacity, described 3rd feedback resistance and the tenth electric capacity parallel with one another, between the inverting input being connected to described 7th operational amplifier and output;
Described 8th operational amplifier also comprises the 4th feedback capacity, and the two ends of described 4th feedback capacity are connected with the inverting input of described 8th operational amplifier and output respectively.
Analog input card as above, preferably, described processor comprises STM32F103 single-chip microcomputer and controller local area network protocol integrated test system chip.
Analog input card as above, preferably, described second control chip is linear optical coupling element.
The analog input card that the utility model provides, by High Pressure Difference divisional processing circuit realiration to the collection of external equipment high-voltage signal, and the high-voltage signal collected is carried out step-down, further by isolation Acquisition Circuit isolated high-voltage difference processing circuit and low-voltage signal treatment circuit, thus the high-voltage signal avoiding external equipment is to the strong jamming of rear portion circuit, improve the stability of whole analog input card, the utility model is also processed the signal that isolation Acquisition Circuit exports by low-voltage signal treatment circuit, thus the signal making isolation Acquisition Circuit export meets the input voltage condition of processor, digital-to-analogue conversion is carried out further by processor, generate the data meeting controller local area network agreement and specify, and these data are delivered to Controller Area Network BUS, finally achieve the collection of high-precision analog input.Analog input card reliability of the present utility model is high, and antijamming capability is strong.
Accompanying drawing explanation
The structural representation of the analog output card that Fig. 1 provides for the utility model embodiment one;
The structural representation of the high voltage isolated power supply circuit that Fig. 2 provides for the utility model embodiment two;
The structural representation of the High Pressure Difference divisional processing circuit that Fig. 3 provides for the utility model embodiment two;
The structural representation of the isolation Acquisition Circuit that Fig. 4 provides for the utility model embodiment two;
The structural representation of the low-voltage signal treatment circuit that Fig. 5 provides for the utility model embodiment two;
The schematic flow sheet of the analog output method that Fig. 6 provides for the utility model embodiment three.
Detailed description of the invention
Embodiment one
The structural representation of the analog output card that Fig. 1 provides for the utility model embodiment one.As shown in Figure 1, the utility model provides a kind of analog input card to comprise: high voltage isolated power supply circuit 1, High Pressure Difference divisional processing circuit 2, isolation Acquisition Circuit 3, low-voltage signal treatment circuit 4, processor 5, controller local area network drive circuit 6.
Wherein, the output of high voltage isolated power supply circuit 1 is connected with the energization input of High Pressure Difference divisional processing circuit 2, and high voltage isolated power supply 1 is for powering to High Pressure Difference divisional processing circuit 2.
The output of High Pressure Difference divisional processing circuit 2 is connected with the input of isolation Acquisition Circuit 3, High Pressure Difference divisional processing circuit 2 generates the first low-voltage analog signal for carrying out step-down to the high voltage analog signal of the external equipment collected, and exports described first low-voltage analog signal to described isolation Acquisition Circuit.Particularly, the high-voltage signal of this external equipment collected is the voltage of 0-74V, and exporting the first low-voltage analog signal after the step-down of High Pressure Difference divisional processing circuit 2 is 0-10V voltage signal.
Because the high-voltage signal of the external equipment gathered can bring strong jamming to affect the work of rear portion circuit, therefore, have employed the isolation that isolation Acquisition Circuit 3 realizes High Pressure Difference divisional processing circuit 2 and low-voltage signal treatment circuit 4, the signal in low-voltage signal treatment circuit 4 is made not to be subject to the interference of the signal in High Pressure Difference divisional processing circuit 2, simultaneously, also the impact of high pressure for processor 5 can be eliminated, ensure that analog input card rear end and high voltage input terminal are without electrical connection, thus strengthen the stability of analog input card.
Concrete, the output of isolation Acquisition Circuit 3 is connected with the input of low-voltage signal treatment circuit 4, isolation Acquisition Circuit 3 is for isolated high-voltage difference processing circuit 3 and low-voltage signal treatment circuit 4, and linear process is carried out to the first low-voltage analog signal, generate the second low-voltage analog signal, export to low-voltage signal treatment circuit 4, wherein, isolation Acquisition Circuit 3 can adopt linear element, namely ensure between the first low-voltage analog signal and the second low-voltage analog signal linear, optionally, the first low-voltage analog signal is equal with the second low-voltage analog signal.
In order to meet the input voltage condition of processor 5, need to utilize the output voltage of low-voltage signal treatment circuit 4 to isolation Acquisition Circuit 3 to carry out step-down process further.
Concrete, the output of low-voltage signal treatment circuit 4 is connected with the input of processor 5, low-voltage signal treatment circuit 4 is for reducing the second low-voltage analog signal, generate the 3rd low-voltage analog signal, with the input voltage making the 3rd low-voltage analog signal meet processor 5, concrete, the 3rd low-voltage analog signal is the voltage signal of 0-2.5V, further, the 3rd low-voltage analog signal is inputed to processor 5 and carry out analog-to-digital conversion.
The output of processor 5 is connected with the input of controller local area network drive circuit 6, and processor 5, for receiving the 3rd low-voltage analog signal, generates standardized digital signal, and this standardized digital signal is delivered to controller local area network drive circuit.Wherein standardized digital signal refers to the data meeting controller local area network agreement and specify.The signal resolution of processor 5 also for being sent by controller local area network drive circuit 6 becomes standardized digital signal, is stored in the buffer area of self, reads for controller.For example, processor 5 can comprise STM32F103 single-chip microcomputer and controller local area network protocol integrated test system chip, and STM32F103 single-chip microcomputer is responsible for the work schedule of control controller local area network protocol integrated test system chip and is carried out the mutual of data with external system.
The output of controller local area network drive circuit 6 is connected with Controller Area Network BUS.For example, controller local area network drive circuit 6 comprises bus transceiver, and processor 5 is met what export the bus that controller local area network agreement specified standard data signal is delivered to controller local area network by bus transceiver.
From above technical scheme, analog input card of the present utility model realizes the collection to external equipment high-voltage signal by High Pressure Difference divisional processing circuit 1, and the high-voltage signal collected is carried out step-down, further by isolation Acquisition Circuit 3 isolated high-voltage difference processing circuit 2 and low-voltage signal treatment circuit 4, thus the high-voltage signal avoiding external equipment is to the strong jamming of rear portion circuit, improve the stability of whole analog input card, the utility model is also processed the signal that isolation Acquisition Circuit 3 exports by low-voltage signal treatment circuit 4, thus the signal making isolation Acquisition Circuit 3 export meets the input voltage condition of processor 5, digital-to-analogue conversion is carried out further by processor 5, generate the data meeting controller local area network agreement and specify, and these data are delivered to Controller Area Network BUS, finally achieve the collection of high-precision analog input.Analog input card reliability of the present utility model is high, and antijamming capability is strong, can meet the demand that high voltage gathers.
Embodiment two
The present embodiment does further supplementary notes to above-described embodiment, the structural representation of the high voltage isolated power supply circuit that Fig. 2 provides for the utility model embodiment two, as shown in Figure 2, high voltage isolated power supply circuit 1 comprises the first resistance 1101, first electric capacity 1201, second electric capacity 1202, the 3rd electric capacity 1203, the 4th electric capacity 1204, the 5th electric capacity 1205, first control chip 1001, the 6th electric capacity 1206 and the first counnter attack diode 1301.
Concrete, first resistance 1101, first electric capacity 1201, second electric capacity 1202, the 3rd electric capacity 1203 are arranged in parallel between the first input end 111 and the second input 112 of high voltage isolated power supply circuit 1, wherein the first resistance 1101 can be piezo-resistance, for the infringement preventing the voltage jump inputing to high_voltage isolation collection potential circuit 1 from causing circuit, 3rd electric capacity 1203 is polar capacitor, be used for preventing surge, in addition, in order to suppress common-mode signal, choke coil 1200 can be set between the first electric capacity 1201 and the second electric capacity 1202.
Further, in order to filtering clutter, the first end of the 4th electric capacity 1204 is connected between the second electric capacity 1202 and the 3rd electric capacity 1203, second end of the 4th electric capacity 1204 is connected with the first end of the 5th electric capacity 1205, and the second end of the 5th electric capacity 1205 is connected between the second electric capacity 1202 and the 3rd electric capacity 1203, wherein, in order to reduce the radiation in circuit, meet safety requirement, by wired earth between the 4th electric capacity 1204 and the 5th electric capacity 1205, make high frequency spurs stream ground end.
The first end of the 4th electric capacity 1204 is connected with the first input end 121 of the first control chip 1001, and the second end of the 5th electric capacity 1205 is connected with the second input 122 of the first control chip 1001.
The 6th electric capacity 1206 and the first counnter attack diode 1301 parallel with one another is provided with between first output 131 of the first control chip 1001 and the second output 132, wherein the first counnter attack diode 1301 can prevent external circuit to the signal disturbing of high voltage isolated power supply circuit 1, optionally, first counnter attack diode 1301 can adopt transient state suppression (Transient Voltage Suppressor is called for short TVS) diode.Further, the first counnter attack diode 1301 is connected with the energization input of High Pressure Difference divisional processing circuit 2.Concrete, the first counnter attack diode 1301 is connected with the energization input of the second operational amplification circuit in High Pressure Difference divisional processing circuit 2.Utility model
The structural representation of the High Pressure Difference divisional processing circuit that Fig. 3 provides for the utility model embodiment two, preferably, as shown in Figure 3, High Pressure Difference divisional processing circuit 2 comprises: the second resistance 1102, first operational amplifier 101, the 3rd resistance 1103, second operational amplifier 102, the 4th resistance 1104, the 3rd operational amplifier 103, the 5th resistance 1105, the 6th resistance 1106, four-operational amplifier 104, the 7th resistance 1107.
The first input end 141 of High Pressure Difference divisional processing circuit 2 is connected with the in-phase input end of the first operational amplifier 101 by the second resistance 1102, the output of the first operational amplifier 101 is connected with the inverting input of the second operational amplifier 102 by the 3rd resistance 1103, the output of the second operational amplifier 102 is connected with the in-phase input end of the 3rd operational amplifier 103 by the 4th resistance 1104, and the output of the 3rd operational amplifier 103 is connected by the input of the 5th resistance 1105 with isolation Acquisition Circuit 3.
Wherein, second operational amplifier 102 also comprises the first feedback resistance 1021, the two ends of the first feedback resistance 1021 connect inverting input and the output of the second operational amplifier 102 respectively, further, the energization input of the second operational amplification circuit comprises the first energization input 151 and the second energization input 152.First energization input 151 of the second operational amplifier 102 is connected with the first output 131 of the first control chip 1001 in high voltage isolated power supply circuit 1, and the second energization input 152 of the second operational amplifier 102 is connected with the second output 132 of the first control chip 1001 in high voltage isolated power supply 1.In addition, high voltage isolated power supply circuit 1 is also connected with the energization input of the first operational amplification circuit 1, for the first operational amplification circuit 1 provides the voltage of 0-74V to input.
Further, second input 142 of High Pressure Difference divisional processing circuit 2 is connected with the in-phase input end of four-operational amplifier 104 by the 6th resistance 1106, and the output of four-operational amplifier 104 is connected with the in-phase input end of the second operational amplifier 102 by the 7th resistance 1107.
Because analog input plate is when carrying out signals collecting, signals collecting is carried out by four acquisition channels, each acquisition channel all has the High Pressure Difference divisional processing circuit of its correspondence, signal disturbing in order to avoid between unlike signal acquisition channel, the second counnter attack diode 1302 is also provided with between the first input end 141 of High Pressure Difference divisional processing circuit 2 and the second input 142, 8th resistance 1108 and the 9th resistance 1109, wherein, 8th resistance 1108 and the 9th resistance 1109 are arranged in order to release current, concrete, the first end of the 8th resistance 1108 is connected with the first input end 141 of High Pressure Difference divisional processing circuit 2, be connected between the second counnter attack diode 1302 and the second resistance 1102, second end of the 8th resistance 1108 is connected with the first end of the 9th resistance 1109, second end of the 9th resistance 1109 is connected with second input 142 on High Pressure Difference divisional processing electricity 2 tunnels, the 7th electric capacity 1207 is provided with between second end of the 8th resistance 1108 and the second end of the second resistance 1102, the first end of the 7th electric capacity 1207 is connected with the second end of the second resistance 1102, second end ground connection of the 7th electric capacity 1207, clutter can be imported the earth, second end of the 8th resistance 1109 is connected with the second end of the 7th electric capacity 1207, optionally, first counnter attack diode 1301 can adopt transient state to suppress (Transient Voltage Suppressor, be called for short TVS) diode.
In addition, in order to the clutter composition in better filtering circuit, the first filter capacitor 2001, second filter capacitor 2002 and the 3rd filter capacitor 2003 is also provided with.Wherein, the first end of the first filter capacitor 2001 is connected between the 6th resistance 1106 and the in-phase input end of four-operational amplifier 104, second end ground connection of the second filter capacitor 2001, the first end of the second filter capacitor 2002 is connected between the in-phase input end of the 4th resistance 1104 and the 3rd operational amplifier 103, second end ground connection of the second filter capacitor 2002, the first end of the 3rd filter capacitor 2003 is connected between the input of the 5th resistance 1105 and isolation Acquisition Circuit 3, the second end ground connection of the 3rd filter capacitor 2003.Simultaneously, in order to prevent the earth in clutter on the impact of whole High Pressure Difference divisional processing circuit 2, also be provided with earth resistance 2004, concrete, the first end of earth resistance 2004 connects 1107 between the 7th resistance 1107 and the in-phase input end of the second operational amplifier 2, the second end ground connection of earth resistance 2004.
It should be noted that, wherein, first operational amplifier 101, second operational amplifier 102, the 3rd operational amplifier 103, four-operational amplifier 104 adopt the operational amplifier that can bear higher supply voltage, optionally, what can adopt Linear Techn Inc. can bear the operational amplifier that supply voltage is 140V.
The structural representation of the isolation Acquisition Circuit that Fig. 4 provides for the utility model embodiment two, preferably, as shown in Figure 4, isolate Acquisition Circuit 3 and comprise the 5th operational amplifier 105, second control chip 1002, the tenth resistance 1110, the 8th electric capacity 1208, the 6th operational amplifier 106.Wherein, the second control chip 1002 is linear optical coupling element.
Concrete, the inverting input of the 5th operational amplifier 105 is connected with the first input end 171 of the second control chip 1002, the output of the 5th operational amplifier 105 is connected with the second input 172 of the second control chip 1002 by the tenth resistance 1110, the 8th electric capacity 1208 is provided with between the inverting input of the 5th operational amplifier 105 and the output of the 5th operational amplifier 105, the first end of the 8th electric capacity 1208 is connected between the inverting input of the 5th operational amplifier 105 and the first input end 171 of the second control chip 1002, second end of the 8th electric capacity 1208 is connected between the output of the 5th operational amplifier 105 and the tenth resistance 1110.The in-phase input end ground connection of the 5th operational amplifier 105, and also have power supply (not shown) to be that the 5th operational amplifier 105 is powered in addition, power supply voltage range is 0-15V.
Further, first output 161 of the second control chip 1002 is connected with the inverting input of the 6th operational amplifier 106, second output 162 of the second control chip 1002 is connected with the in-phase input end of the 6th operational amplifier 106, and the output of the 6th operational amplifier 106 is connected with the input of low-voltage signal treatment circuit 4.
In addition, 6th operational amplifier 106 also comprises the second feedback resistance 1022 and the 9th electric capacity 1209, second feedback resistance 1022 and the 9th electric capacity 1209 parallel with one another, between the anti-phase defeated input being connected to the 6th operational amplifier 106 and output, the in-phase input end ground connection of the 6th operational amplifier 106.
The structural representation of the low-voltage signal treatment circuit that Fig. 5 provides for the utility model embodiment two, preferably, as shown in Figure 5, low-voltage signal treatment circuit 4 comprises the 7th operational amplifier the 107, the 11 resistance the 1111, the 12 resistance the 1112, the 13 resistance the 1113, the 14 resistance 1114 and the 8th operational amplifier 108.
Concrete, the inverting input of the 7th operational amplifier 107 is connected with the output of the 6th operational amplifier 106 by the 11 resistance 1111, the in-phase input end of the 7th operational amplifier 107 is by the 12 resistance 1112 ground connection, and the output of the 7th operational amplifier 107 is connected with the inverting input of the 8th operational amplifier 108 by the 13 resistance 1113.The in-phase input end of the 8th operational amplifier 108 is connected to ground by the 14 resistance 1114, and the output of the 8th operational amplifier 108 is connected with processor 5.
Wherein, it is parallel with one another that the 7th operational amplifier 107 also comprises the 3rd feedback resistance 1023 and the tenth electric capacity the 1210, three feedback resistance 1023 and the tenth electric capacity 1210, between the inverting input being connected to the 7th operational amplifier 107 and output.8th operational amplifier 108 also comprises the 4th feedback capacity 1024, the two ends of the 4th feedback capacity 1024 are connected with the inverting input of the 8th operational amplifier 108 and output respectively, in addition, also have power supply (not shown) to be that the 7th operational amplifier 107 is powered, power supply voltage range is 0-15V.
It should be noted that, in the present embodiment, the ground connection in the 6th operational amplifier 106, the 7th operational amplifier 107 and the 8th operational amplifier 108 for connect with common the earth, namely with the reference in circuit connect, remaining ground connection is and connects in analog.
From above technical scheme, analog input card of the present utility model realizes the collection to external equipment high-voltage signal by High Pressure Difference divisional processing circuit 2, and the high-voltage signal collected is carried out step-down, further by isolation Acquisition Circuit 3, isolated high-voltage difference processing circuit 2 and low-voltage signal treatment circuit 4, thus the high-voltage signal avoiding external equipment is to the strong jamming of rear portion circuit, improve the stability of whole analog input card, the utility model is also processed the signal that isolation Acquisition Circuit 3 exports by low-voltage signal treatment circuit 4, thus the signal making isolation Acquisition Circuit 3 export meets the input voltage condition of processor 5, digital-to-analogue conversion is carried out further by processor 5, generate the data meeting controller local area network agreement and specify, and these data are delivered to Controller Area Network BUS, finally achieve the collection of high-precision analog input.Analog input card reliability of the present utility model is high, and antijamming capability is strong.
Embodiment three
Present embodiments provide a kind of analogue quantity acquiring method, the schematic flow sheet of the analog output method that Fig. 6 provides for the utility model embodiment three, as shown in Figure 6, the method for this analog acquisition comprises:
Step 301, High Pressure Difference divisional processing circuit exports the first low-voltage analog signal to isolation Acquisition Circuit.
Concrete, High Pressure Difference divisional processing circuit gathers the high-voltage signal that high voltage analog signal is external equipment 0-74V, and the first low-voltage analog signal exported after the step-down of High Pressure Difference divisional processing circuit is the voltage of 0-10V.
Step 302, isolation Acquisition Circuit isolated high-voltage difference processing circuit and low-voltage signal treatment circuit, and linear process is carried out to the first low-voltage analog signal, generate the second low-voltage analog signal, export described second low-voltage analog signal to this low-voltage signal treatment circuit.
The strong jamming brought in order to avoid the high-voltage signal of external equipment gathered affects the work of rear portion circuit, therefore isolation Acquisition Circuit is adopted to carry out electrical isolation, namely utilizing isolation Acquisition Circuit every making the signal in low-voltage signal treatment circuit not by the interference of the signal in High Pressure Difference divisional processing circuit, strengthening the stability of analog input card.Further, in order to meet the input voltage of processor, need to utilize low-voltage signal treatment circuit to carry out further step-down process to the second low-voltage analog signal received.
Step 303, low-voltage signal treatment circuit receives the second low-voltage analog signal, and carries out step-down process to the second low-voltage analog signal, generates the 3rd low-voltage analog signal, with the input voltage making the 3rd low-voltage analog signal meet processor.
Step 304, low pressure processing signals treatment circuit transmits the 3rd low-voltage analog signal to processor.
Concrete, the 3rd low-voltage analog signal is the voltage signal of 0-2.5V.
Step 305, processor receives the 3rd low-voltage analog signal, generates standardized digital signal, and this standardized digital signal is delivered to controller local area network drive circuit.
Wherein, namely standardized digital signal meets the data that controller local area network agreement specifies.The signal resolution of processor also for being sent by controller local area network drive circuit becomes standardized digital signal, is stored in the buffer area of self, reads for controller.For example, processor can comprise STM32F103 single-chip microcomputer and controller local area network protocol integrated test system chip, and STM32F103 single-chip microcomputer is responsible for the work schedule of control controller local area network protocol integrated test system chip and is carried out the mutual of data with external system.
High voltage isolated power supply circuit in the analogue quantity acquiring method of the present embodiment, High Pressure Difference divisional processing circuit, isolation Acquisition Circuit, low-voltage signal treatment circuit, processor, controller local area network drive circuit can be consistent with the structure of above-described embodiment, do not repeat them here.
From above technical scheme, the utility model provides a kind of analogue quantity acquiring method, by High Pressure Difference divisional processing circuit realiration to the collection of external equipment high-voltage signal, and the high-voltage signal collected is carried out step-down, further by isolation Acquisition Circuit isolated high-voltage difference processing circuit and low-voltage signal treatment circuit, thus the high-voltage signal avoiding external equipment is to the strong jamming of rear portion circuit, improve the stability of whole analog input card, the utility model is also processed the signal that isolation Acquisition Circuit exports by low-voltage signal treatment circuit, thus the signal making isolation Acquisition Circuit export meets the input voltage condition of processor, digital-to-analogue conversion is carried out further by processor, generate the data meeting controller local area network agreement and specify, and these data are delivered to Controller Area Network BUS, finally achieve the collection of high-precision analog input.
Last it is noted that above embodiment is only in order to illustrate the technical solution of the utility model, be not intended to limit; Although be described in detail the utility model with reference to previous embodiment, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of each embodiment technical scheme of the utility model.
Claims (8)
1. an analog input card, is characterized in that, comprising: high voltage isolated power supply circuit, High Pressure Difference divisional processing circuit, isolation Acquisition Circuit, low-voltage signal treatment circuit, processor, controller local area network drive circuit;
The output of described high voltage isolated power supply circuit is connected with the energization input of described High Pressure Difference divisional processing circuit, and described high voltage isolated power supply is used for powering to described High Pressure Difference divisional processing circuit;
The output of described High Pressure Difference divisional processing circuit is connected with the input of described isolation Acquisition Circuit, described High Pressure Difference divisional processing circuit is used for carrying out step-down to the high voltage analog signal of the external equipment collected, generate the first low-voltage analog signal, and export described first low-voltage analog signal to described isolation Acquisition Circuit;
The output of described isolation Acquisition Circuit is connected with the input of described low-voltage signal treatment circuit, described isolation Acquisition Circuit is for isolating described High Pressure Difference divisional processing circuit and described low-voltage signal treatment circuit, and linear process is carried out to described first low-voltage analog signal, generate the second low-voltage analog signal, export to described low-voltage signal treatment circuit;
The output of described low-voltage signal treatment circuit is connected with the input of described processor, described low-voltage signal treatment circuit is for reducing described second low-voltage analog signal, generate the 3rd low-voltage analog signal, meet the input voltage of processor to make described 3rd low-voltage analog signal;
The output of described processor is connected with the input of described controller local area network drive circuit, described processor is for receiving described 3rd low-voltage analog signal, generate standardized digital signal, and described standardized digital signal is delivered to controller local area network drive circuit;
The output of described controller local area network drive circuit is connected with Controller Area Network BUS.
2. analog input card according to claim 1, it is characterized in that, described high voltage isolated power supply circuit comprises: the first resistance, the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the first control chip, the 6th electric capacity and the first counnter attack diode;
Between the first input end that described first resistance, the first electric capacity, the second electric capacity, the 3rd Capacitance parallel connection are arranged on described high voltage isolated power supply circuit and the second input;
The first end of described 4th electric capacity is connected between described second electric capacity and described 3rd electric capacity, second end of described 4th electric capacity is connected with the first end of described 5th electric capacity, and the second end of described 5th electric capacity is connected between described second electric capacity and described 3rd electric capacity;
The first end of described 4th electric capacity is connected with the first input end of described first control chip, and the second end of described 5th electric capacity is connected with the second input of described first control chip;
Between the first output that described 6th electric capacity and described first counnter attack diodes in parallel are arranged on described first control chip and the second output;
Described first counnter attack diode is connected with the energization input of described High Pressure Difference divisional processing circuit, the impact that described first counnter attack diode produces the energization input of described High Pressure Difference divisional processing circuit for Anti-surging and voltage jump.
3. analog input card according to claim 2, it is characterized in that, described High Pressure Difference divisional processing circuit comprises: the second resistance, the first operational amplifier, the 3rd resistance, the second operational amplifier, the 4th resistance, the 3rd operational amplifier, the 5th resistance, the 6th resistance, four-operational amplifier, the 7th resistance;
The first input end of described High Pressure Difference divisional processing circuit is connected with the in-phase input end of described first operational amplifier by described second resistance, the output of described first operational amplifier is connected with the inverting input of described second operational amplifier by described 3rd resistance, the output of described second operational amplifier is connected with the in-phase input end of described 3rd operational amplifier by described 4th resistance, and the output of described 3rd operational amplifier is connected with the input of described isolation Acquisition Circuit by described 5th resistance;
Described second operational amplifier also comprises the first feedback resistance, and the two ends of described first feedback resistance connect inverting input and the output of described second operational amplifier respectively;
Second input of described High Pressure Difference divisional processing circuit is connected with the in-phase input end of described four-operational amplifier by the 6th resistance, and the output of described four-operational amplifier is connected with the in-phase input end of described second operational amplifier by the 7th resistance.
4. analog input card according to claim 3, is characterized in that, is also provided with the second counnter attack diode, the 8th resistance and the 9th resistance between the first input end of described High Pressure Difference divisional processing circuit and the second input;
Described second counnter attack diode, for preventing the voltage gathering external equipment excessive, produces voltge surge to the input of described High Pressure Difference divisional processing circuit;
The first end of described 8th resistance is connected with the first input end of described High Pressure Difference divisional processing circuit, second end of described 8th resistance is connected with the first end of described 9th resistance, and the second end of described 9th resistance is connected with the second input of described High Pressure Difference divisional processing circuit;
The 7th electric capacity is provided with between second end of described 8th resistance and the second end of described second resistance, the first end of described 7th electric capacity is connected with the second end of described second resistance, second end ground connection of described 7th electric capacity, the second end of described 8th resistance is connected with the second end of described 7th electric capacity.
5. analog input card according to claim 4, is characterized in that, described isolation Acquisition Circuit comprises the 5th operational amplifier, the second control chip, the tenth resistance, the 8th electric capacity, the 6th operational amplifier;
The inverting input of described 5th operational amplifier is connected with the first input end of described second control chip, the output of described 5th operational amplifier is connected with the second input of described second control chip by described tenth resistance, the 8th electric capacity is provided with between the inverting input of described 5th operational amplifier and the output of described 5th operational amplifier, between the inverting input that the first end of described 8th electric capacity is connected to described 5th operational amplifier and the first input end of described second control chip, second end of described 8th electric capacity is connected between the output of described 5th operational amplifier and described tenth resistance,
First output of described second control chip is connected with the inverting input of described 6th operational amplifier, second output of described second control chip is connected with the in-phase input end of described 6th operational amplifier, and the output of described 6th operational amplifier is connected with the input of described low-voltage signal treatment circuit;
Described 6th operational amplifier also comprises the second feedback resistance and the 9th electric capacity, described second feedback resistance and described 9th electric capacity parallel with one another, between the anti-phase defeated input being connected to described 6th operational amplifier and output.
6. analog input card according to claim 5, is characterized in that, described low-voltage signal treatment circuit comprises the 7th operational amplifier, the 11 resistance, the 12 resistance, the 13 resistance, the 14 resistance and the 8th operational amplifier;
The inverting input of described 7th operational amplifier is connected with the output of described 6th operational amplifier by described 11 resistance, the in-phase input end of described 7th operational amplifier is connected to ground by described 12 resistance, and the output of described 7th operational amplifier is connected with the inverting input of described 8th operational amplifier by described 13 resistance;
The in-phase input end of described 8th operational amplifier is connected to ground by described 14 resistance, and the output of described 8th operational amplifier is connected with described processor;
Described 7th operational amplifier also comprises the 3rd feedback resistance and the tenth electric capacity, described 3rd feedback resistance and the tenth electric capacity parallel with one another, between the inverting input being connected to described 7th operational amplifier and output;
Described 8th operational amplifier also comprises the 4th feedback capacity, and the two ends of described 4th feedback capacity are connected with the inverting input of described 8th operational amplifier and output respectively.
7. analog input card according to claim 1, is characterized in that, described processor comprises STM32F103 single-chip microcomputer and controller local area network protocol integrated test system chip.
8. analog input card according to claim 5, is characterized in that, described second control chip is linear optical coupling element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420821148.7U CN204302728U (en) | 2014-12-19 | 2014-12-19 | Analog input card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420821148.7U CN204302728U (en) | 2014-12-19 | 2014-12-19 | Analog input card |
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|---|---|
| CN204302728U true CN204302728U (en) | 2015-04-29 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105759675A (en) * | 2014-12-19 | 2016-07-13 | 中车大连电力牵引研发中心有限公司 | Analog quantity input board card and analog quantity acquisition method |
| CN106627156A (en) * | 2016-11-06 | 2017-05-10 | 北京理工华创电动车技术有限公司 | High-voltage information acquisition controller |
| CN111830423A (en) * | 2020-06-24 | 2020-10-27 | 东风电驱动系统有限公司 | Isolated high-voltage sampling circuit |
-
2014
- 2014-12-19 CN CN201420821148.7U patent/CN204302728U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105759675A (en) * | 2014-12-19 | 2016-07-13 | 中车大连电力牵引研发中心有限公司 | Analog quantity input board card and analog quantity acquisition method |
| CN106627156A (en) * | 2016-11-06 | 2017-05-10 | 北京理工华创电动车技术有限公司 | High-voltage information acquisition controller |
| CN111830423A (en) * | 2020-06-24 | 2020-10-27 | 东风电驱动系统有限公司 | Isolated high-voltage sampling circuit |
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Address after: 116045 Liaoning province Dalian City Lushun Economic Development Zone Dalian Hao Yang No. 1 North Street Patentee after: CRRC DALIAN ELECTRIC TRACTION R & D CENTER CO., LTD. Address before: 116045 Liaoning province Dalian City Lushun Economic Development Zone Dalian Hao Yang No. 1 North Street Patentee before: Co., Ltd of Bei Che Dalian Electric Traction R & D Center |