CN204290716U - A kind of circuit - Google Patents
A kind of circuit Download PDFInfo
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- CN204290716U CN204290716U CN201420509516.4U CN201420509516U CN204290716U CN 204290716 U CN204290716 U CN 204290716U CN 201420509516 U CN201420509516 U CN 201420509516U CN 204290716 U CN204290716 U CN 204290716U
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Abstract
The execution mode of present disclosure relates to circuit.First soft-start signal indicates the operation in the load phase of boost rectifier and the operation in the second pulsed drive stage of soft-start signal instruction after this load phase.Rectifying transistor is energized to generate the output voltage risen within the duration of load phase in response to the first soft starting circuit.Rectifying transistor is repeatedly encouraged the output voltage generating boosting in response to the second soft starting circuit further during the pulsed drive stage.During load phase, the first transistor be coupling between the first Lead-through terminal of rectifying transistor and body terminal is energized, and the transistor seconds be coupling between the body terminal of rectifying transistor and the second Lead-through terminal is deactivated.During the pulsed drive stage, the first transistor is deactivated, and transistor seconds is energized.
Description
Technical field
Present disclosure relates generally to step-up converter circuit, particularly relates to a kind of for using in boost converter to control the circuit of shutdown electric current.
Background technology
DC/DC converter circuit widely uses in battery powered portable set.The example of such equipment comprises: smart phone, intelligent watch, camera, media player and other portable digital device multiple.For the transducer of boost type, circuit carries out operating receive DC input voltage (from battery) and generate DC output voltage, and wherein the magnitude of DC output voltage is more than the magnitude of DC input voltage.In order to extending battery life, those skilled in the art recognize that, especially in the down periods, the leakage current between needing input and output controls.
Utility model content
Technical problem to be solved in the utility model is the technical problem of the existing Leakage Current how solving the above-mentioned circuit down periods.
In one embodiment, a kind of circuit comprises boost converter, and it has: input node; Output node; Rectifying transistor, it to be coupling between this input and output node and to have body terminal; The first transistor, it is coupling between this input node and body terminal; And transistor seconds, it is coupling between this body terminal and output node.This circuit comprises further: soft starting circuit, and it is configured to receive soft-start signal and the first control signal generating the control terminal being applied to this rectifying transistor in response to this; And drive circuit, it is configured to generate the second control signal of the control terminal being applied to this first transistor, and is configured to further receive this soft-start signal and generates the 3rd control signal of the control terminal being applied to this transistor seconds in response to this.
According to an execution mode, described input node is arranged to and is connected to inductor and described output node is arranged to and is connected to capacitor.
According to an execution mode, described soft-start signal comprises: the first enabling signal, and described soft starting circuit encourages described rectifying transistor to charge to described output node in response to described first enabling signal by described first control signal; And second enabling signal, described soft starting circuit allows repeatedly to encourage described rectifying transistor to boost to the voltage at described output node place by described first control signal in response to described second enabling signal.
According to an execution mode, described drive circuit be configured to described first enabling signal and described second enabling signal all effectively time encourage described transistor seconds by described 3rd control signal.
According to an execution mode, the control terminal of described the first transistor is controlled by described second control signal by the voltage of described output node.
According to an execution mode, this circuit comprises further: the first Nverter circuit, and described first Nverter circuit has as the 3rd control signal and is coupled to the output of the described control terminal of described transistor seconds and has the first power supply terminal and the second power supply terminal; Voltage control circuit, is configured to, in response to the output of described first Nverter circuit, one of the voltage at the voltage at described input terminal place or described lead-out terminal place is applied to described first power supply terminal; And clamp circuit, be configured to the voltage that the voltage from described body terminal draws to be applied to described second power supply terminal.
According to an execution mode, described soft-start signal comprises the first soft-start signal and the second soft-start signal, and wherein said clamp circuit is controlled in response to described first soft-start signal and wherein said first Nverter circuit is controlled in response to described second soft-start signal.
According to an execution mode, this circuit comprises the second Nverter circuit further, described second Nverter circuit has the output of the input being coupled to described first Nverter circuit, and wherein said voltage control circuit responds the output of described second Nverter circuit further and wherein said second Nverter circuit is controlled in response to described second soft-start signal.
According to an execution mode, described first power supply terminal is logic high signal supply terminal and described second power supply terminal is logic low signal supply terminal, and described 3rd control signal has the voltage from described logic low supply terminal when encouraging described transistor seconds.
In one embodiment, a kind of circuit comprises: booster circuit, and it comprises the rectifying transistor with the first and second Lead-through terminals and body terminal; The first transistor, it is coupling between this first Lead-through terminal and body terminal; And transistor seconds, it is coupling between this body terminal and the second Lead-through terminal; And control circuit, it is configured to control the operation of described booster circuit.This control circuit comprises: soft starting circuit, it is configured to receive the first soft-start signal of instruction load phase and indicate second soft-start signal in the pulsed drive stage after described load phase, this soft starting circuit can operate with this rectifying transistor of duration underexcitation in response to the first soft starting circuit in this load phase, and can operate further with transport pulse signal during this pulsed drive stage to control the excitation of this rectifying transistor; With body control circuit, it is configured to control in response to this excitation of the first and second soft-start signal to this first and second transistor, this body control circuit can operate with in the first soft-start signal activity and the second soft-start signal without encouraging the first transistor during activity and transistor seconds of stopping using, and can operate to stop using the first transistor and encourage transistor seconds when the second soft-start signal activity further.
According to an execution mode, this circuit comprises the output node of described second Lead-through terminal being coupled to described rectifying transistor further, and described body control circuit comprises the circuit being configured to the described control terminal described output node being coupled to described the first transistor.
According to an execution mode, this circuit comprises clamp voltage generator circuit further, has the supply node of the described body terminal being coupled to described rectifying transistor and is configured to generate the clamp voltage as the function of the logic state of described first soft-start signal.
According to an execution mode, this circuit comprises the first Nverter circuit further, has logic height supply node, logic low supply node, is configured to generate the output node for the control signal controlled the excitation of described transistor seconds; Wherein said clamp voltage is applied to described logic low supply node.
According to an execution mode, this circuit comprises voltage control circuit further, is configured to select the first voltage or the second voltage to be applied to described logic height supply node in response to described control signal.
According to an execution mode, described first voltage is the voltage of the output of described booster circuit and described second voltage is the voltage of the input of described booster circuit.
According to an execution mode, the input of described reverser is configured to receive the signal drawn from described second soft-start signal.
In one embodiment, a kind of method comprises: receive the first soft-start signal, the operation in the load phase of its instruction boost rectifier; In response to the first soft starting circuit at this rectifying transistor of duration underexcitation of this load phase to generate the output voltage risen towards the level of input voltage, described rectifying transistor has the first and second Lead-through terminals and body terminal; Receive the second soft-start signal, it indicates the operation in the pulsed drive stage after the described load phase of described boost rectifier; During this pulsed drive stage, transport pulse signal generates the output voltage through boosting to control the excitation repeatedly of this rectifying transistor; During this load phase, encourage the first transistor that is coupling between the first Lead-through terminal and body terminal and the transistor seconds be coupling between body terminal and the second Lead-through terminal of stopping using exceedes input voltage to boost to described output voltage; And during this pulsed drive stage, encourage the transistor seconds and the first transistor be coupling between the first Lead-through terminal and body terminal of stopping using that are coupling between body terminal and the second Lead-through terminal.
According to execution mode of the present utility model, leakage current is very little.
Accompanying drawing explanation
In order to more intactly understand present disclosure and advantage thereof, with reference now to the description carried out below in conjunction with accompanying drawing, wherein:
Fig. 1 is the circuit diagram of the embodiment of boost converter;
Fig. 2 is the circuit diagram of the embodiment of boost converter;
Fig. 3 A and 3B illustrates the operation of the circuit of Fig. 2;
Fig. 3 C is the circuit diagram of the operation for control chart 2A;
Fig. 4 is the circuit diagram for the soft starting circuit used with the circuit of Fig. 2;
Fig. 5 is the sequential chart of circuit operation; With
Fig. 6 is the circuit diagram of body control circuit.
Embodiment
With reference now to Fig. 1, it illustrates the circuit diagram of the embodiment of boost converter 100.Circuit 100 comprises node LX.Inductor L is coupling in node LX and is configured to receive between the power supply input node VIN of input voltage.Shunting transistor MN is coupling between node LX and benchmark supply node (such as, earth terminal).Transistor MN such as can comprise n channel MOSFET transistors, and it has the source drain path be coupling between node LX and benchmark supply node.The control terminal (grid) of transistor MN is configured to receiving key signal S1.Circuit 100 comprises transistor MP1 and MP2 being coupling in pair of series connection between node LX and output node VOUT further.Transistor MP1 and MP2 such as can comprise p channel MOSFET transistors, and it has the source drain path of between node LX and node VOUT (at node VMID) mutual series coupled.The control terminal (grid) of transistor MP1 is configured to receiving key signal S2.The control terminal (grid) of transistor MP2 is configured to receiving key signal S3.Capacitor Cout is coupling between output node VOUT and benchmark supply node.Transistor MP1 comprises rectifying transistor, and transistor MP2 comprises load transistor.
In a kind of example embodiment, node LX can comprise the package pins of integrated device electronics, and inductor L is provided as external circuit components.In another kind of example embodiment, node VOUT comprises the package pins of integrated device electronics.Capacitor Cout may be provided in internal circuit unit (as shown) or external circuit components.In another execution mode, node VOUT can comprise the node of integrated device electronics inside, and it is configured to the DC voltage of other circuit arrangement supply through boosting to being also implemented in this integrated device electronics.
Switching signal S1, S2 and S3 are generated by control circuit 102.At operate in any case, load transistor MP2 encouraged by control signal S3.Control circuit 102 encourages shunting transistor MN to be coupling in by inductor L between supply node VIN and benchmark supply node by control signal S1 subsequently.Electric current flows through inductor L and voltage across inductor increases.Control circuit deactivated transistor MN and encourage rectifying transistor MP1 by control signal S2 subsequently.Therefore electric current flows through transistor MP1 and MP2 and enters output capacitor Cout.Control circuit deactivated transistor MP1 and repeat this process subsequently.As a result, to be stored in capacitor Cout and to be caught the voltage rise that can obtain at input node VOUT place to the level of voltage exceeding input node VIN place.
When circuit 100 is closed, transistor MP1 and MP2 all turns off.The body diode of these transistors is reverse biased and does not therefore supply the path of current leakage between node VIN and VOUT.The voltage at node VMID place will move to one higher in two voltages making to obtain at node VIN and VOUT place.
Notice that the defect of circuit 100 comprises: a) need two pMOS devices (MP1 and MP2), this occupies the bulk area on integrated circuit, and transistor MP1 b) owing to being used as the switching transistor exporting rectification needs twice size to keep little Rdson numerical value still however still to produce the switching loss of increase, so its efficiency is lower.
With reference now to Fig. 2, it illustrates the circuit diagram of the embodiment of boost converter 110.Same Reference numeral about the circuit 100 of Fig. 1 refers to same or similar part.Circuit 110 comprises the rectifying transistor MP be coupling between node LX and output node VOUT.Transistor MP such as can comprise p channel MOSFET transistors, and its source drain path is coupling between node LX and node VOUT.The control terminal (grid) of transistor MP is configured to receiving key signal S4.Circuit 110 comprises body control transistor MPS1 and MPS2 being coupling in the pair of series between node LX and output node VOUT and connecting further.Transistor MPS1 and MPS2 such as can comprise p channel MOSFET transistors, their source drain path (at Node B G) series coupled mutually between node LX and node VOUT.Node B G is coupled to the body terminal of transistor MP.The control terminal (grid) of transistor MPS1 is configured to receiving key signal S5.The control terminal (grid) of transistor MPS2 is configured to receiving key signal S6.Therefore transistor MPS1 and MPS2 be connected in series be connected in parallel with transistor MP.Transistor MPS1 and MPS2 will be the device being significantly less than transistor MP usually.
Transistor MPS1 with MPS2 carries out work and is connected with the body controlling transistor MP.If the voltage at node VIN place is greater than the voltage at node VOUT place, then control circuit 102 carries out work, with driver transistor MPS1, the body of transistor MP is coupled to the drain electrode (see Fig. 3 A) of transistor MP and the back-biased body diode utilizing transistor MPS2 to provide and prevent the Leakage Current from being input to output at Node B G.On the contrary, if the voltage at node VOUT place is greater than the voltage at node VIN place, then control circuit 102 carries out work, with driver transistor MPS2, the body of transistor MP is coupled to the source electrode (see Fig. 3 B) of transistor MP and the back-biased body diode utilizing transistor MPS1 to provide and prevent the Leakage Current from outputting to input at Node B G.
Switching signal S1, S4, S5 and S6 generated by control circuit 202.First control circuit 202 encourages shunting transistor MN to be coupling in by inductor L between supply node VIN and benchmark supply node by control signal S1.Electric current flows through inductor L and voltage across inductor terminals increases to some extent.Control circuit deactivated transistor MN and by control signal S4 driver transistor MP subsequently.Therefore electric current enters output capacitor Cout by transistor MP.Control circuit deactivated transistor MP and repeat this process subsequently.As a result, be stored in capacitor Cout and make the voltage rise that can obtain at output node VOUT place to the level of voltage exceeding input node VIN place.
Control circuit 202 is used as voltage sensor 204 further to sense and the voltage (see Fig. 3 C) at comparison node VIN and VOUT place.If booster circuit 110 is turned off and the voltage at the sensing instructs node VIN place of voltage is greater than the voltage at node VOUT place, then control circuit driver transistor MPS1 (by signal S5) and the body diode of transistor MPS2 is reverse biased in case stopping leak leakage current (Fig. 3 A).When booster circuit 110 carries out work and the voltage at the sensing instructs node VOUT place of voltage is greater than the voltage at node VIN place, then control circuit driver transistor MPS2 (by signal S6) and the body diode of transistor MPS1 is reverse biased in case stopping leak leakage current (Fig. 3 B).
Notice that the defect of circuit 110 comprises: a) there is the cut-off current (Fig. 3 C) be associated with the operation of amplifier/comparator; B) need PCLAMP circuit to control the conducting of transistor MPS2 when the voltage at node VOUT place remains high after shutdown, and this clamp circuit is by consumed power; And c) amplifier/comparator and PCLAMP circuit occupy the large stretch of area on integrated circuit.
With reference now to Fig. 4, it illustrates the soft starting circuit 120 for using with the circuit 110 of Fig. 2.Soft starting circuit 120 comprises the logic circuit apparatus that can be included in control circuit 202.Soft starting circuit 120 comprises logical AND (AND) door 122, and it has the grid that is coupled to transistor MP and is configured to generate the output of control signal DrP (as signal S4).Soft starting circuit 120 comprises logical AND non-(NAND) door 124 further, and it has the output of the first input being coupled to logic AND door 122.Second input of logic AND door 122 is configured to Received signal strength Driver_P.Soft starting circuit 120 comprises logic NOT (NOT) door 126 further, and it has the output of the first input being coupled to logic NAND door.Second input of logic NAND door 124 is configured to Received signal strength PLOAD.The input of logic NOT door 126 is configured to Received signal strength PWD_ST.PLOAD and PWD_ST signal is soft-start signal.
The operating process (shown in Fig. 5) of circuit 110 comprises four-stage:
Stage 1:PLOAD=0, PWD_ST=0, Driver_P=1, DrP=1, VOUT=0.This is dwell period.
Stage 2:PLOAD=1, PWD_ST=0, Driver_P=1, DrP=0 are with conducting MP.Output capacitor Cout is slowly charged the voltage reaching node VIN place.This is load phase.
Stage 3:PLOAD=1, PWD_ST=1, DrP control by Driver_P signal to carry out switching and cause the boosted magnitude of voltage to being greater than node VIN place of the voltage at output node VOUT place.Carry out supplementing excitation to control transistor MN to signal S1 (not shown).This is the pulsed drive stage.
Stage 4: if this equipment is closed, but still need the voltage at VOUT place, then PLOAD=0, PWD_ST=0 and DrP=1.
This four operational phases can be associated to the energized condition of the different requirement of transistor MPS1 and MPS2 as follows.
Stage 1: transistor MPS1 is carried out the drain electrode encouraged Node B G to be connected to transistor MP by signal S5 by control circuit 202.
Stage 2: transistor MPS1 is carried out the drain electrode encouraged Node B G to be connected to transistor MP by signal S6 by control circuit 202.Transistor MPS2 is deactivated.
Stage 3: transistor MPS2 is carried out the source electrode encouraged Node B G to be connected to transistor MP by signal S6 by control circuit 202.Transistor MPS1 is deactivated.
Stage 4: transistor MPS2 controlled signal 202 carries out encouraging with source electrode Node B G being connected to transistor MP (voltage at voltage about node VIN place at node VOUT place simultaneously, otherwise turn to the stage 1).Transistor MPS1 is deactivated.
Therefore, PLOAD and PWD_ST soft-start signal suitably can be encouraged transistor MPS1 and MPS2 based on the operational phase to generate control signal S4 and S5 by the process of body control circuit.With reference now to Fig. 6, the circuit diagram of the body control circuit 130 used when it illustrates for controlling the body terminal of the transistor MP in step-up converter circuit.Same Reference numeral about the circuit 110 of Fig. 2 refers to same or similar part.Circuit 130 comprises the circuit arrangement that can be included in control circuit 202.Advantageously, the comparator circuit 204 of Fig. 3 C does not need, and can be removed to control the transistor of MPS1 and MPS2 owing to providing other circuit arrangement.
The gate terminal of transistor MPS1 is coupled to output node VOUT.Therefore, signal S5 equal the voltage at output node VOUT place and the exciter response of transistor MPS1 in the voltage at node VOUT place, the voltage at node VOUT place is then controlled in response to soft-start signal PLOAD and PWD_ST.If PLOAD and PWD_ST is low, then output voltage VO UT be low and transistor MPS1 be energized.If PLOAD is for high and PWD_ST is low, then output voltage keeps below the voltage at node VIN place and transistor MPS1 keeps being energized at this section of time durations within a period of time.
Clamp circuit 140 comprises the transistor M3 having and be configured to control (grid) terminal receiving PLOAD soft-start signal.Transistor M3 can comprise n channel mosfet.The source drain path of transistor M3 between node PCLAMP and supply datum node (earth terminal) with current source I3 series coupled.Circuit 140 is powered from the voltage of Node B G.Resistor R1 is coupling between Node B G and node PCLAMP.Zener diode D1 and resistor R1 is coupling between Node B G and node PCLAMP in parallel.Circuit 140 is configured to the clamp voltage at output node PCLAMP place, and this clamp voltage depends on signal PLOAD.As PLOAD=0, PCLAMP=V
bGand as PLOAD=1, PCLAMP=V
bG-V
d1.
Signal S6 is generated by drive circuit 142.Circuit 142 comprises the transistor M4 having and be configured to control (grid) terminal receiving PWD_ST soft-start signal.Transistor M4 can comprise n channel mosfet.The source drain path of transistor M4 between Node B and supply datum node (earth terminal) with current source I4 series coupled.Circuit 142 carries out power (as described below, the voltage at node VPRL place draws (such as, selecting between which) from the voltage of node VOUT and node VIN) from the voltage of node VPRL.Resistor R2 is coupling between node VPRL and Node B.Zener diode D2 and resistor R2 is coupling between node VPRL and Node B in parallel.Circuit 142 is configured to the drive singal at output node B place, and this drive singal depends on signal PWD_ST.As PWD_ST=0, B=V
vPRL, and as PWD_ST=1, B=V
vPRL-V
d2.
The drive singal at Node B place utilizes low logical voltage level to be shifted the signal carrying out cushioning to generate Node B 1 and B2 place by a pair Nverter circuit 144 and 146.Nverter circuit 144 and 146 all has the first power supply terminal (such as, Vdd) being coupled to node VPRL, and all has the second power supply terminal (such as, earth terminal) being coupled to node PCLAMP.The voltage at the first power supply terminal place is for the signal definition logic high voltage exported from each reverser, and the voltage at the second power supply terminal place is for the signal definition logic low-voltage exported from each reverser.Thus, will be noted that, the voltage being set to the node PCLAMP place of logic low-voltage is shifted and higher than reference voltage (earth terminal).
Circuit 140 comprises the transistor M1 with the control terminal (grid) being coupled to the Node B 2 and transistor M2 with the control terminal (grid) being coupled to Node B 1 further.Transistor M1 and M2 can comprise p channel mosfet.The source drain path of transistor M1 is coupling between node VPRL and node VOUT.The source drain path of transistor M2 is coupling between node VPRL and node VIN.The circuit arrangement comprising transistor M1 and M2 is used as voltage control circuit, it is configured to generate the voltage at node VPRL place, as the voltage (when transistor M1 conducting) at node VOUT place or the voltage (during when transistor M2 conducting) at node VIN place.Control operation is in response to the signal at Node B 1 and B2 place.Therefore, according to the selection that voltage control circuit carries out, the logic high voltage of the signal exported from each reverser will be the voltage of node VOUT or the voltage at node VIN place.
Circuit 40 can carry out in each stage described above operating with following suitably driver transistor MPS1 and MPS2:
Stage 1:VOUT=0V, and when being applied to the grid of transistor MPS1 as signal S5, this voltage causes transistor MPS1 conducting (compared with Fig. 3 A) and the voltage at Node B G place equals the voltage at node VIN place.PLOAD=0, therefore transistor M3 turns off and the voltage at node PCLAMP place equals the voltage (that is, it equals the voltage at node VIN place) at Node B G place by pullup resistor R1.In this case, the voltage at node VPRL place is approximately equal to the voltage (and being therefore approximately equal to the voltage at Node B G place) at node PCLAMP place.Reverser 144 and 146 does not operate.Therefore transistor M1 and M2 be turned off, cannot turn-on transistor M1 or transistor M2 because the voltage at Node B 1 and B2 place is all too high.But the body of transistor M1 and M2 is coupled to the voltage at node VPRL place.The signal DrP exported from soft starting circuit 120 will equal the voltage of node VBPRL and transistor MP is turned off.
Stage 2:PLOAD=1 and PWD_ST=0.In response to PLOAD signal, the voltage equaling Node B G place deducts across the voltage set by the pressure drop (such as, 5V) of Zener diode D1 transistor M3 by conducting and the voltage at node PCLAMP place.This voltage is by the signal setting logic low voltage level for exporting from reverser 144 and 146.Transistor M4 turns off in response to signal PWD_ST, and therefore Node B has the voltage (by pullup resistor R2) of the voltage equaling node VPRL place.Therefore buffering Nverter circuit 144 and 146 produces the signal with the logic low-voltage of the voltage equaling node PCLAMP place at Node B 1 place and the signal with the logic high voltage of the voltage equaling node VPRL place at Node B 2 place in response to the voltage at Node B place.Transistor M2 in response to the logic low-voltage at Node B 1 place conducting so that the voltage at node VIN place is applied to node VPRL.Transistor M1 and MPS2 keeps turning off.Transistor MPS1 keeps conducting while the voltage at node VOUT place slowly charges to the voltage at node VIN place.
Stage 3:PLOAD=1 and PWD_ST=1.The voltage at node PCLAMP place keeps the voltage equaling Node B G place to deduct across the voltage set by the pressure drop (such as, 5V) of Zener diode D1, and this is similarly the signal setting exported from reverser 144 and 146 logic low-voltage.The logic state change of signal PWD_ST causes transistor M4 conducting and (namely the voltage at Node B place be down to the voltage at node VPRL place, the voltage at node VIN place) deduct across the voltage set by the pressure drop (such as, 5V) of Zener diode D1.Buffering Nverter circuit 144 produces the signal with the logic high voltage of the voltage equaling node VPRL place at Node B 1 place in response to the voltage at Node B place, and Nverter circuit 146 produces the signal with the logic low-voltage of the voltage equaling node PCLAMP place at Node B 2 place.Transistor M2 turns off and transistor M1 conducting.The voltage at node VPRL place equal now node VOUT place voltage (its in response to be applied to the switching of signal DrP of grid of transistor MP and boosted to the voltage higher than node VIN place).Voltage due to node VOUT place is boosted and at least equal the voltage at node VIN place, so transistor MPS1 is turned off.The logic low-voltage at Node B 2 place is further used as signal S6 and is applied with turn-on transistor MPS2.
Stage 4: but within the time period that the voltage at device shutdown node VOUT place is kept above the voltage at node VIN place, the voltage at node VOUT place causes transistor MPS1 to keep turning off.Owing to not drawing electric current from node VPRL, so the voltage at node VPRL place keeps by the excitation of transistor M1 the voltage equaling node VOUT place.PLOAD=0, therefore transistor M3 turns off.This causes the voltage at node VCLAMP place to equal the voltage (action by Node B G and pullup resistor R1) at node VOUT place.Signal DrP is set to the voltage at node VPRL place, and under this condition, transistor MP is turned off.
Circuit 130 advantageously utilizes the signal be associated with soft start.
In the emulation of the circuit of Fig. 6, the voltage at node VIN place is 3.7V.During the stage 1, the voltage at node VOUT place is 0V.The current drain in this simulated measurement stage 1 is approximately 3.8nA.The current drain that this emulation measures the stage 3 is further approximately 10nA.Therefore, notice that leakage current is very little.
Those skilled in the art will be gently intelligible, and while within the scope remaining in present disclosure, material and method can change to some extent.It is also to be understood that, this disclosure provides the inventive concept many applicatory beyond the concrete context for embodiment is described.Therefore, claims are intended to such process, machine, manufacture, material synthesis, device, method or step to be included within its scope.
Claims (16)
1. a circuit, is characterized in that, comprising:
Boost converter, has:
Input node;
Output node;
Rectifying transistor, to be coupling between described input node and described output node and to have body terminal;
The first transistor, is coupling between described input node and described body terminal; With
Transistor seconds, is coupling between described body terminal and described output node;
Soft starting circuit, is configured to receive soft-start signal and the first control signal generating the control terminal being applied to this rectifying transistor in response to described soft-start signal; And
Drive circuit, be configured to generate the second control signal of the control terminal being applied to described the first transistor, and be configured to further receive described soft-start signal and the 3rd control signal generating the control terminal being applied to described transistor seconds in response to described soft-start signal.
2. circuit according to claim 1, is characterized in that, described input node is arranged to and is connected to inductor and described output node is arranged to and is connected to capacitor.
3. circuit according to claim 1, is characterized in that, described soft-start signal comprises:
First enabling signal, described soft starting circuit encourages described rectifying transistor to charge to described output node in response to described first enabling signal by described first control signal; And
Second enabling signal, described soft starting circuit allows repeatedly to encourage described rectifying transistor to boost to the voltage at described output node place by described first control signal in response to described second enabling signal.
4. circuit according to claim 3, is characterized in that, described drive circuit be configured to described first enabling signal and described second enabling signal all effectively time encourage described transistor seconds by described 3rd control signal.
5. circuit according to claim 1, is characterized in that, the control terminal of described the first transistor is controlled by described second control signal by the voltage of described output node.
6. circuit according to claim 1, is characterized in that, comprises further:
First Nverter circuit, described first Nverter circuit has as the 3rd control signal and is coupled to the output of the described control terminal of described transistor seconds and has the first power supply terminal and the second power supply terminal;
Voltage control circuit, is configured to, in response to the output of described first Nverter circuit, one of the voltage at the voltage at described input terminal place or described lead-out terminal place is applied to described first power supply terminal; And
Clamp circuit, is configured to the voltage that the voltage from described body terminal draws to be applied to described second power supply terminal.
7. circuit according to claim 6, it is characterized in that, described soft-start signal comprises the first soft-start signal and the second soft-start signal, and wherein said clamp circuit is controlled in response to described first soft-start signal and wherein said first Nverter circuit is controlled in response to described second soft-start signal.
8. circuit according to claim 7, it is characterized in that, comprise the second Nverter circuit further, described second Nverter circuit has the output of the input being coupled to described first Nverter circuit, and wherein said voltage control circuit responds the output of described second Nverter circuit further and wherein said second Nverter circuit is controlled in response to described second soft-start signal.
9. circuit according to claim 6, it is characterized in that, described first power supply terminal is logic high signal supply terminal and described second power supply terminal is logic low signal supply terminal, and described 3rd control signal has the voltage from described logic low supply terminal when encouraging described transistor seconds.
10. a circuit, is characterized in that, comprising:
Booster circuit, comprises the rectifying transistor with the first Lead-through terminal and the second Lead-through terminal and body terminal; Be coupling in the first transistor between described first Lead-through terminal and described body terminal; And the transistor seconds be coupling between described body terminal and the second Lead-through terminal; And
Control circuit, be configured to control the operation of described booster circuit, described control circuit comprises:
Soft starting circuit, be configured to receive the first soft-start signal of instruction load phase and indicate second soft-start signal in the pulsed drive stage after described load phase, described soft starting circuit can operate with in response to described first soft starting circuit described in the duration underexcitation of described load phase rectifying transistor, and can to operate further with transport pulse signal during the described pulsed drive stage to control the excitation of described rectifying transistor; With
Body control circuit, be configured to the excitation to described the first transistor and described transistor seconds in response to described first soft-start signal and described second soft-start signal control, described body control circuit can operate to encourage described the first transistor when described first soft-start signal is effective and described second soft-start signal is invalid and described transistor seconds of stopping using, and can operate to stop using described the first transistor and encourage described transistor seconds when described second soft-start signal is effective further.
11. circuit according to claim 10, it is characterized in that, comprise the output node of described second Lead-through terminal being coupled to described rectifying transistor further, described body control circuit comprises the circuit being configured to the described control terminal described output node being coupled to described the first transistor.
12. circuit according to claim 10, it is characterized in that, comprise clamp voltage generator circuit further, there is the supply node of the described body terminal being coupled to described rectifying transistor and be configured to generate the clamp voltage as the function of the logic state of described first soft-start signal.
13. circuit according to claim 12, it is characterized in that, comprise the first Nverter circuit further, there is logic height supply node, logic low supply node, be configured to generate the output node for the control signal controlled the excitation of described transistor seconds; Wherein said clamp voltage is applied to described logic low supply node.
14. circuit according to claim 13, is characterized in that, comprise voltage control circuit further, are configured to select the first voltage or the second voltage to be applied to described logic height supply node in response to described control signal.
15. circuit according to claim 14, is characterized in that, described first voltage is the voltage of the output of described booster circuit and described second voltage is the voltage of the input of described booster circuit.
16. circuit according to claim 14, is characterized in that, the input of described reverser is configured to receive the signal drawn from described second soft-start signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420509516.4U CN204290716U (en) | 2014-08-29 | 2014-08-29 | A kind of circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420509516.4U CN204290716U (en) | 2014-08-29 | 2014-08-29 | A kind of circuit |
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| Publication Number | Publication Date |
|---|---|
| CN204290716U true CN204290716U (en) | 2015-04-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420509516.4U Withdrawn - After Issue CN204290716U (en) | 2014-08-29 | 2014-08-29 | A kind of circuit |
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| CN (1) | CN204290716U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105375758A (en) * | 2014-08-29 | 2016-03-02 | 意法半导体研发(深圳)有限公司 | Boost converter possessing circuit of controlling body of boost output rectification transistor and method |
-
2014
- 2014-08-29 CN CN201420509516.4U patent/CN204290716U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105375758A (en) * | 2014-08-29 | 2016-03-02 | 意法半导体研发(深圳)有限公司 | Boost converter possessing circuit of controlling body of boost output rectification transistor and method |
| CN105375758B (en) * | 2014-08-29 | 2019-06-14 | 意法半导体研发(深圳)有限公司 | Circuit for power conversion and method for power conversion |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20150422 Effective date of abandoning: 20190614 |