CN204258621U - Reduce switch electromagnetic interference adjusting device - Google Patents
Reduce switch electromagnetic interference adjusting device Download PDFInfo
- Publication number
- CN204258621U CN204258621U CN201420843157.6U CN201420843157U CN204258621U CN 204258621 U CN204258621 U CN 204258621U CN 201420843157 U CN201420843157 U CN 201420843157U CN 204258621 U CN204258621 U CN 204258621U
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- Prior art keywords
- pmos
- tube
- nmos tube
- resistance
- termination
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Abstract
The utility model discloses a kind of reduction switch electromagnetic interference adjusting device.Reduce switch electromagnetic interference adjusting device and comprise error amplifier, pulse-width modulation circuit, the first resistance, the first electric capacity, the first PMOS, the first NMOS tube, power tube, the second PMOS, the second NMOS tube, the second resistance, the second electric capacity, the 3rd PMOS, the 3rd NMOS tube, lock-in tube, energy storage inductor, filter capacitor, the 3rd resistance and the 4th resistance.The device utilizing the utility model to provide can reduce power tube and the electromagnetic interference of lock-in tube when on off state.
Description
Technical field
The utility model relates to electromagnetic interference technology, refers more particularly to the electromagnetic interference adjusting device when on off state.
Background technology
In switch power supply system, high-tension overshoot voltage can be caused during the conducting of power tube and lock-in tube, make the damage of power tube and lock-in tube on the one hand, the electromagnetic interference of system can be produced on the other hand, be provided with the adjusting device reducing switch electromagnetic interference for this reason.
Summary of the invention
The utility model is intended to solve the deficiencies in the prior art, provides a kind of and reduces power tube and the electromagnetic interference adjusting device of lock-in tube when on off state.
Reduce switch electromagnetic interference adjusting device, comprise error amplifier, pulse-width modulation circuit, the first resistance, the first electric capacity, the first PMOS, the first NMOS tube, power tube, the second PMOS, the second NMOS tube, the second resistance, the second electric capacity, the 3rd PMOS, the 3rd NMOS tube, lock-in tube, energy storage inductor, filter capacitor, the 3rd resistance and the 4th resistance:
Described error amplifier amplifies the difference of the feedback voltage produced through described 3rd resistance and described 4th electric resistance partial pressure and reference voltage V REF;
Described pulse-width modulation circuit is that the size of the voltage produced according to described error amplifier produces pulse-width signal;
Described first resistance and described first electric capacity are connected into parallel connection, a termination power VCC, and the other end produces internal electric source VCCR;
Described second resistance and described second electric capacity are connected into parallel connection, one end ground connection GND, and the other end produces internally GNDR;
Described first PMOS and described first NMOS tube are connected into power tube described in inverter drive, and the source electrode of described first PMOS meets internal electric source VCCR, and the source electrode of described first NMOS tube meets internally GNDR;
Described power tube carries out energy storage to described energy storage inductor, and output current;
Described second PMOS and described second NMOS tube are connected into the inverter that the 3rd PMOS described in inverter drive and described 3rd NMOS tube are connected into, and the source electrode of described second PMOS meets internal electric source VCCR, and the source electrode of described second NMOS tube meets internally GNDR;
Described 3rd PMOS and described 3rd NMOS tube are connected into lock-in tube described in inverter drive, and the source electrode of described 3rd PMOS meets internal electric source VCCR, and the source electrode of described 3rd NMOS tube meets internally GNDR;
Described lock-in tube is in order to described energy storage inductor afterflow;
Described energy storage inductor carries out energy storage to the electric current that described power tube flows through, and carries out afterflow to the electric current that described lock-in tube flows through;
Described filter capacitor carries out filtering to the voltage that described energy storage inductor exports and produces direct voltage;
Described 3rd resistance becomes dividing potential drop feedback resistance to be carry out dividing potential drop to output voltage to feed back to described error amplifier with described 4th resistor group.
One end of 3rd resistance described in the negative input termination of described error amplifier and one end of described 4th resistance, positive input termination reference voltage V REF, exports pulse-width modulation circuit described in termination;
The output of error amplifier described in described pulse-width modulation circuit input termination, exports the grid of the first PMOS described in termination and the grid of the grid of described first NMOS tube and described second PMOS and the grid of described second NMOS tube;
Described in the input termination that described first PMOS and described second NMOS tube are connected into inverter, the output of pulse-width modulation circuit, exports the grid of power tube described in termination;
Described in the input termination that described second PMOS and described second NMOS tube are connected into inverter, the output of pulse-width modulation circuit, exports the grid of the 3rd PMOS and the grid of described 3rd NMOS tube described in termination;
Described in the input termination that described 3rd PMOS and described 3rd NMOS tube are connected into inverter, the second PMOS and described second NMOS tube are connected into the output of inverter, export the grid of lock-in tube described in termination;
The grid of described power tube connects the output that described first PMOS and described second NMOS tube are connected into inverter, and source electrode meets input power VCC, and drain electrode connects one end of described energy storage inductor and the drain electrode of described lock-in tube;
The grid of described lock-in tube connects the output that described 3rd PMOS and described 3rd NMOS tube are connected into inverter, and drain electrode connects the drain electrode of described power tube and one end of described energy storage inductor, source ground;
The drain electrode of power tube described in one termination of described energy storage inductor and the drain electrode of described lock-in tube, the other end is one end of the output of device and one end of described filter capacitor and described 3rd resistance, the other end ground connection of described filter capacitor;
The output of one terminating set of described 3rd resistance and one end of one end of described energy storage inductor and described filter capacitor, one end of the 4th resistance described in another termination and the negative input end of described error amplifier, the other end ground connection of described 4th resistance.
After powering on, input power VCC passes through described power tube to described energy storage inductor output current, the feedback voltage that output voltage VO UT obtains through described 3rd resistance and described 4th electric resistance partial pressure and reference voltage V REF amplify through described error amplifier the duty ratio that the error voltage signal obtained determines the pulse that described pulse-width modulation circuit exports, thus determine inductive current; The change of feedback voltage will cause the change driving described power tube signal dutyfactor by described error amplifier, thus controls the conducting of described power tube and deadline to reach the object of voltage stabilizing.
The magnitude of voltage of internal electric source VCCR is determined by the resistance value of described first resistance, it is larger that the resistance value of described first resistance drops to more greatly described first ohmically voltage, drive the rise time of described power tube to increase, large overshoot voltage would not be had like this to produce; Described first electric capacity has the effect absorbing electric charge simultaneously, offsets overshoot voltage further, also can reduce electromagnetic interference; Internally the magnitude of voltage of GNDR is determined by the resistance value of described second resistance, makes internally GNDR equal zero volt, can make also can increase the fall time of described power tube like this, also can reduce electromagnetic interference; In like manner, drive described lock-in tube to be also such process, electromagnetic interference can be reduced in driving process.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of reduction switch electromagnetic interference adjusting device of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model content is further illustrated.
Reduce switch electromagnetic interference adjusting device, as shown in Figure 1, error amplifier 101, pulse-width modulation circuit 102, first resistance 103, first electric capacity 104, first PMOS 105, first NMOS tube 106, power tube 107, second PMOS 108, second NMOS tube 109, second resistance 110, second electric capacity 111, the 3rd PMOS 112, the 3rd NMOS tube 113, lock-in tube 114, energy storage inductor 115, filter capacitor 116, the 3rd resistance 117 and the 4th resistance 118 is comprised:
Described error amplifier 101 amplifies the difference of the feedback voltage produced through described 3rd resistance 117 and described 4th resistance 118 dividing potential drop and reference voltage V REF;
Described pulse-width modulation circuit 102 is that the size of the voltage produced according to described error amplifier 101 produces pulse-width signal;
Described first resistance 103 and described first electric capacity 104 are connected into parallel connection, a termination power VCC, and the other end produces internal electric source VCCR;
Described second resistance 110 and described second electric capacity 111 are connected into parallel connection, one end ground connection GND, and the other end produces internally GNDR;
Described first PMOS 105 and described first NMOS tube 106 are connected into power tube 107 described in inverter drive, and the source electrode of described first PMOS 105 meets internal electric source VCCR, and the source electrode of described first NMOS tube 106 meets internally GNDR;
Described power tube 107 carries out energy storage to described energy storage inductor 115, and output current;
Described second PMOS 108 and described second NMOS tube 109 are connected into the inverter that the 3rd PMOS 112 described in inverter drive and described 3rd NMOS tube 113 are connected into, the source electrode of described second PMOS 108 meets internal electric source VCCR, and the source electrode of described second NMOS tube 109 meets internally GNDR;
Described 3rd PMOS 112 and described 3rd NMOS tube 113 are connected into lock-in tube 114 described in inverter drive, and the source electrode of described 3rd PMOS 112 meets internal electric source VCCR, and the source electrode of described 3rd NMOS tube 113 meets internally GNDR;
Described lock-in tube 114 is in order to the afterflow of described energy storage inductor 114;
Described energy storage inductor 115 carries out energy storage to the electric current that described power tube 107 flows through, and carries out afterflow to the electric current that described lock-in tube 114 flows through;
Described filter capacitor 116 carries out filtering to the voltage that described energy storage inductor 115 exports and produces direct voltage;
It is carry out dividing potential drop to output voltage to feed back to described error amplifier 101 that described 3rd resistance 117 and described 4th resistance 118 form dividing potential drop feedback resistance.
One end of 3rd resistance 117 described in the negative input termination of described error amplifier 101 and one end of described 4th resistance 118, positive input termination reference voltage V REF, exports pulse-width modulation circuit 102 described in termination;
Described pulse-width modulation circuit 102 inputs the output of error amplifier 101 described in termination, exports the grid of the first PMOS 105 described in termination and the grid of the grid of described first NMOS tube 106 and described second PMOS 108 and the grid of described second NMOS tube 109;
Described in the input termination that described first PMOS 105 and described second NMOS tube 106 are connected into inverter, the output of pulse-width modulation circuit 102, exports the grid of power tube 107 described in termination;
Described in the input termination that described second PMOS 108 and described second NMOS tube 109 are connected into inverter, the output of pulse-width modulation circuit 102, exports the grid of the 3rd PMOS 112 and the grid of described 3rd NMOS tube 113 described in termination;
Described in the input termination that described 3rd PMOS 112 and described 3rd NMOS tube 113 are connected into inverter, the second PMOS 108 and described second NMOS tube 109 are connected into the output of inverter, export the grid of lock-in tube 114 described in termination;
The grid of described power tube 107 connects the output that described first PMOS 105 and described second NMOS tube 106 are connected into inverter, and source electrode meets input power VCC, and drain electrode connects one end of described energy storage inductor 115 and the drain electrode of described lock-in tube 114;
The grid of described lock-in tube 114 connects the output that described 3rd PMOS 112 and described 3rd NMOS tube 113 are connected into inverter, and drain electrode connects the drain electrode of described power tube 107 and one end of described energy storage inductor 115, source ground;
The drain electrode of power tube 107 described in one termination of described energy storage inductor 115 and the drain electrode of described lock-in tube 114, the other end is one end of the output of device and one end of described filter capacitor 116 and described 3rd resistance 117, the other end ground connection of described filter capacitor 116;
The output of one terminating set of described 3rd resistance 117 and one end of one end of described energy storage inductor 115 and described filter capacitor 116, one end of 4th resistance 118 described in another termination and the negative input end of described error amplifier 101, the other end ground connection of described 4th resistance 118.
After powering on, input power VCC passes through described power tube 107 to described energy storage inductor 115 output current, the feedback voltage that output voltage VO UT obtains through described 3rd resistance 117 and described 4th resistance 118 dividing potential drop and reference voltage V REF amplify through described error amplifier 101 duty ratio that the error voltage signal obtained determines the pulse that described pulse-width modulation circuit 102 exports, thus determine inductive current; The change of feedback voltage will cause the change driving described power tube 107 signal dutyfactor by described error amplifier 101, thus controls the conducting of described power tube 107 and deadline to reach the object of voltage stabilizing.
The magnitude of voltage of internal electric source VCCR is determined by the resistance value of described first resistance 103, the voltage that the resistance value of described first resistance 103 drops to more greatly on described first resistance 103 is larger, drive the rise time of described power tube 107 to increase, large overshoot voltage would not be had like this to produce; Described first electric capacity 104 has the effect absorbing electric charge simultaneously, offsets overshoot voltage further, also can reduce electromagnetic interference; Internally the magnitude of voltage of GNDR is determined by the resistance value of described second resistance 110, makes internally GNDR equal zero volt, can make also can increase the fall time of described power tube 107 like this, also can reduce electromagnetic interference; In like manner, drive described lock-in tube 114 to be also such process, electromagnetic interference can be reduced in driving process.
Claims (1)
1. reduce switch electromagnetic interference adjusting device, it is characterized in that comprising error amplifier, pulse-width modulation circuit, the first resistance, the first electric capacity, the first PMOS, the first NMOS tube, power tube, the second PMOS, the second NMOS tube, the second resistance, the second electric capacity, the 3rd PMOS, the 3rd NMOS tube, lock-in tube, energy storage inductor, filter capacitor, the 3rd resistance and the 4th resistance:
Described first resistance and described first electric capacity are connected into parallel connection, a termination power VCC, and the other end produces internal electric source VCCR;
Described second resistance and described second electric capacity are connected into parallel connection, one end ground connection GND, and the other end produces internally GNDR;
Described first PMOS and described first NMOS tube are connected into power tube described in inverter drive, and the source electrode of described first PMOS meets internal electric source VCCR, and the source electrode of described first NMOS tube meets internally GNDR;
Described second PMOS and described second NMOS tube are connected into the inverter that the 3rd PMOS described in inverter drive and described 3rd NMOS tube are connected into, and the source electrode of described second PMOS meets internal electric source VCCR, and the source electrode of described second NMOS tube meets internally GNDR;
Described 3rd PMOS and described 3rd NMOS tube are connected into lock-in tube described in inverter drive, and the source electrode of described 3rd PMOS meets internal electric source VCCR, and the source electrode of described 3rd NMOS tube meets internally GNDR;
One end of 3rd resistance described in the negative input termination of described error amplifier and one end of described 4th resistance, positive input termination reference voltage V REF, exports pulse-width modulation circuit described in termination;
The output of error amplifier described in described pulse-width modulation circuit input termination, exports the grid of the first PMOS described in termination and the grid of the grid of described first NMOS tube and described second PMOS and the grid of described second NMOS tube;
Described in the input termination that described first PMOS and described second NMOS tube are connected into inverter, the output of pulse-width modulation circuit, exports the grid of power tube described in termination;
Described in the input termination that described second PMOS and described second NMOS tube are connected into inverter, the output of pulse-width modulation circuit, exports the grid of the 3rd PMOS and the grid of described 3rd NMOS tube described in termination;
Described in the input termination that described 3rd PMOS and described 3rd NMOS tube are connected into inverter, the second PMOS and described second NMOS tube are connected into the output of inverter, export the grid of lock-in tube described in termination;
The grid of described power tube connects the output that described first PMOS and described second NMOS tube are connected into inverter, and source electrode meets input power VCC, and drain electrode connects one end of described energy storage inductor and the drain electrode of described lock-in tube;
The grid of described lock-in tube connects the output that described 3rd PMOS and described 3rd NMOS tube are connected into inverter, and drain electrode connects the drain electrode of described power tube and one end of described energy storage inductor, source ground;
The drain electrode of power tube described in one termination of described energy storage inductor and the drain electrode of described lock-in tube, the other end is one end of the output of device and one end of described filter capacitor and described 3rd resistance, the other end ground connection of described filter capacitor;
The output of one terminating set of described 3rd resistance and one end of one end of described energy storage inductor and described filter capacitor, one end of the 4th resistance described in another termination and the negative input end of described error amplifier, the other end ground connection of described 4th resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420843157.6U CN204258621U (en) | 2014-12-25 | 2014-12-25 | Reduce switch electromagnetic interference adjusting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420843157.6U CN204258621U (en) | 2014-12-25 | 2014-12-25 | Reduce switch electromagnetic interference adjusting device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204258621U true CN204258621U (en) | 2015-04-08 |
Family
ID=52962884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420843157.6U Expired - Fee Related CN204258621U (en) | 2014-12-25 | 2014-12-25 | Reduce switch electromagnetic interference adjusting device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204258621U (en) |
-
2014
- 2014-12-25 CN CN201420843157.6U patent/CN204258621U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150408 Termination date: 20151225 |
|
| EXPY | Termination of patent right or utility model |