CN204256734U

CN204256734U - Peripheral interface expanding unit

Info

Publication number: CN204256734U
Application number: CN201420769107.8U
Authority: CN
Inventors: 曾欢; 李亿博; 陈正伟; 何代钦; 丁莉; 鲍晓伟; 刘月
Original assignee: Beijing BNC Technologies Co Ltd
Current assignee: Beijing BNC Technologies Co Ltd
Priority date: 2014-12-09
Filing date: 2014-12-09
Publication date: 2015-04-08
Anticipated expiration: 2024-12-09

Abstract

The utility model relates to a kind of peripheral interface expanding unit, and described PS2 peripheral interface expanding unit comprises: strengthen RISC performance optimization processor P owerPC, on-site programmable gate array FPGA and input and output I/O control chip; Described PowerPC is connected by local bus controller LBC and FPGA, and described FPGA is connected with described extended chip by low pin count lpc bus, by described extended chip expansion peripheral interface.The utility model peripheral interface expanding unit connects FPGA at the local bus LBC by PowerPC processor and connects extended chip by lpc bus again, thus expands multichannel peripheral interface easily.

Description

Peripheral interface expanding unit

Technical field

The utility model relates to a kind of peripheral interface expanding unit, particularly relates to a kind of device from PowerPC expansion interface.

Background technology

The full name of PowerPC is Performance Optimization With Enhanced RISCPerformance Computing, and being also called for short PPC, is the central processing unit of a kind of reduced instruction set computer (RISC) framework.

PowerPC is used in Communication Control field usually as the flush bonding processor of reduced instruction set computer, and its display performance is often more weak, and the support of corresponding hardware and software is also all more weak.But need under some special screne to use PowerPC processor, and embedded video card will be expanded by its PCI-E interface and do figure display interface, also need the function expanding mouse-keyboard accordingly.Interface for expanding mouse-keyboard has USB (universal serial bus) (Universal Serial Bus, and PS2 (Personal System2 USB), ps 2) two kinds of interfaces, PS/2 interface compares USB interface the advantage that transmission range is long, this meets the scene that we use, therefore needs from PowerPC processor expansion PS2 interface.

The existing mode poor stability from PowerPC processor expansion PS/2 interface, or, Macintosh use-pattern can not be supported.And some processor cannot directly expand PS2 interface.

Utility model content

The purpose of this utility model is the defect for prior art, provides a kind of peripheral interface expanding unit, to realize expanding peripheral interface easily from PowerPC.

For achieving the above object, the utility model provides a kind of peripheral interface expanding unit, and described PS2 peripheral interface expanding unit comprises: strengthen RISC performance optimization processor P owerPC, on-site programmable gate array FPGA and input and output I/O control chip;

Described PowerPC is connected by local bus controller LBC and FPGA, and described FPGA is connected with described extended chip by low pin count lpc bus, by described extended chip expansion peripheral interface.

Further, described I/O control chip is specially W83627HG chip.

Further, described peripheral interface is general-purpose serial bus USB interface, ps PS/2 interface or UART Universal Asynchronous Receiver Transmitter UART interface.

The utility model peripheral interface expanding unit connects FPGA at the local bus LBC by PowerPC processor and connects extended chip by lpc bus again, thus expands multichannel peripheral interface easily.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of the utility model peripheral interface expanding unit.

Embodiment

Below by drawings and Examples, the technical solution of the utility model is described in further detail.

Fig. 1 is the schematic diagram of the utility model peripheral interface expanding unit, as shown in the figure, the utility model specifically comprises: PowerPC1, field programmable gate array (Field-Programmable Gate Array, FPGA) 2 and input and output (Input/Output, I/O) control chip 3.

PowerPC1 is connected by local bus controller LBC and FPGA2, and FPGA2 is connected with I/O control chip 3 by low pin count (Low pin count Bus, LPC) bus, expands peripheral interface by I/O control chip 3.

Concrete, I/O control chip 3 provide to and serial ports, PS2 mouth, USB port, and the management of cpu fan etc. and support, such as I/O control chip can be specially W83627HG chip.Lpc bus is for being connected to CPU low bandwidth devices and " old ".Common low-speed device has: BIOS, serial ports, parallel port, the keyboard of PS/2 and mouse, Floppy Disk Controller, and newer equipment has credible platform module.Lpc bus is connected with the south bridge physics on mainboard usually, and south bridge is usually connected to a series of " old " equipment on IBM PC AT platform, such as two programmable interrupt controller, programmable interval timer and two ISADMA controllers.Lpc bus is that Intel introduces as the substitute of Industry Standard Architecture system (ISA) 1998 time, it and ISA are similar at software view, although have huge different at physical layer, ISA is 16 bit widths, 8.33MHz bus, and it is 4 bit widths, there is the bus of quadruple rate (33.3MHz).The maximum advantage of lpc bus only needs 7 signals, and crowded modern mainboard is easy to layout.

Further, run built-in Linux operating system by PowerPC processor P 1022, by video card output display interface on display, run QT interface program.PowerPC processor extends W83627HG chip by FPGA, and obtain PS2 mouse-keyboard interface, mouse can operate the cursor on display interface, and keyboard can at display interface inputing characters.

And peripheral interface can be USB interface, PS/2 or UART Universal Asynchronous Receiver Transmitter (UniversalAsynchronous Receiver and Transmitter, UART) interface etc.

The utility model peripheral interface expanding unit connects FPGA by the local bus LBC of PowerPC processor P 1022 and expands the peripheral interfaces such as PS2 by lpc bus connection W83627HG chip again, W83627HG chip can also expand other interfaces such as UART, USB except expanding PS2 interface, but the utility model emphasis will solve PS2 interface problem.The utility model solves in some special industrial applications, utilize PowerPC processor by the local bus expansion lpc bus chip of self, realize peripheral interface, such as PS2 interface, finally realize reliable and stable, meet application scheme industrial and requirement, (about 10 meters) mouse-keyboard at a distance.

Professional should recognize further, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present utility model.

The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.

Above-described embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; be understood that; the foregoing is only embodiment of the present utility model; and be not used in restriction protection domain of the present utility model; all within spirit of the present utility model and principle, any amendment made, equivalent replacement, improvement etc., all should be included within protection domain of the present utility model.

Claims

1. a peripheral interface expanding unit, is characterized in that, described PS2 peripheral interface expanding unit comprises: strengthen RISC performance optimization processor P owerPC, on-site programmable gate array FPGA and input and output I/O control chip;

2. peripheral interface expanding unit according to claim 1, is characterized in that, described I/O control chip is specially W83627HG chip.

3. peripheral interface expanding unit according to claim 1, is characterized in that, described peripheral interface is general-purpose serial bus USB interface, ps PS/2 interface or UART Universal Asynchronous Receiver Transmitter UART interface.