CN204244167U - Anti-PID device in a kind of many level photovoltaic generating system - Google Patents
Anti-PID device in a kind of many level photovoltaic generating system Download PDFInfo
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- CN204244167U CN204244167U CN201420689607.0U CN201420689607U CN204244167U CN 204244167 U CN204244167 U CN 204244167U CN 201420689607 U CN201420689607 U CN 201420689607U CN 204244167 U CN204244167 U CN 204244167U
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Abstract
The utility model provides the anti-PID device in a kind of many level photovoltaic generating system, and the positive output end PV+ of PV array connects+1 level input of inverter, and the negative output terminal PV-of PV array connects-1 level input of inverter; Connect two equalizing capacitances of series connection between PV+ and PV-, the common port of two equalizing capacitances connects 0 level input of inverter; PV+ with PV-is connected all the other level input of inverter by Boost circuit; When PV-potential to ground can not be back bias voltage, pass through anti-PID circuit ground at the M level input of inverter; Anti-PID circuit comprises at least one in following device: diode, resistance, positive voltage source and normally closed switch.By regulating and controlling the DC bus electromotive force over the ground of inverter, indirect adjustments and controls PV array electromotive force over the ground, reduce the impact of PID effect.
Description
Technical field
The utility model relates to technical field of photovoltaic power generation, the anti-PID device particularly in a kind of many level photovoltaic generating system.
Background technology
PV array operation is when negative potential higher over the ground or positive potential, there will be photovoltaic battery panel open circuit voltage, short circuit current and fill factor, curve factor relevant parameter reduce, the phenomenon of decrease of power generation, the i.e. generation of so-called potential induction attenuation (PID, Potential Induced Degradation) phenomenon.It should be noted that, PV array comprises cell panel, can be series, parallel or the connection in series-parallel combination of multiple cell panel.
The positive potential that PV array is higher over the ground or negative potential are mainly because the DC side of inverter in the photovoltaic generating system reason such as to suspend over the ground formed.Therefore need to eliminate or reduce PV array positive potential over the ground or negative potential, thus the impact of PV array PID effect is down to minimum, guarantee the generating efficiency of photovoltaic generating system.
Therefore, those skilled in the art need to provide a kind of anti-PID device, are applied in many level photovoltaic generating system, reduce or avoid the PID phenomenon of PV array, thus improve the generating efficiency of photovoltaic generating system.
Utility model content
The technical problems to be solved in the utility model is to provide the anti-PID device in a kind of many level photovoltaic generating system, reduces or avoid the PID phenomenon of PV array, thus improves the generating efficiency of photovoltaic generating system.
The utility model provides the anti-PID device in a kind of many level photovoltaic generating system, and be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV-potential to ground can not be back bias voltage, at the M level input of described inverter by anti-PID circuit ground, described M be less than-1 negative integer; Described anti-PID circuit comprises at least one in following device: diode, resistance, positive voltage source and normally closed switch;
When comprising diode, closely, the negative electrode of described diode is near the input of described M level for the anode of described diode.
The utility model also provides the anti-PID device in a kind of many level photovoltaic generating system, and be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV-potential to ground can not be positive bias, at the M level input of described inverter by anti-PID circuit ground, described M be less than-1 negative integer; Described anti-PID circuit comprises: negative voltage source.
Preferably, described anti-PID circuit also comprises at least one in the following device of connecting with described negative voltage source: diode, resistance and normally closed switch;
When comprising described diode, the anode of described diode is near described M level input, and the negative electrode of described diode closely.
The utility model also provides the anti-PID device in a kind of many level photovoltaic generating system, and be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV+ potential to ground can not be back bias voltage, at the Q level input of described inverter by anti-PID circuit ground, described Q be greater than 1 positive integer; Described anti-PID circuit comprises: positive voltage source.
Preferably, described anti-PID circuit also comprises at least one in the following device of connecting with described positive voltage source: diode, resistance, normally closed switch;
When described anti-PID circuit comprises diode, closely, the negative electrode of described diode is near the input of the Q level of described inverter for the anode of described diode.
The utility model also provides the anti-PID device in a kind of many level photovoltaic generating system, and be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV+ potential to ground can not be positive bias, at the Q level input of described inverter by anti-PID circuit ground, described Q be greater than 1 positive integer; Described anti-PID circuit comprises at least one in following device: diode, resistance, negative voltage source and normally closed switch;
When comprising diode, the anode of described diode is near described Q level input, and the negative electrode of described diode closely.
The utility model also provides the anti-PID device in a kind of many level photovoltaic generating system, and be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV-potential to ground can not be back bias voltage, pass through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: positive voltage source, and the amplitude of described positive voltage source is more than or equal to the magnitude of voltage between described inverter 0 level input and-1 level input; When PV+ potential to ground can not be back bias voltage, pass through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: voltage source, and the amplitude of described voltage source is more than or equal to the magnitude of voltage between described inverter 0 level input and+1 level input.
Preferably, described anti-PID circuit also comprises at least one in the following device of connecting with described positive voltage source: diode, resistance and normally closed switch;
When described anti-PID circuit comprises described diode, the negative electrode of described diode is near 0 level input of described inverter, and the anode of described diode closely.
The utility model also provides the anti-PID device in a kind of many level photovoltaic generating system, and be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV-potential to ground can not be positive bias, pass through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: voltage source, and the amplitude of described voltage source is less than or equal to the magnitude of voltage between described inverter 0 level input and-1 level input;
When PV+ potential to ground can not be positive bias, pass through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: voltage source, and the amplitude of described voltage source is less than or equal to the magnitude of voltage between described inverter 0 level input and+1 level input.
Preferably, described anti-PID circuit also comprises at least one in the following device of connecting with described voltage source: diode, resistance and normally closed switch;
When described anti-PID circuit comprises described diode, the anode of described diode is near 0 level input of described inverter, and the negative electrode of described diode closely.
Compared with prior art, the utility model has the following advantages:
The anti-PID device that the utility model provides, be connected on the DC bus of inverter by simple anti-PID circuit, the DC bus electromotive force over the ground of regulation and control inverter, thus indirect adjustments and controls PV array electromotive force over the ground, reduce PV array positive potential over the ground or negative potential, the impact of the PID effect of PV array is down to minimum, thus guarantees the efficiency of photovoltaic generation.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is anti-PID device embodiment one schematic diagram in many level photovoltaic generating system of providing of the utility model;
Fig. 2 is many level photovoltaic generating system schematic diagram that the utility model provides;
Fig. 3 is anti-PID device embodiment two schematic diagram in many level photovoltaic generating system of providing of the utility model;
Fig. 4 is anti-PID device embodiment three schematic diagram in many level photovoltaic generating system of providing of the utility model;
Fig. 5 is anti-PID device embodiment four schematic diagram in many level photovoltaic generating system of providing of the utility model;
Fig. 6 is anti-PID device embodiment five schematic diagram in many level photovoltaic generating system of providing of the utility model;
Fig. 7 is anti-PID device embodiment six schematic diagram in many level photovoltaic generating system of providing of the utility model.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.
For enabling above-mentioned purpose of the present utility model, feature and advantage become apparent more, are described in detail embodiment of the present utility model below in conjunction with accompanying drawing.
Embodiment one:
See Fig. 1, this figure is anti-PID device embodiment one schematic diagram in many level photovoltaic generating system of providing of the utility model.
Anti-PID device in many level photovoltaic generating system that the present embodiment provides, be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV-potential to ground can not be back bias voltage, pass through anti-PID circuit ground at the M level input of described inverter, described M is for being less than-1 negative integer; Described anti-PID circuit comprises at least one in following device: diode, resistance, positive voltage source and normally closed switch.
When comprising diode, closely, the negative electrode of described diode is near the input of described M level for the anode of described diode.
As shown in Figure 1, in Fig. 1 with N for 2, namely inverter is five-electrical level inverter is that example is introduced.Be understandable that, Boost circuit comprises two, if when the level grade of inverter is more, then corresponding Boost circuit can be more, and as shown in Figure 2, corresponding 2N+1 electrical level inverter needs (N-1) to Boost circuit.
As shown in Figure 1, when PV-potential to ground can not be back bias voltage, pass through anti-PID circuit ground at-2 level input of described inverter; Anti-PID circuit ground is passed through with-2 level input in Fig. 1.
It should be noted that, it can be any one in figure that described anti-PID circuit comprises:
The first: the direct ground connection of-2 level input;
The second :-2 level input are by diode ground connection, and the negative electrode of diode connects-2 level input, the plus earth of diode;
The third :-2 level input by series connection diode and grounding through resistance, the connected mode of diode is similar to the second, anode near ground connection, close-2 level input of negative electrode;
4th kind :-2 level input are by positive voltage source ground connection; Positive voltage source is voltage source, close-2 level input of anode of voltage source, and the negative terminal of voltage source closely;
5th kind :-2 level input pass through positive voltage source and the diode ground connection of series connection; Connected mode and the second of diode are similar; The connected mode of positive voltage source and the 4th kind similar;
6th kind :-2 level input pass through positive voltage source and the grounding through resistance of series connection;
7th kind: the resistance that-2 level input pass through to connect, diode and positive voltage source ground connection; Connected mode and the second of diode are similar, the connected mode of positive voltage source and the 4th kind similar.
A and the B two ends substituting anti-PID circuit with the physical circuit in square frame are only needed in Fig. 1.
For the connected mode wherein having voltage source, the magnitude of voltage by regulation voltage source changes the potential to ground of PV-indirectly.
Embodiment two:
See Fig. 3, this figure is anti-PID device embodiment two schematic diagram in many level photovoltaic generating system of providing of the utility model.
The present embodiment provides the anti-PID device in a kind of many level photovoltaic generating system, and be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV-potential to ground can not be positive bias, at the M level input of described inverter by anti-PID circuit ground, described M be less than-1 negative integer; Described anti-PID circuit comprises: negative voltage source.See the first connected mode in Fig. 3, namely negative voltage source is anti-PID circuit, and the negative pole of negative voltage source connects-2 level input, the plus earth of negative voltage source.Can ensure that PV-potential to ground is 0 or is negative voltage like this.
In addition, anti-PID circuit, except comprising negative voltage source, can also comprise at least one in the following device of connecting with described negative voltage source: diode, resistance and normally closed switch.When comprising described diode, the anode of described diode is near described M level input, and the negative electrode of described diode closely.Continue see Fig. 3, anti-PID circuit can be negative voltage source and the connecting of diode, and also can be negative voltage source and the connecting of resistance, also can be the series connection of negative voltage source and diode and resistance.Wherein, close-2 level input of anode of diode, the negative electrode of diode closely.A, the B of physical circuit in Fig. 3 in square frame hold A, the B receiving anti-PID circuit respectively to hold.Can by the potential to ground regulating the magnitude of voltage of negative voltage source indirectly to change PV-.
Embodiment three:
See Fig. 4, this figure is anti-PID device embodiment three schematic diagram in many level photovoltaic generating system of providing of the utility model.
Anti-PID device in a kind of many level photovoltaic generating system that the present embodiment provides, be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV+ potential to ground can not be back bias voltage, at the Q level input of described inverter by anti-PID circuit ground, described Q be greater than 1 positive integer; Described anti-PID circuit comprises positive voltage source.
For five-electrical level inverter ,+2 level input of inverter are by anti-PID circuit ground.
As in Fig. 4, be introduced by anti-PID circuit ground for+2 of five-electrical level inverter level input.
Be understandable that, the anti-PID circuit in the present embodiment, except comprising positive voltage source, can also comprise at least one in the following device of connecting with described positive voltage source: diode, resistance, normally closed switch;
When described anti-PID circuit comprises diode, closely, the negative electrode of described diode is near the input of the Q level of described inverter for the anode of described diode.Namely A, the B of seven kinds of physical circuits in square frame hold A, the B receiving anti-PID circuit respectively to hold.For the connected mode wherein having positive voltage source, by the electromotive force over the ground regulating the magnitude of voltage of positive voltage source indirectly to change PV-.
Embodiment four:
See Fig. 5, this figure is anti-PID device embodiment four schematic diagram in many level photovoltaic generating system of providing of the utility model.
The present embodiment provides the anti-PID device in a kind of many level photovoltaic generating system, and be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV+ potential to ground can not be positive bias, at the Q level input of described inverter by anti-PID circuit ground, described Q be greater than 1 positive integer; Described anti-PID circuit comprises: at least one in following device: diode, resistance, negative voltage source and normally closed switch.When comprising diode, the anode of described diode is near described Q level input, and the negative electrode of described diode closely.
In addition, anti-PID circuit, except comprising negative voltage source, can also comprise at least one in the following device of connecting with described negative voltage source: diode, resistance and normally closed switch.Continue see Fig. 3, anti-PID circuit can be negative voltage source and the connecting of diode, and also can be negative voltage source and the connecting of resistance, also can be the series connection of negative voltage source and diode and resistance.Wherein, close-2 level input of anode of diode, the negative electrode of diode closely.A, the B of physical circuit in Fig. 3 in square frame hold A, the B receiving anti-PID circuit respectively to hold.Can by the potential to ground regulating the magnitude of voltage of negative voltage source indirectly to change PV-.
Embodiment five:
See Fig. 6, this figure is anti-PID device embodiment five schematic diagram in many level photovoltaic generating system of providing of the utility model.
The present embodiment is introduced anti-PID circuit and is connected to situation between 0 level input of inverter and ground.
Anti-PID device in many level photovoltaic generating system that the present embodiment provides, be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
The first: when PV-potential to ground can not be back bias voltage, pass through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: positive voltage source, and the amplitude of described positive voltage source is more than or equal to the magnitude of voltage between described inverter 0 level input and-1 level input, and namely the voltage magnitude of positive voltage source is more than or equal to V1Neg.
The second: when PV+ potential to ground can not be back bias voltage, passes through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: voltage source, and the amplitude of described voltage source is more than or equal to the magnitude of voltage between described inverter 0 level input and+1 level input;
It should be noted that, the inside concrete structure of the anti-PID circuit that the first and the second provide can select first, second, third in the square frame shown in Fig. 5 and the 5th, namely except only comprising except voltage source, other resistance of connecting with voltage source, diode and normally closed switch (not shown) can also be comprised.
That is: described anti-PID circuit also comprises at least one in the following device of connecting with described positive voltage source: diode, resistance and normally closed switch;
When described anti-PID circuit comprises described diode, the negative electrode of described diode is near 0 level input of described inverter, and the anode of described diode closely.
The third: when PV-potential to ground can not be positive bias, pass through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: voltage source, and the amplitude of described voltage source is less than or equal to the magnitude of voltage between described inverter 0 level input and-1 level input; Namely the voltage magnitude of positive voltage source is less than or equal to the V1Neg of inverter;
4th kind: when PV+ potential to ground can not be positive bias, pass through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: voltage source, and the amplitude of described voltage source is less than or equal to the magnitude of voltage between inverter 0 level input and+1 level input; Namely the voltage magnitude of voltage source is less than or equal to-V1Pos.
It should be noted that, the inside concrete structure of the third and the 4th kind of anti-PID circuit provided can select in the square frame shown in Fig. 5 first, second, the 4th and the 6th, namely except only comprising except voltage source, other resistance of connecting with voltage source, diode and normally closed switch (not shown) can also be comprised.
That is, described anti-PID circuit also comprises at least one in the following device of connecting with described voltage source: diode, resistance and normally closed switch;
When described anti-PID circuit comprises described diode, the anode of described diode is near 0 level input of described inverter, and the negative electrode of described diode closely.
Be understandable that, when the first and the second comprise diode, when comprising diode with the third and the 4th kind, the connected mode of diode is distinguished to some extent.
It should be noted that, V1Neg in schematic diagram above in all embodiments represents the voltage of-1 level input for 0 level input of inverter, V2Neg represents the voltage of-2 level input for 0 level input of inverter, V1Pos represents the voltage of+1 level input for 0 level input of inverter, and V2Pos represents the voltage of+2 level inputs for 0 level input of inverter.
It should be noted that, all illustrate for an inverter in all embodiment corresponding diagram above, be understandable that, in photovoltaic generating system, sometimes be not only an inverter separate unit to run, also can be at least two inverter parallels, when multiple stage inverter parallel, only need the effect that described anti-PID circuit can ensure all to play whole system all PV array anti-PID effect to be installed in an inverter wherein.And the anti-PID circuit that above embodiment provides is equally applicable in the photovoltaic generating system of multiple stage inverter parallel, system shown in Figure 7.
The anti-PID device provided in above embodiment, be connected on the DC bus of inverter by detecting anti-PID circuit, the DC bus electromotive force over the ground of regulation and control inverter, thus indirect adjustments and controls PV array electromotive force over the ground, reduce PV array positive potential over the ground or negative potential, by near minimum for the impact of the PID effect of PV array, thus guarantee the efficiency of photovoltaic generation.
The above is only preferred embodiment of the present utility model, not does any pro forma restriction to the utility model.Although the utility model discloses as above with preferred embodiment, but and be not used to limit the utility model.Any those of ordinary skill in the art, do not departing under technical solutions of the utility model ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solutions of the utility model, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solutions of the utility model, according to technical spirit of the present utility model to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solutions of the utility model protection.
Claims (10)
1. the anti-PID device in the photovoltaic generating system of level more than, is characterized in that, be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV-potential to ground can not be back bias voltage, at the M level input of described inverter by anti-PID circuit ground, described M be less than-1 negative integer; Described anti-PID circuit comprises at least one in following device: diode, resistance, positive voltage source and normally closed switch;
When comprising diode, closely, the negative electrode of described diode is near the input of described M level for the anode of described diode.
2. the anti-PID device in the photovoltaic generating system of level more than, is characterized in that, be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV-potential to ground can not be positive bias, at the M level input of described inverter by anti-PID circuit ground, described M be less than-1 negative integer; Described anti-PID circuit comprises: negative voltage source.
3. the anti-PID device in many level photovoltaic generating system according to claim 2, is characterized in that, described anti-PID circuit also comprises at least one in the following device of connecting with described negative voltage source: diode, resistance and normally closed switch;
When comprising described diode, the anode of described diode is near described M level input, and the negative electrode of described diode closely.
4. the anti-PID device in the photovoltaic generating system of level more than, is characterized in that, be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV+ potential to ground can not be back bias voltage, at the Q level input of described inverter by anti-PID circuit ground, described Q be greater than 1 positive integer; Described anti-PID circuit comprises: positive voltage source.
5. the anti-PID device in many level photovoltaic generating system according to claim 4, is characterized in that, described anti-PID circuit also comprises at least one in the following device of connecting with described positive voltage source: diode, resistance, normally closed switch;
When described anti-PID circuit comprises diode, closely, the negative electrode of described diode is near the input of the Q level of described inverter for the anode of described diode.
6. the anti-PID device in the photovoltaic generating system of level more than, is characterized in that, be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV+ potential to ground can not be positive bias, at the Q level input of described inverter by anti-PID circuit ground, described Q be greater than 1 positive integer; Described anti-PID circuit comprises at least one in following device: diode, resistance, negative voltage source and normally closed switch;
When comprising diode, the anode of described diode is near described Q level input, and the negative electrode of described diode closely.
7. the anti-PID device in the photovoltaic generating system of level more than, is characterized in that, be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV-potential to ground can not be back bias voltage, pass through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: positive voltage source, and the amplitude of described positive voltage source is more than or equal to the magnitude of voltage between described inverter 0 level input and-1 level input; When PV+ potential to ground can not be back bias voltage, pass through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: voltage source, and the amplitude of described voltage source is more than or equal to the magnitude of voltage between described inverter 0 level input and+1 level input.
8. the anti-PID device in many level photovoltaic generating system according to claim 7, is characterized in that, described anti-PID circuit also comprises at least one in the following device of connecting with described positive voltage source: diode, resistance and normally closed switch;
When described anti-PID circuit comprises described diode, the negative electrode of described diode is near 0 level input of described inverter, and the anode of described diode closely.
9. the anti-PID device in the photovoltaic generating system of level more than, is characterized in that, be applied in many level photovoltaic generating system, this system comprises: 2N+1 electrical level inverter, PV array and Boost circuit; N is positive integer; The positive output end PV+ of described PV array connects+1 level input of described inverter, and the negative output terminal PV-of described PV array connects-1 level input of described inverter; Connect two equalizing capacitances of series connection between described PV+ and PV-, the common port of described two equalizing capacitances connects 0 level input of described inverter; Described PV+ with PV-is connected all the other level input of described inverter by described Boost circuit;
When PV-potential to ground can not be positive bias, pass through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: voltage source, and the amplitude of described voltage source is less than or equal to the magnitude of voltage between described inverter 0 level input and-1 level input;
When PV+ potential to ground can not be positive bias, pass through anti-PID circuit ground at 0 level input of described inverter; Described anti-PID circuit at least comprises: voltage source, and the amplitude of described voltage source is less than or equal to the magnitude of voltage between described inverter 0 level input and+1 level input.
10. the anti-PID device in many level photovoltaic generating system according to claim 9, is characterized in that, described anti-PID circuit also comprises at least one in the following device of connecting with described voltage source: diode, resistance and normally closed switch;
When described anti-PID circuit comprises described diode, the anode of described diode is near 0 level input of described inverter, and the negative electrode of described diode closely.
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| WO2015169135A1 (en) * | 2014-05-09 | 2015-11-12 | 阳光电源股份有限公司 | Anti-potential induced degradation photovoltaic power generation system, photovoltaic assembly and inverter |
| CN107196597A (en) * | 2017-05-16 | 2017-09-22 | 华为技术有限公司 | A kind of photovoltaic generating system |
| CN110474359A (en) * | 2018-05-10 | 2019-11-19 | 太阳能安吉科技有限公司 | Increase the system and method for the reliability and service life of photovoltaic (PV) module |
| CN113872241A (en) * | 2021-10-20 | 2021-12-31 | 固德威技术股份有限公司 | Grid-connected inverter system for preventing photovoltaic assembly potential induced attenuation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2015169135A1 (en) * | 2014-05-09 | 2015-11-12 | 阳光电源股份有限公司 | Anti-potential induced degradation photovoltaic power generation system, photovoltaic assembly and inverter |
| CN107196597A (en) * | 2017-05-16 | 2017-09-22 | 华为技术有限公司 | A kind of photovoltaic generating system |
| CN107196597B (en) * | 2017-05-16 | 2019-12-13 | 华为技术有限公司 | photovoltaic power generation system |
| CN110474359A (en) * | 2018-05-10 | 2019-11-19 | 太阳能安吉科技有限公司 | Increase the system and method for the reliability and service life of photovoltaic (PV) module |
| CN110474359B (en) * | 2018-05-10 | 2024-02-09 | 太阳能安吉科技有限公司 | System and method for increasing reliability and useful life of Photovoltaic (PV) modules |
| CN113872241A (en) * | 2021-10-20 | 2021-12-31 | 固德威技术股份有限公司 | Grid-connected inverter system for preventing photovoltaic assembly potential induced attenuation |
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