CN204206134U - A kind of high speed clocked comparator - Google Patents
A kind of high speed clocked comparator Download PDFInfo
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- CN204206134U CN204206134U CN201420604995.8U CN201420604995U CN204206134U CN 204206134 U CN204206134 U CN 204206134U CN 201420604995 U CN201420604995 U CN 201420604995U CN 204206134 U CN204206134 U CN 204206134U
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Abstract
The utility model relates to a kind of high speed clocked comparator, comprises pre-amplification stage circuit, clock circuit; In described pre-amplification stage circuit, input difference is after transistor M0 connects with differential input stage transistor M4 to the active load of pipe, is that transistor M1 and differential input stage transistor M5 are in parallel with the input difference of connecting to the active load of pipe; Described tail current source transistor M6 is connected with differential input stage transistor M4, differential input stage transistor M5 respectively; Described clock control transistor M11 is connected with tail current source transistor M6, and controls by clock circuit; Work when the signal CLK of clock circuit is high level, gather the voltage signal that differential input end need compare; When the signal CLK of clock circuit is low level, clock control transistor M11 closes, and pre-amplification stage circuit does not work, thus reduces power consumption; The utility model pre-amplification stage circuit controls alternation by clock circuit, reduces circuit power consumption.
Description
Technical field
It is low that the utility model relates to a kind of circuit power consumption, pre-amplification stage circuit, judges that level circuit controls the high speed clocked comparator of alternation by clock circuit.
Background technology
Comparator as the unit of Design of A/D Converter, its important performance index are operating rates, precision, power consumption, input offset voltage, positive feedback time produce kick back noise etc.Analog to digital converter proposes very high requirement to the operating rate of comparator and power consumption.At present, comparator more employing Dynamic latch structure, and Dynamic latch comparator has speed is high, power consumption is little feature.But the comparator of this structure but also exists and large kicks back noise, and input offset voltage is also larger.For this reason, it is low that we have developed a kind of circuit power consumption, pre-amplification stage circuit, judges that level circuit controls the high speed clocked comparator of alternation by clock circuit.
Utility model content
For the technical problem of above-mentioned existence, the purpose of this utility model is: propose a kind of circuit power consumption low, pre-amplification stage circuit, judges that level circuit controls the high speed clocked comparator of alternation by clock circuit.
Technical solution of the present utility model is achieved in that a kind of high speed clocked comparator, comprises pre-amplification stage circuit, clock circuit; Described pre-amplification stage circuit, comprise differential input stage transistor M4, differential input stage transistor M5, input difference to the active load of pipe be transistor M0, input difference to the active load of pipe be transistor M1, tail current source transistor M6, clock control transistor M11, secondary amplifier transistor M2, secondary amplifier transistor M3, secondary amplification active load be transistor M9, the active load of secondary amplification is transistor M10, clock control transistor M12; Described input difference is after transistor M0 connects with differential input stage transistor M4 to the active load of pipe, is that transistor M1 and differential input stage transistor M5 are in parallel with the input difference of connecting to the active load of pipe; Described tail current source transistor M6 is connected with differential input stage transistor M4, differential input stage transistor M5 respectively; Described clock control transistor M11 is connected with tail current source transistor M6, and controls by clock circuit; Described secondary amplifier transistor M2 and input difference are that transistor M0 is connected to the active load of pipe, simultaneously and be that transistor M10 is connected with the active load of secondary amplification; Described secondary amplifier transistor M3 and input difference are that transistor M1 is connected to the active load of pipe, simultaneously and be that transistor M9 is connected with the active load of secondary amplification; The active load of described secondary amplification is transistor M9, the active load of secondary amplification is that transistor M10 is connected with clock control transistor M12 respectively, and is subject to and controls by clock circuit; Work when the signal CLK of clock circuit is high level, gather the voltage signal that differential input end need compare; When the signal CLK of clock circuit is low level, clock control transistor M11, M12 close, and pre-amplification stage circuit does not work, thus reduces power consumption; Differential input stage transistor M4, M5 adopt minimum channel length to improve speed.
Preferably, described high speed clocked comparator, also comprises and judges level circuit, described judgement level circuit, comprises transistor M7, transistor M8, clock control transistor M14, clock control transistor M15; In parallel with the transistor M8 connected and clock control transistor M15 after described transistor M7 is connected with clock control transistor M14, the cross bonding of transistor M7, M8 grid, realizes positive feedback, to improve the gain of decision circuitry simultaneously; Described clock control transistor M14 is connected with secondary amplifier transistor M2; Described clock control transistor M15 is connected with secondary amplifier transistor M3; When the signal CLK of clock circuit is low level, clock control transistor M14, M15 conducting, judges level circuit working.
Preferably, described transistor M7, transistor M8 are connected with the transistor M13 of grid leak short circuit respectively.
Due to the utilization of technique scheme, the utility model compared with prior art has following advantages:
The pre-amplification stage circuit of high speed clocked comparator of the present utility model, judge that level circuit controls alternation by clock circuit, reduce circuit power consumption.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, technical solutions of the utility model are described further:
Accompanying drawing 1 is the circuit theory diagrams of high speed clocked comparator of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described.
Be high speed clocked comparator described in the utility model as shown in Figure 1, comprise pre-amplification stage circuit, judge level circuit, clock circuit; Described pre-amplification stage circuit, comprise differential input stage transistor M4, differential input stage transistor M5, input difference to the active load of pipe be transistor M0, input difference to the active load of pipe be transistor M1, tail current source transistor M6, clock control transistor M11, secondary amplifier transistor M2, secondary amplifier transistor M3, secondary amplification active load be transistor M9, the active load of secondary amplification is transistor M10, clock control transistor M12; Described input difference is after transistor M0 connects with differential input stage transistor M4 to the active load of pipe, is that transistor M1 and differential input stage transistor M5 are in parallel with the input difference of connecting to the active load of pipe; Described tail current source transistor M6 is connected with differential input stage transistor M4, differential input stage transistor M5 respectively; Described clock control transistor M11 is connected with tail current source transistor M6, and controls by clock circuit; Described secondary amplifier transistor M2 and input difference are that transistor M0 is connected to the active load of pipe, simultaneously and be that transistor M10 is connected with the active load of secondary amplification; Described secondary amplifier transistor M3 and input difference are that transistor M1 is connected to the active load of pipe, simultaneously and be that transistor M9 is connected with the active load of secondary amplification; The active load of described secondary amplification is transistor M9, the active load of secondary amplification is that transistor M10 is connected with clock control transistor M12 respectively, and is subject to and controls by clock circuit; Work when the signal CLK of clock circuit is high level, gather the voltage signal that differential input end need compare; When the signal CLK of clock circuit is low level, clock control transistor M11, M12 close, and pre-amplification stage circuit does not work, thus reduces power consumption; Differential input stage transistor M4, M5 adopt minimum channel length to improve speed.Described judgement level circuit, comprises transistor M7, transistor M8, clock control transistor M14, clock control transistor M15; In parallel with the transistor M8 connected and clock control transistor M15 after described transistor M7 is connected with clock control transistor M14, the cross bonding of transistor M7, M8 grid, realizes positive feedback, to improve the gain of decision circuitry simultaneously; Described clock control transistor M14 is connected with secondary amplifier transistor M2; Described clock control transistor M15 is connected with secondary amplifier transistor M3; Described transistor M7, transistor M8 are connected with the transistor M13 of grid leak short circuit respectively, the drain terminal current potential of transistor M7, M8 can be improved, reduce the size of transistor M2, M3, improve speed, the drain terminal electric current of M2, M3 reduces thereupon, thus lower power consumption; When the signal CLK of clock circuit is low level, clock control transistor M14, M15 conducting, judges level circuit working.
Due to the utilization of technique scheme, the utility model compared with prior art has following advantages:
The pre-amplification stage circuit of high speed clocked comparator of the present utility model, judge that level circuit controls alternation by clock circuit, reduce circuit power consumption.
Below be only embody rule example of the present utility model, protection range of the present utility model is not constituted any limitation.The technical scheme that all employing equivalents or equivalence are replaced and formed, all drops within the utility model rights protection scope.
Claims (4)
1. a high speed clocked comparator, is characterized in that: comprise pre-amplification stage circuit, clock circuit; Described pre-amplification stage circuit, comprise differential input stage transistor M4, differential input stage transistor M5, input difference to the active load of pipe be transistor M0, input difference to the active load of pipe be transistor M1, tail current source transistor M6, clock control transistor M11, secondary amplifier transistor M2, secondary amplifier transistor M3, secondary amplification active load be transistor M9, the active load of secondary amplification is transistor M10, clock control transistor M12; Described input difference is after transistor M0 connects with differential input stage transistor M4 to the active load of pipe, is that transistor M1 and differential input stage transistor M5 are in parallel with the input difference of connecting to the active load of pipe; Described tail current source transistor M6 is connected with differential input stage transistor M4, differential input stage transistor M5 respectively; Described clock control transistor M11 is connected with tail current source transistor M6, and controls by clock circuit; Described secondary amplifier transistor M2 and input difference are that transistor M0 is connected to the active load of pipe, simultaneously and be that transistor M10 is connected with the active load of secondary amplification; Described secondary amplifier transistor M3 and input difference are that transistor M1 is connected to the active load of pipe, simultaneously and be that transistor M9 is connected with the active load of secondary amplification; The active load of described secondary amplification is transistor M9, the active load of secondary amplification is that transistor M10 is connected with clock control transistor M12 respectively, and is subject to and controls by clock circuit; Work when the signal CLK of clock circuit is high level, gather the voltage signal that differential input end need compare; When the signal CLK of clock circuit is low level, clock control transistor M11, M12 close, and pre-amplification stage circuit does not work, thus reduces power consumption.
2. high speed clocked comparator according to claim 1, is characterized in that: described differential input stage transistor M4, M5 adopt minimum channel length to improve speed.
3. high speed clocked comparator according to claim 1 and 2, is characterized in that: also comprise and judge level circuit, described judgement level circuit, comprises transistor M7, transistor M8, clock control transistor M14, clock control transistor M15; In parallel with the transistor M8 connected and clock control transistor M15 after described transistor M7 is connected with clock control transistor M14, the cross bonding of transistor M7, M8 grid, realizes positive feedback, to improve the gain of decision circuitry simultaneously; Described clock control transistor M14 is connected with secondary amplifier transistor M2; Described clock control transistor M15 is connected with secondary amplifier transistor M3; When the signal CLK of clock circuit is low level, clock control transistor M14, M15 conducting, judges level circuit working.
4. high speed clocked comparator according to claim 3, is characterized in that: described transistor M7, transistor M8 are connected with the transistor M13 of grid leak short circuit respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420604995.8U CN204206134U (en) | 2014-10-20 | 2014-10-20 | A kind of high speed clocked comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420604995.8U CN204206134U (en) | 2014-10-20 | 2014-10-20 | A kind of high speed clocked comparator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204206134U true CN204206134U (en) | 2015-03-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420604995.8U Expired - Fee Related CN204206134U (en) | 2014-10-20 | 2014-10-20 | A kind of high speed clocked comparator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204206134U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104333358A (en) * | 2014-10-20 | 2015-02-04 | 苏州市职业大学 | High-speed clock-controlled comparator |
-
2014
- 2014-10-20 CN CN201420604995.8U patent/CN204206134U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104333358A (en) * | 2014-10-20 | 2015-02-04 | 苏州市职业大学 | High-speed clock-controlled comparator |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150311 Termination date: 20151020 |
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| EXPY | Termination of patent right or utility model |