CN204143195U - A kind of data acquisition processing device simultaneously meeting AD, DI, DO - Google Patents
A kind of data acquisition processing device simultaneously meeting AD, DI, DO Download PDFInfo
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- CN204143195U CN204143195U CN201420574856.5U CN201420574856U CN204143195U CN 204143195 U CN204143195 U CN 204143195U CN 201420574856 U CN201420574856 U CN 201420574856U CN 204143195 U CN204143195 U CN 204143195U
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Abstract
The utility model provides one to meet AD simultaneously, DI, the data acquisition processing device of DO, comprise central processing module (1), AD data input module (2), digital signal load module (3), digital signal output modules (4) and usb communication module (5), described AD data input module (2) is connected with external analog data channel, described digital signal load module (3), digital signal output modules (4) respectively with external digital signal expanding channels, described usb communication module (5) and outside host computer communicate to connect, the simulated data that described AD data input module (2) will collect, the data that described digital signal load module (3) will collect, deliver to described central processing module (1) to process, finally send host computer to by usb communication module (5) and perform corresponding actions, described host computer, by sending instruction to described usb communication module (5), is accepted by described central processing module (1), is finally undertaken performing corresponding instruction by described digital signal output modules (4).
Description
Technical field
The utility model relates to technical field of measurement and test, is specifically related to a kind of data acquisition processing device simultaneously meeting AD, DI, DO.
Background technology
Along with the progress of data acquisition technology, the maturation of chip Multi-core technology, high speed, high-level efficiency, high integration become the trend of data acquisition process.But current data acquisition process mode still adopts monokaryon processing mode, at synchronization, one group of data can only be gathered, the process needs of multi-group data or multiple types of data can not be met simultaneously, govern the raising of data acquisition process efficiency to a certain extent.The chip of data acquisition process was all monokaryon in the past, can only process a task within a time, if there is multitasking, needed to carry out timesharing etc. to task pending, can not meet the acquisition process of multi-group data or multiple types of data simultaneously.When processing data volume and being larger, the situation of inefficiency will be caused.
Utility model content
For above-mentioned prior art, technical problem to be solved in the utility model is to provide a kind of data acquisition processing device simultaneously meeting AD, DI, DO, and this device can meet the acquisition process of multi-group data or multiple types of data simultaneously, and efficiency is high.
In order to solve the problems of the technologies described above, the utility model provides one and meets AD simultaneously, DI, the data acquisition processing device of DO, comprise central processing module, AD data input module, digital signal load module, digital signal output modules and usb communication module, described AD data input module is connected with external analog data channel, described digital signal load module, digital signal output modules respectively with external digital signal expanding channels, described usb communication module and outside host computer communicate to connect, the simulated data that described AD data input module will collect, the data that described digital signal load module will collect, deliver to described central processing module to process, finally send host computer to by usb communication module and perform corresponding actions, described host computer, by sending instruction to described usb communication module, is accepted by described central processing module, is finally undertaken performing corresponding instruction by described digital signal output modules.
Further improvement of the utility model is, described central processing module is four core processors.
Further improvement of the utility model is, described four core processors are Freescale I.MX6Q tetra-core processor.
Further improvement of the utility model is, described AD data input module comprises two groups of single-ended analog multiplexers and AD converter, is connected after the parallel connection of described two groups of single-ended analog multiplexers with described AD converter.
Further improvement of the utility model is, described digital signal load module is composed in parallel by four group of eight road bus transceiver.
Further improvement of the utility model is, described digital signal output modules comprises two group of eight Darlington transistor display and four groups of photoelectrical couplers, displays be connected after described two groups of photoelectrical coupler parallel connections with one group of eight Darlington transistor.
Further improvement of the utility model is, described usb communication module adopts Single-chip Controlling.
Compared with prior art, the utility model has the advantage of, this device adopts four core processors, AD data input module, digital signal load module, digital signal output modules and usb communication module simultaneously, the data acquisition process of AD, DI, DO can be met simultaneously, when processing data volume and being larger, the efficiency of process is also very high.
Accompanying drawing explanation
Fig. 1 is theory structure schematic diagram of the present utility model;
Fig. 2 is the circuit theory diagrams of central processing module of the present utility model;
Fig. 3 is the circuit theory diagrams of AD data input module of the present utility model;
Fig. 4 is the circuit theory diagrams of digital signal load module of the present utility model;
Fig. 5 is the circuit theory diagrams of digital signal output modules of the present utility model;
Fig. 6 is the circuit theory diagrams of usb communication module of the present utility model.
In figure, each component names is as follows:
1-central processing module;
2-AD data input module;
3-digital signal load module;
4-digital signal output modules;
5-usb communication module.
Embodiment
Illustrate below in conjunction with accompanying drawing and embodiment further illustrates the utility model, element numbers similar in accompanying drawing represents similar element.
As shown in Figure 1, one of the present utility model meets AD simultaneously, DI, the data acquisition processing device of DO, it comprises central processing module 1, AD data input module 2, digital signal load module 3, digital signal output modules 4 and usb communication module 5, described AD data input module 2 is connected with external analog data channel, described digital signal load module 3, digital signal output modules 4 respectively with external digital signal expanding channels, described usb communication module 5 communicates to connect with outside host computer, the simulated data that described AD data input module 2 will collect, the data that described digital signal load module 3 will collect, deliver to described central processing module 1 to process, finally send host computer to by usb communication module 5 and perform corresponding actions, described host computer, by sending instruction to described usb communication module 5, is accepted by described central processing module 1, is finally undertaken performing corresponding instruction by described digital signal output modules 4.
Particularly, described central processing module 1 is four core processors.
Particularly, Fig. 2 is the circuit theory diagrams of central processing module of the present utility model.As shown in Figure 2, described central processing module 1 adopts the concrete model of four core processors to be Freescale I.MX6Q tetra-core processor.
Particularly, Fig. 3 is the circuit theory diagrams of AD data input module of the present utility model.As shown in Figure 3, described AD data input module 2 comprises two groups of single-ended analog multiplexers and AD converter, is connected after the parallel connection of described two groups of single-ended analog multiplexers with described AD converter.The multiplexed implement body of described single-ended analog adopts MPC506A; Described AD converter specifically adopts ADS774JP.
Particularly, Fig. 4 is the circuit theory diagrams of digital signal load module of the present utility model.As shown in Figure 4, described digital signal load module 3 is composed in parallel by four group of eight road bus transceiver.Described eight road bus transceivers specifically adopt SN74HC245.
Particularly, Fig. 5 is the circuit theory diagrams of digital signal output modules of the present utility model.As shown in Figure 5, described digital signal output modules 4 comprises two group of eight Darlington transistor display and four groups of photoelectrical couplers, displays be connected after described two groups of photoelectrical coupler parallel connections with one group of eight Darlington transistor.Described eight Darlington transistor displays specifically adopt ULN2803-1; Described photoelectric coupling implement body adopts PC847.
Particularly, Fig. 6 is the circuit theory diagrams of usb communication module of the present utility model.As shown in Figure 6, described usb communication module 5 adopts Single-chip Controlling.The concrete model of described single-chip microcomputer is C8051F340 or C8051F341 or C8051F344 or C8051F345.
The utility model has the advantage of, this device adopts four core processors, AD data input module, digital signal load module, digital signal output modules and usb communication module simultaneously, the data acquisition process of AD, DI, DO can be met simultaneously, when processing data volume and being larger, the efficiency of process is also very high.Because central processing module adopts four core process frameworks, non-interfering process can be carried out to four tasks simultaneously, substantially increase the speed of system to data processing, also meet process while DO is exported to AD data, digital signal input DI, digital signal simultaneously, make the execution of system to each task reach the effect of real-time response.
Above content is in conjunction with concrete preferred implementation further detailed description of the utility model, can not assert that concrete enforcement of the present utility model is confined to these explanations.For the utility model person of an ordinary skill in the technical field, without departing from the concept of the premise utility, some simple deduction or replace can also be made, all should be considered as belonging to protection domain of the present utility model.
Claims (7)
1. one kind meets AD simultaneously, DI, the data acquisition processing device of DO, it is characterized in that: comprise central processing module (1), AD data input module (2), digital signal load module (3), digital signal output modules (4) and usb communication module (5), described AD data input module (2) is connected with external analog data channel, described digital signal load module (3), digital signal output modules (4) respectively with external digital signal expanding channels, described usb communication module (5) and outside host computer communicate to connect, the simulated data that described AD data input module (2) will collect, the data that described digital signal load module (3) will collect, deliver to described central processing module (1) to process, finally send host computer to by usb communication module (5) and perform corresponding actions, described host computer, by sending instruction to described usb communication module (5), is accepted by described central processing module (1), is finally undertaken performing corresponding instruction by described digital signal output modules (4).
2. meet the data acquisition processing device of AD, DI, DO as claimed in claim 1 simultaneously, it is characterized in that: described central processing module (1) is four core processors.
3. meet the data acquisition processing device of AD, DI, DO as claimed in claim 2 simultaneously, it is characterized in that: described four core processors are Freescale I.MX6Q tetra-core processor.
4. while as described in any one of claims 1 to 3, meet the data acquisition processing device of AD, DI, DO, it is characterized in that: described AD data input module (2) comprises two groups of single-ended analog multiplexers and AD converter, is connected after the parallel connection of described two groups of single-ended analog multiplexers with described AD converter.
5. meet the data acquisition processing device of AD, DI, DO while as described in any one of claims 1 to 3, it is characterized in that: described digital signal load module (3) is composed in parallel by four group of eight road bus transceiver.
6. while as described in any one of claims 1 to 3, meet the data acquisition processing device of AD, DI, DO, it is characterized in that: described digital signal output modules (4) comprises two group of eight Darlington transistor display and four groups of photoelectrical couplers, displays be connected after described two groups of photoelectrical coupler parallel connections with one group of eight Darlington transistor.
7. meet the data acquisition processing device of AD, DI, DO while as described in any one of claims 1 to 3, it is characterized in that: described usb communication module (5) adopts Single-chip Controlling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420574856.5U CN204143195U (en) | 2014-09-30 | 2014-09-30 | A kind of data acquisition processing device simultaneously meeting AD, DI, DO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420574856.5U CN204143195U (en) | 2014-09-30 | 2014-09-30 | A kind of data acquisition processing device simultaneously meeting AD, DI, DO |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204143195U true CN204143195U (en) | 2015-02-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420574856.5U Expired - Fee Related CN204143195U (en) | 2014-09-30 | 2014-09-30 | A kind of data acquisition processing device simultaneously meeting AD, DI, DO |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204143195U (en) |
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2014
- 2014-09-30 CN CN201420574856.5U patent/CN204143195U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150204 Termination date: 20210930 |
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| CF01 | Termination of patent right due to non-payment of annual fee |