CN204131421U - A kind of voltage output control circuit - Google Patents
A kind of voltage output control circuit Download PDFInfo
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- CN204131421U CN204131421U CN201420451037.1U CN201420451037U CN204131421U CN 204131421 U CN204131421 U CN 204131421U CN 201420451037 U CN201420451037 U CN 201420451037U CN 204131421 U CN204131421 U CN 204131421U
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Abstract
The utility model relates to a kind of voltage output control circuit, belongs to technical field of electronic products.The utility model comprises adjustable voltage-stabilized source I, adjustable voltage-stabilized source II, analog to digital conversion circuit, match control circuit; Wherein adjustable voltage-stabilized source I, adjustable voltage-stabilized source II are connected with match control circuit respectively with analog to digital conversion circuit.The utility model circuit is simple, with low cost, because circuit is lower for the requirement of environment, under can being adapted to different occasions.
Description
Technical field
The utility model relates to a kind of voltage output control circuit, belongs to technical field of electronic products.
Background technology
In some industrial circuits, output voltage after the analog signal of some circuit converts digital signal to just will can guarantee the normal operation of subordinate's circuit in certain scope, and existing voltage output control circuit employing is hardware handles mode, although hardware has stronger disposal ability, effect is better, but hardware development cost hinders universal key factor beyond doubt.It is higher that people require to provide a kind of reliability and cost performance, circuit structure relatively simply, the voltage output control circuit that range of application is wider.
Summary of the invention
The utility model provides a kind of voltage output control circuit, exports for solving existing voltage with high costs, the problem that circuit structure is complicated that control.
The technical solution of the utility model is: a kind of voltage output control circuit, comprises adjustable voltage-stabilized source I 1, adjustable voltage-stabilized source II 2, analog to digital conversion circuit 3, match control circuit 4; Wherein adjustable voltage-stabilized source I 1, adjustable voltage-stabilized source II 2 are connected with match control circuit 4 respectively with analog to digital conversion circuit 3.
Described adjustable voltage-stabilized source I 1 comprises transformer T1, slide rheostat RP1, resistance R1, R2, R3, R4, electric capacity C1, C2, C3, diode VD1, VD2, VD3, VD4, VD5, triode VT1, VT2, VT3;
Described adjustable voltage-stabilized source II 2 comprises transformer T2, slide rheostat RP2, resistance R5, R6, R7, R8, electric capacity C4, C5, C6, diode VD6, VD7, VD8, VD9, VD10, triode VT4, VT5, VT6;
The circuit structure of described adjustable voltage-stabilized source I 1, adjustable voltage-stabilized source II 2 is identical.
The circuit structure of described adjustable voltage-stabilized source I 1 is: transformer T1 mono-end-coil two the end of a thread are received on 220V voltage, the other end two lines first receive on diode VD1, another is connected on diode VD3; Slide rheostat RP1 tri-end is received on the emitter of resistance R3, resistance R4 and triode VT2 respectively; Resistance R1 mono-end is received on triode VT3 emitter, and an end is received on the collector electrode of triode VT2; Resistance R2 mono-end is received in triode VT1 base stage, and an end is received on electric capacity C2; Resistance R3 mono-end is received in triode VT3 base stage, and an end is received on slide rheostat RP1; Resistance R4 mono-end is received on slide rheostat RP1, and an end is received on electric capacity C3; Electric capacity C1 mono-end is received on triode VT2 collector electrode, and an end is received on diode VD4; Electric capacity C2 mono-end is received in triode VT2 base stage, and an end is received on diode VD5; Electric capacity C3 mono-end is received on triode VT2 emitter, and an end is received on resistance R4; Diode VD1 mono-end is received on transformer T1 the end of a thread, and an end is received on the collector electrode of triode VT2; Diode VD2 mono-end is received on diode VD1, and an end is received on diode VD4; Diode VD3 mono-end is received on the collector electrode of triode VT2, and an end is received on transformer T1 the end of a thread; Diode VD4 mono-end is received on transformer T1 the end of a thread, and an end is received on diode VD2; Diode VD5 mono-end receives the emitter of triode VT3, and an end is received on electric capacity C2; Triode VT1 emitter receives resistance R1, and base stage receives resistance R2, and the collector electrode of triode VT3 received by collector electrode; Triode VT2 emitter is received on electric capacity C3, and base stage receives electric capacity C2, and the emitter of triode VT1 received by collector electrode; Triode VT3 emitter receives resistance R1, and base stage receives resistance R3, and the collector electrode of triode VT1 received by collector electrode.
Analog-digital conversion circuit as described 3 comprises modulus conversion chip ADC8032, resistance R9, R10, R11, R12, R13, diode VD11, triode VT7, VT8; Wherein modulus conversion chip ADC8032 port 2 incoming analog signal, port 4 ground connection, port 5 connects power supply, and port 6 connects triode VT7 collector electrode; Resistance R9 mono-termination triode VT7 collector electrode, another termination triode VT8 collector electrode; Resistance R10 mono-termination triode VT7 emitter, a termination triode VT8 emitter; Resistance R11 mono-termination triode VT8 base stage, another termination triode VT7 emitter; Resistance R12 mono-terminating resistor R11, other end connecting resistance R13; Resistance R13 mono-termination triode VT7 emitter, other end connecting resistance R12; Diode VD11 mono-termination triode VT8 emitter, the other end receives resistance R12; Triode VT7 base stage and collector electrode connecting resistance R9, emitter connecting resistance R10; Triode VT8 base stage connecting resistance R11, emitter meets VD11, collector electrode connecting resistance R9.
Described match control circuit 4 comprises voltage compare chip LM339, with door; Wherein voltage compare chip LM339 port 3 connects voltage, port one 2 ground connection, port 4 and 6 connects the output of analog to digital conversion circuit 3, in port 5 and adjustable voltage-stabilized source II 2, the emitter of triode VT5 is connected with the binding site of electric capacity C6, and in port 7 and adjustable voltage-stabilized source I 1, the emitter of triode VT2 is connected with the binding site of electric capacity C3; Port one and 2 connects and door two ports, is output port with the door other end.
Operation principle of the present utility model is:
The analog signal of input, through modulus conversion chip ADC8032 output digit signals, is carried out stable regulation by a voltage stabilizing circuit to digital signal voltage, is then input to the port 4 and 6 of voltage compare chip LM339; The rated voltage that adjustable voltage-stabilized source I 1 produces is the minimum of the permission voltage of digital signal, and the signal of generation is input to the port 7 of voltage compare chip LM339; The rated voltage that adjustable voltage-stabilized source II 2 produces is the peak of the permission voltage of digital signal, and the signal of generation is input to the port 5 of voltage compare chip LM339; Two rated voltages of voltage compare chip LM339 to the digital signal voltage of input and two adjustable voltage-stabilized source generations compare, if the input voltage of port 6 is higher than port 7 input voltage, port one produces high level, otherwise is low level; If the input voltage of port 4 is lower than the input voltage of port 5, port 2 produces high level, otherwise produces low level; Carry out logical AND calculating to port one and port 2, only have when port one and port 2 produce high level simultaneously, namely digital signal voltage in allowed limits, could export high level with door, and subordinate's circuit could normal work.
The beneficial effects of the utility model are: circuit is simple, with low cost, because circuit is lower for the requirement of environment, under can being adapted to different occasions.
Accompanying drawing explanation
Fig. 1 is circuit theory diagrams of the present utility model;
In figure, each label is: 1 for adjustable voltage-stabilized source I, 2 for adjustable voltage-stabilized source II, 3 is analog to digital conversion circuit, 4 is match control circuit.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail, but content of the present utility model is not limited to described scope.
Embodiment 1: as shown in Figure 1, a kind of voltage output control circuit, comprises adjustable voltage-stabilized source I 1, adjustable voltage-stabilized source II 2, analog to digital conversion circuit 3, match control circuit 4; Wherein adjustable voltage-stabilized source I 1, adjustable voltage-stabilized source II 2 are connected with match control circuit 4 respectively with analog to digital conversion circuit 3.
Described adjustable voltage-stabilized source I 1 comprises transformer T1, slide rheostat RP1, resistance R1, R2, R3, R4, electric capacity C1, C2, C3, diode VD1, VD2, VD3, VD4, VD5, triode VT1, VT2, VT3;
Described adjustable voltage-stabilized source II 2 comprises transformer T2, slide rheostat RP2, resistance R5, R6, R7, R8, electric capacity C4, C5, C6, diode VD6, VD7, VD8, VD9, VD10, triode VT4, VT5, VT6;
The circuit structure of described adjustable voltage-stabilized source I 1, adjustable voltage-stabilized source II 2 is identical.
The circuit structure of described adjustable voltage-stabilized source I 1 is: transformer T1 mono-end-coil two the end of a thread are received on 220V voltage, the other end two lines first receive on diode VD1, another is connected on diode VD3; Slide rheostat RP1 tri-end is received on the emitter of resistance R3, resistance R4 and triode VT2 respectively; Resistance R1 mono-end is received on triode VT3 emitter, and an end is received on the collector electrode of triode VT2; Resistance R2 mono-end is received in triode VT1 base stage, and an end is received on electric capacity C2; Resistance R3 mono-end is received in triode VT3 base stage, and an end is received on slide rheostat RP1; Resistance R4 mono-end is received on slide rheostat RP1, and an end is received on electric capacity C3; Electric capacity C1 mono-end is received on triode VT2 collector electrode, and an end is received on diode VD4; Electric capacity C2 mono-end is received in triode VT2 base stage, and an end is received on diode VD5; Electric capacity C3 mono-end is received on triode VT2 emitter, and an end is received on resistance R4; Diode VD1 mono-end is received on transformer T1 the end of a thread, and an end is received on the collector electrode of triode VT2; Diode VD2 mono-end is received on diode VD1, and an end is received on diode VD4; Diode VD3 mono-end is received on the collector electrode of triode VT2, and an end is received on transformer T1 the end of a thread; Diode VD4 mono-end is received on transformer T1 the end of a thread, and an end is received on diode VD2; Diode VD5 mono-end receives the emitter of triode VT3, and an end is received on electric capacity C2; Triode VT1 emitter receives resistance R1, and base stage receives resistance R2, and the collector electrode of triode VT3 received by collector electrode; Triode VT2 emitter is received on electric capacity C3, and base stage receives electric capacity C2, and the emitter of triode VT1 received by collector electrode; Triode VT3 emitter receives resistance R1, and base stage receives resistance R3, and the collector electrode of triode VT1 received by collector electrode.
Analog-digital conversion circuit as described 3 comprises modulus conversion chip ADC8032, resistance R9, R10, R11, R12, R13, diode VD11, triode VT7, VT8; Wherein modulus conversion chip ADC8032 port 2 incoming analog signal, port 4 ground connection, port 5 connects power supply, and port 6 connects triode VT7 collector electrode; Resistance R9 mono-termination triode VT7 collector electrode, another termination triode VT8 collector electrode; Resistance R10 mono-termination triode VT7 emitter, a termination triode VT8 emitter; Resistance R11 mono-termination triode VT8 base stage, another termination triode VT7 emitter; Resistance R12 mono-terminating resistor R11, other end connecting resistance R13; Resistance R13 mono-termination triode VT7 emitter, other end connecting resistance R12; Diode VD11 mono-termination triode VT8 emitter, the other end receives resistance R12; Triode VT7 base stage and collector electrode connecting resistance R9, emitter connecting resistance R10; Triode VT8 base stage connecting resistance R11, emitter meets VD11, collector electrode connecting resistance R9.
Described match control circuit 4 comprises voltage compare chip LM339, with door; Wherein voltage compare chip LM339 port 3 connects voltage, port one 2 ground connection, port 4 and 6 connects the output of analog to digital conversion circuit 3, in port 5 and adjustable voltage-stabilized source II 2, the emitter of triode VT5 is connected with the binding site of electric capacity C6, and in port 7 and adjustable voltage-stabilized source I 1, the emitter of triode VT2 is connected with the binding site of electric capacity C3; Port one and 2 connects and door two ports, is output port with the door other end.
Embodiment 2: as shown in Figure 1, a kind of voltage output control circuit, comprises adjustable voltage-stabilized source I 1, adjustable voltage-stabilized source II 2, analog to digital conversion circuit 3, match control circuit 4; Wherein adjustable voltage-stabilized source I 1, adjustable voltage-stabilized source II 2 are connected with match control circuit 4 respectively with analog to digital conversion circuit 3.
By reference to the accompanying drawings embodiment of the present utility model is explained in detail above, but the utility model is not limited to above-mentioned execution mode, in the ken that those of ordinary skill in the art possess, various change can also be made under the prerequisite not departing from the utility model aim.
Claims (5)
1. a voltage output control circuit, is characterized in that: comprise adjustable voltage-stabilized source I (1), adjustable voltage-stabilized source II (2), analog to digital conversion circuit (3), match control circuit (4); Wherein adjustable voltage-stabilized source I (1), adjustable voltage-stabilized source II (2) are connected with match control circuit (4) respectively with analog to digital conversion circuit (3).
2. voltage output control circuit according to claim 1, is characterized in that:
Described adjustable voltage-stabilized source I (1) comprises transformer T1, slide rheostat RP1, resistance R1, R2, R3, R4, electric capacity C1, C2, C3, diode VD1, VD2, VD3, VD4, VD5, triode VT1, VT2, VT3;
Described adjustable voltage-stabilized source II (2) comprises transformer T2, slide rheostat RP2, resistance R5, R6, R7, R8, electric capacity C4, C5, C6, diode VD6, VD7, VD8, VD9, VD10, triode VT4, VT5, VT6;
The circuit structure of described adjustable voltage-stabilized source I (1), adjustable voltage-stabilized source II (2) is identical.
3. voltage output control circuit according to claim 2, it is characterized in that: the circuit structure of described adjustable voltage-stabilized source I (1) is: transformer T1 mono-end-coil two the end of a thread are received on 220V voltage, the other end two lines first receive on diode VD1, another is connected on diode VD3; Slide rheostat RP1 tri-end is received on the emitter of resistance R3, resistance R4 and triode VT2 respectively; Resistance R1 mono-end is received on triode VT3 emitter, and an end is received on the collector electrode of triode VT2; Resistance R2 mono-end is received in triode VT1 base stage, and an end is received on electric capacity C2; Resistance R3 mono-end is received in triode VT3 base stage, and an end is received on slide rheostat RP1; Resistance R4 mono-end is received on slide rheostat RP1, and an end is received on electric capacity C3; Electric capacity C1 mono-end is received on triode VT2 collector electrode, and an end is received on diode VD4; Electric capacity C2 mono-end is received in triode VT2 base stage, and an end is received on diode VD5; Electric capacity C3 mono-end is received on triode VT2 emitter, and an end is received on resistance R4; Diode VD1 mono-end is received on transformer T1 the end of a thread, and an end is received on the collector electrode of triode VT2; Diode VD2 mono-end is received on diode VD1, and an end is received on diode VD4; Diode VD3 mono-end is received on the collector electrode of triode VT2, and an end is received on transformer T1 the end of a thread; Diode VD4 mono-end is received on transformer T1 the end of a thread, and an end is received on diode VD2; Diode VD5 mono-end receives the emitter of triode VT3, and an end is received on electric capacity C2; Triode VT1 emitter receives resistance R1, and base stage receives resistance R2, and the collector electrode of triode VT3 received by collector electrode; Triode VT2 emitter is received on electric capacity C3, and base stage receives electric capacity C2, and the emitter of triode VT1 received by collector electrode; Triode VT3 emitter receives resistance R1, and base stage receives resistance R3, and the collector electrode of triode VT1 received by collector electrode.
4. voltage output control circuit according to claim 1, is characterized in that: analog-digital conversion circuit as described (3) comprises modulus conversion chip ADC8032, resistance R9, R10, R11, R12, R13, diode VD11, triode VT7, VT8; Wherein modulus conversion chip ADC8032 port 2 incoming analog signal, port 4 ground connection, port 5 connects power supply, and port 6 connects triode VT7 collector electrode; Resistance R9 mono-termination triode VT7 collector electrode, another termination triode VT8 collector electrode; Resistance R10 mono-termination triode VT7 emitter, a termination triode VT8 emitter; Resistance R11 mono-termination triode VT8 base stage, another termination triode VT7 emitter; Resistance R12 mono-terminating resistor R11, other end connecting resistance R13; Resistance R13 mono-termination triode VT7 emitter, other end connecting resistance R12; Diode VD11 mono-termination triode VT8 emitter, the other end receives resistance R12; Triode VT7 base stage and collector electrode connecting resistance R9, emitter connecting resistance R10; Triode VT8 base stage connecting resistance R11, emitter meets VD11, collector electrode connecting resistance R9.
5. voltage output control circuit according to claim 1, is characterized in that: described match control circuit (4) comprises voltage compare chip LM339, with door; Wherein voltage compare chip LM339 port 3 connects voltage, port one 2 ground connection, port 4 and 6 connects the output of analog to digital conversion circuit (3), the emitter of port 5 and the middle triode VT5 of adjustable voltage-stabilized source II (2) is connected with the binding site of electric capacity C6, and the emitter of port 7 and the middle triode VT2 of adjustable voltage-stabilized source I (1) is connected with the binding site of electric capacity C3; Port one and 2 connects and door two ports, is output port with the door other end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420451037.1U CN204131421U (en) | 2014-08-12 | 2014-08-12 | A kind of voltage output control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420451037.1U CN204131421U (en) | 2014-08-12 | 2014-08-12 | A kind of voltage output control circuit |
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| Publication Number | Publication Date |
|---|---|
| CN204131421U true CN204131421U (en) | 2015-01-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420451037.1U Expired - Fee Related CN204131421U (en) | 2014-08-12 | 2014-08-12 | A kind of voltage output control circuit |
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| CN (1) | CN204131421U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106394523A (en) * | 2016-10-17 | 2017-02-15 | 广州铁路职业技术学院 | Intelligent braking system preventing driver from stepping on accelerator mistakenly during emergency braking of vehicle |
-
2014
- 2014-08-12 CN CN201420451037.1U patent/CN204131421U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106394523A (en) * | 2016-10-17 | 2017-02-15 | 广州铁路职业技术学院 | Intelligent braking system preventing driver from stepping on accelerator mistakenly during emergency braking of vehicle |
| CN106394523B (en) * | 2016-10-17 | 2019-02-15 | 广州铁路职业技术学院 | Emergency brake of vehicle accelerator stepping misoperation preventing Intelligent brake system |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150128 Termination date: 20160812 |
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| CF01 | Termination of patent right due to non-payment of annual fee |