CN204130535U - A kind of nonvolatile three-dimensional semiconductor memory - Google Patents
A kind of nonvolatile three-dimensional semiconductor memory Download PDFInfo
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- CN204130535U CN204130535U CN201420532334.9U CN201420532334U CN204130535U CN 204130535 U CN204130535 U CN 204130535U CN 201420532334 U CN201420532334 U CN 201420532334U CN 204130535 U CN204130535 U CN 204130535U
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The utility model discloses a kind of nonvolatile three-dimensional semiconductor memory, comprise the three dimensional NAND storage string of multiple vertical direction, each three dimensional NAND storage string comprises horizontal substrate, perpendicular to the cylindrical semiconductive region of substrate, lay respectively on semiconductor regions, under the second electrode and the first electrode, the Tunneling dielectric in parcel cylindrical semiconductive region, around on Tunneling dielectric, under distributed multiple discrete charge storage layer, wrap up the obstruct dielectric layer of Tunneling dielectric and multiple charge storage layer, the control grid electrode mutually stacking with insulating barrier, cylindrical semiconductive region comprises the source region of multiple memory cell, drain region and raceway groove.The utility model adopts floating transistor as memory cell, adopts chalcogenide compound as channel material, and memory cell adopts encloses grid structure, and channel region and source and drain areas adopt same material, are formed without junction structure, well avoid short channel effect.
Description
Technical field
The utility model belongs to technical field of microelectronic devices, more specifically, relates to a kind of nonvolatile three-dimensional semiconductor memory.
Background technology
In order to meet the development of efficient and cheap microelectronic industry, semiconductor storage unit needs to have higher integration density.About semiconductor storage unit, because their integration density is very important in decision product price, namely High Density Integration is very important.For traditional two dimension and planar semiconductor memory part, because their integration density depends primarily on the unit are shared by single memory device, integrated level depends on the quality of masking process very much.But even if continuous expensive process equipment improves masking process precision, the lifting of integration density remains very limited.
As overcoming substituting of this two-dimentional limit, three-dimensional semiconductor memory device is suggested.Three-dimensional semiconductor memory device, needs to have the technique that can obtain lower manufacturing cost, and can obtain positive means structure.
For flash storage device, the memory cell of flash memory is three terminal device, and three ends are divided into: source electrode, drain and gate.Source electrode is connected with device channel with drain electrode, and charge carrier in channels sports becomes channel current to make source electrode and drain electrode conducting, and grid voltage can control charge carrier state in raceway groove thus the whether conducting of control raceway groove.Flash memory is a kind of voltage-controlled device, the wiping of NAND (not and) type flash memory and to write be all based on tunnel effect, electric current, through the insulating barrier floating grid and raceway groove, charges (writing data) to floating grid or discharges (obliterated data).By the control of grid voltage, electric charge is stored in floating boom, realize the storage of data, after removing grid voltage, the electric charge stored in floating boom to control the break-make of raceway groove, thus can realize the reading of data at source electrode and drain electrode.
In three dimensional NAND type flash memories, raceway groove preparation technology is very challenging, if according to traditional microelectronic material technique, channel material selects single crystal silicon material, select single crystal silicon material technique to realize upper just needs and first form channel part by etching technics, form grid structure again, need in the vertical direction due to three dimensional NAND type flash memories or parallel direction realize the display of raceway groove, etching technics has on a silicon substrate been difficult to so complicated structure.
The heavy doping of source electrode and drain electrode is a technical barrier, because channel region adopts light dope, and source-drain area needs heavy doping to realize ohmic contact, source, drain region are different from the doping content of channel region, so just need the vertical channel portion of vertical channel structure to need layering to prepare, aligning so is between layers just very difficult, and doping gradient is also difficult to control.
Utility model content
For the defect of prior art, the purpose of this utility model is to provide a kind of nonvolatile three-dimensional semiconductor memory, is intended to the source in prior art that solves, drain region and differently from the doping content of channel region makes source, is formed with the problem that PN junction causes short channel effect between drain region and channel region.
The utility model provides a kind of nonvolatile three-dimensional semiconductor memory, comprise the three dimensional NAND storage string of multiple vertical direction, each three dimensional NAND storage string comprises: horizontal substrate, perpendicular to the cylindrical semiconductive region of described substrate, lay respectively on described semiconductor regions, under the second electrode and the first electrode, wrap up the Tunneling dielectric in described cylindrical semiconductive region, around on Tunneling dielectric, under distributed multiple discrete charge storage layer, wrap up the obstruct dielectric layer of Tunneling dielectric and multiple charge storage layer, and the control grid electrode that outermost is mutually stacking with insulating barrier, described cylindrical semiconductive region comprises the source region of multiple memory cell, drain region and raceway groove, commaterial is all adopted to fill, between source region and raceway groove, do not form PN junction, between drain region and raceway groove, do not form PN junction, described channel region is cylindrical, and described control grid electrode encloses grid structure around described channel region formation.
Further, the body diameter in described cylindrical semiconductive region is 20nm ~ 100nm.
Further, in described cylindrical semiconductive region, source region, drain region and raceway groove all adopt chalcogenide compound material to prepare.
Further, described chalcogenide compound material comprises Sb2Te3 material, GeTe material, Bi2Te3 material, SnTe material, Bi2Se3 material, GeSe material, PbTe material, SnSe material.
Further, the intrinsic carrier concentration of described chalcogenide compound material is 10
18cm
-3-10
20cm
-3.
The utility model is by introducing chalcogenide compound material, Sb2Te3 material, GeTe material, Bi2Te3 material, SnTe material, Bi2Se3 material, GeSe material, PbTe material, SnSe material etc. are as channel material, and in technological process, after gate stack structure completes, channel material is filled in reserved raceway groove through hole, and adopt without junction device structure, namely source region, drain region and channel region adopt carrier concentration of the same race, doping can be avoided.So also change the working method of transistor, adopt transistor carriers to exhaust device and turn off.
Enclosing grid structure and can strengthen the control ability of grid for charge carrier in raceway groove in the utility model, can make raceway groove can end under suitable threshold voltage (about 5V).(concentration is 10 to adopt high carrier concentration for raceway groove
18cm
-3the device of chalcogenide compound material above), source-drain area and channel region adopt same material, and carrier concentration is consistent, can not form PN junction.Without the channel region structure of knot, compared with there being knot transoid device, well avoiding short channel effect, there is good Sub-Threshold Characteristic.The contact resistance problem of source-drain electrode can well be improved, reduce the tender subject for grid overlap.Insensitive for channel dopant concentration change, the technological problems of channel doping can be avoided like this.In addition, this without junction structure, better than the thermostable type of traditional transoid device, its source-drain current affects less by doping content.Charge carrier adopts transport in body to carry out alternative traditional surperficial inversion charge transport, can work under smaller szie.
The raceway groove depletion region that in the utility model, grid voltage causes and source region, drain region pn tie the depletion region caused and overlap, and therefore effectively gate controlled charge reduces, when ditch length reduces, gate controlled charge reduces, thus causing threshold voltage to reduce, after threshold voltage reduces, device cannot normally work.Because without junction device there is not pn knot in it, so it can well avoid short channel effect.In addition, characterize subthreshold behavior by sub-threshold slope, this is the important parameter of devices function when subthreshold state, and its sub-threshold slope is less, and the speed that device works in subthreshold region is faster.Without knot enhancement device, its raceway groove, by exhausting cut-off work, has the sub-threshold slope disappeared.
Accompanying drawing explanation
Fig. 1 is the structural representation of the nonvolatile three-dimensional semiconductor memory that the utility model embodiment provides;
Fig. 2 (a) is the profile of the non-volatile three dimensional NAND storage string structure that the utility model embodiment provides
Fig. 2 (b) is the vertical view of the non-volatile three dimensional NAND storage string structure that the utility model embodiment provides;
Fig. 3 is the structural representation of multilayer film in the preparation process one of the non-volatile three dimensional NAND storage string that the utility model embodiment provides, and figure is profile;
In the preparation process one of the non-volatile three dimensional NAND storage string that Fig. 4 the utility model embodiment provides, multilayer film carries out the structural representation after deep hole etching;
Fig. 5 is the structural representation after carrying out selective etch in the preparation process two of the non-volatile three dimensional NAND storage string that the utility model embodiment provides, and figure is profile;
Fig. 6 is the structural representation in the preparation process three of the non-volatile three dimensional NAND storage string that the utility model embodiment provides after deposition obstruct dielectric, and figure is profile;
Fig. 7 is the structural representation in the preparation process three of the non-volatile three dimensional NAND storage string that the utility model embodiment provides after deposited charge storage medium, and figure is profile;
Fig. 8 carries out the structural representation after intercepting dielectric and charge storage media etching in the preparation process three of the non-volatile three dimensional NAND storage string that the utility model embodiment provides, figure is profile;
Fig. 9 is in the preparation process four of the non-volatile three dimensional NAND storage string that the utility model embodiment provides, and carry out the structural representation after deep hole filling Tunneling dielectric, figure is profile;
Figure 10 is in the preparation process four of the non-volatile three dimensional NAND storage string that the utility model embodiment provides, and carry out the structural representation after Tunneling dielectric etching, figure is profile.
Figure 11 is in the preparation process four of the non-volatile three dimensional NAND storage string that the utility model embodiment provides, and carry out the structural representation that deep hole fills channel material, figure is profile.
Figure 12 is in the preparation process five of the non-volatile three dimensional NAND storage string that the utility model embodiment provides, and carry out the structural representation after top electrode preparation, figure is profile.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
The utility model is by introducing chalcogenide compound material, Sb2Te3 material, GeTe material, Bi2Te3 material, SnTe material, Bi2Se3 material, GeSe material, PbTe material, SnSe material etc. are as channel material, and in technological process, after gate stack structure completes, channel material is filled in reserved raceway groove through hole, and adopt without junction device structure, namely source region, drain region and channel region adopt carrier concentration of the same race, doping can be avoided.So also change the working method of transistor, adopt transistor carriers to exhaust device and turn off.
Enclose grid structure and can strengthen the control ability of grid for charge carrier in raceway groove, raceway groove can be made can to end under suitable threshold voltage (about 5V).
(concentration is 10 to adopt high carrier concentration for raceway groove
18cm
-3-10
20cm
-3the device of chalcogenide compound material above), source-drain area and channel region adopt same material, and carrier concentration is consistent, can not form PN junction.Without the channel region structure of knot, compared with there being knot transoid device, well avoiding short channel effect, there is good Sub-Threshold Characteristic.The contact resistance problem of source-drain electrode can well be improved, reduce the tender subject for grid overlap.Insensitive for channel dopant concentration change, the technological problems of channel doping can be avoided like this.In addition, this without junction structure, better than the thermostable type of traditional transoid device, its source-drain current affects less by doping content.Charge carrier adopts transport in body to carry out alternative traditional surperficial inversion charge transport, can work under smaller szie.
Short channel effect, the raceway groove depletion region that grid voltage causes and source region, drain region pn tie the depletion region caused and overlap, and therefore effectively gate controlled charge reduces, when ditch length reduces, gate controlled charge reduces, thus causes threshold voltage to reduce, after threshold voltage reduces, device cannot normally work.Because without junction device there is not pn knot in it, so it can well avoid short channel effect.
Subthreshold behavior, characterizes subthreshold behavior by sub-threshold slope, and this is the important parameter of devices function when subthreshold state, and its sub-threshold slope is less, and the speed that device works in subthreshold region is faster.Without knot enhancement device, its raceway groove, by exhausting cut-off work, has the sub-threshold slope disappeared.
In the utility model, an independent memory cell comprises: source electrode and drain region, and source electrode and drain electrode are all perpendicular to substrate; A channel region formed perpendicular to substrate, channel region is between source region and drain region; The column structure formed perpendicular to substrate at source electrode, drain electrode and channel region is surrounded by gate oxide; Contain floating gate layer in gate oxide, floating gate layer adopts metallic nanodots.
Be made up of the series connection storage string of enclosing grid structure of multiple vertical-channels during storage array, and the grid be in same plane in different storage string is interconnected, wherein each memory cell comprises: perpendicular to source electrode and the drain region of substrate; Perpendicular to the channel region of substrate, and channel region is between source region and drain region; Be a kind of dielectric substance as gate medium round source channel region, and contain a kind of floating gate structure in the dielectric.
The nonvolatile three-dimensional semiconductor memory device that the utility model provides, Figure 1 shows that its structure chart, as shown in fig. 1, the three-dimensional storage that the utility model embodiment provides comprises multiple three dimensional NAND storage string, and each three dimensional NAND storage string comprises multiple memory cell.Wherein Fig. 2 (a) is the profile of storage string structure, the vertical view that Fig. 2 (b) is storage string.By reference to the accompanying drawings, details are as follows for its structure:
According to an embodiment of the present utility model, this three-dimensional storage comprises the three dimensional NAND storage string (NAND storage string) of multiple vertical direction.As shown in Fig. 2 (a) He (b), a three dimensional NAND storage string comprises: be positioned at the horizontal substrate 100 of bottom, perpendicular to substrate cylindrical semiconductive region 1, be positioned at semiconductor regions about 1 electrode 201 and electrode 202, parcel cylindrical semiconductive region 1 Tunneling dielectric 11, distributed multiple discrete charge storage layer 9, the obstruct dielectric layer 7 having wrapped up Tunneling dielectric 11 and multiple charge storage layer 9 and the outermost control grid electrode 121 mutually stacking with insulating barrier 122 around Tunneling dielectric about 11.
In the utility model, the source and drain areas of the different units on same memory cell string and channel region adopt commaterial, define without junction device in one, namely there is not PN junction between source-drain electrode and raceway groove.Channel region is formed perpendicular to substrate direction, the source-drain electrode series connection of the different units on same memory cell string, and adopts the commaterial preparation identical with channel region.Source, leakage, raceway groove adopt without junction structure, and namely the source drain of memory cell and raceway groove have identical carrier concentration, tying transoid device, having better short-channel properties and Sub-Threshold Characteristic without junction structure compared with having.
In the utility model, the single memory cell in three-dimensional semiconductor memory adopts encloses grid structure.Enclose grid structure to comprise dielectric and wrap up channel region completely, and gate electrode wraps up gate dielectric completely.
In the utility model, as shown in Figure 2, substrate 100 is positioned at the bottommost of whole storage string structure, in the horizontal direction, the range of choice of substrate is very wide, can be any semi-conducting material, such as monocrystalline silicon, IV-IV compounds of group such as SiGe or SiGeC compounds, III-V, II-VI group compound, the epitaxial loayer that formed of face on such substrates, or any other semiconductor or non-semiconducting material, such as silica, glass, plastics, metal or ceramic substrate.Substrate 100 can be included in the integrated circuit prepared on it, the drive circuit of such as memory device.
In the utility model, as shown in Figure 2, semiconductor regions 1 comprises the source region of multiple memory cell, drain region and raceway groove, semiconductor regions is positioned at the bosom of three dimensional NAND storage string, with substrate transverse, be cylindrical structure, its body diameter is in 20nm to 100nm scope.Cylindrical semiconductive region 1 is formed by the raceway groove of multiple memory cell, source electrode, drain series, because the source electrode of memory cell each in this structure, drain electrode and raceway groove adopt high carrier concentration material of the same race, so adopt commaterial to fill in cylindrical semiconductive region 1.Cylindrical semiconductive region 1 adopts chalcogenide compound material to prepare, such as Sb2Te3, GeTe material, can adopt the depositional mode preparations such as molecular beam epitaxy (MBE, MOLECULAR BEAM EPITAXY), magnetron sputtering.Wherein for molecular beam epitaxy (MBE, MOLECULAR BEAM EPITAXY) etc. technology directly can prepare the materials such as Sb2Te3, GeTe of crystalline state, for depositional modes such as magnetron sputterings, what deposition obtained is amorphous material, need to carry out annealing in process after completing primary depositing, amorphous state is treated to crystalline state.
In the utility model, depositing operation after raceway groove can be adopted, adopt the chalcogenide compound semi-conducting material deposited as channel material, channel material can adopt chalcogenide compound material, chalcogenide compound material has high intrinsic carrier concentration, and it can adopt the techniques such as molecular beam epitaxy to carry out the deposition of raceway groove.Chalcogenide compound comprises the materials such as Sb2Te3, GeTe, BiTe, and can form monocrystalline or polycrystalline according to different preparation technologies, these materials have higher intrinsic carrier concentration.
In the utility model, as shown in Figure 2, electrode 202 and electrode 201 lay respectively at the two ends up and down in region 1, its distribution is determined according to the reading circuit of storage string, it is that electrode 202 is connected (one of operating line when wordline described here is memory operation) as top electrode with wordline that ordinary circumstance bottom electrode 201 connects place as bottom electrode.Electrode 201 is connected with region 1 respectively with 202, as source electrode and drain electrode in storage string work.
In the utility model, as shown in Figure 2, region 11 is Tunneling dielectric, and Tunneling dielectric is positioned at the periphery in region 1, has wrapped up region 1 completely, Tunneling dielectric 11 one-tenth hollow cylinder.It is when this memory device write data, and high grid voltage can make the electric charge in raceway groove be tunneling in charge storage floating gate from Tunneling dielectric, thus realizes the write of data.Tunneling dielectric can be form silicon oxide layer by ald (ALD) or chemical meteorology deposition (CVD) method.Tunnelling dielectric substrate 11 thickness is within the scope of 5 to 20nm.
In the utility model, as shown in Figure 2, a three dimensional NAND storage string comprises multiple control grid electrode 121, control grid electrode is parallel to substrate 100, distribute in stacked on top, separated by dielectric 122 between multiple control grid electrode, between gate electrode and dielectric, form alternate stacked structure.Control grid electrode 121 at least comprises the first control grid electrode that is positioned at the first device level (the horizontal A of device), on the surperficial 100a of substrate 100, under the horizontal A of device, second control grid electrode of the second device level (the horizontal B of device) is positioned at one.Control grid electrode material has multiple choices, such as doped polycrystalline silicon, tungsten, copper, aluminium, tantalum, titanium, cobalt, titanium nitride or their alloy.For example, in certain embodiments, polysilicon is used because of easily preparing.Control grid electrode 121, insulating barrier 122 can be 6 to 100 nanometer thickness.Wherein, control grid electrode 121 generally adopts conductor (such as metal or metal alloy) or the semiconductor control gate material such as (such as heavy doping n+, p+ polysilicon), and dielectric 122 adopts edge material (such as silicon nitride, silica etc.).Described heavy doping comprises semi-conducting material Doped n-type or p-type concentration is greater than 10
18cm
-3.
Intercept dielectric layer 7 adjacent with control grid electrode 121, intercept dielectric layer 7 and surrounded by the stacked structure of control grid electrode 121 with insulating medium layer 122, intercept dielectric layer 7 and comprise multiple " pincer structure ".Described " pincer " is that its cross sectional shape is as English alphabet " C ".A pincer has two mutual almost parallel parts, simultaneously also parallel with substrate 100.Intercepting medium 7 with tunnel dielectric 11 can be independent from any one or more identical or different electrical insulating materials selection, such as silica, silicon nitride, silicon oxynitride, or other high-k insulating material.
As shown in Figure 2, a three dimensional NAND also comprises multiple discrete charge storage layer 9, and each is arranged in each pincerlike opening intercepting part 7 at least in part.Similarly, multiple discrete charge storage layer 9 comprises the first discrete charge storage layer that at least one is positioned at the horizontal A of device, and is positioned at the second discrete charge storage layer of the horizontal B of device.Discrete charge storage layer 9 can comprise a conductor (metal or metal alloy, for example titanium, platinum, ruthenium, titanium nitride, hafnium nitride, tantalum nitride, zirconium nitride, or metal silicide, for example titanium silicide, nickle silicide, cobalt silicide, or their mixture), or semiconductor (such as polysilicon) floating boom, conductor nano particle, or discrete charge storage dielectric (such as silicon nitride or other dielectric), etc.
In traditional handicraft, flash cell is when selecting the raceway groove of low doping concentration, its grid not making alive time, raceway groove carriers is little, disconnect between source electrode and drain electrode, when grid is added to threshold voltage, form inversion charge in raceway groove, conducting between source electrode and drain electrode, the break-make that therefore can control between source electrode and drain electrode by grid voltage.And in the utility model, select the channel material of high carrier concentration, grid not making alive time, raceway groove carriers concentration is high, conducting between source electrode and drain electrode, when grid is added to threshold voltage, raceway groove carriers exhausts completely, and source electrode is separated with drain electrode, thus realizes by the break-make between grid voltage control source electrode and drain electrode.
By applying tunneling voltage for grid, the charge carrier in raceway groove being tunneling in floating grid and storing, realizing the write of data, by applying reverse tunnel voltage, making the electric charge tunnelling stored in floating boom in raceway groove, realizing the erasing of data.The electric charge be stored in floating boom can provide voltage to make the carrier depletion in raceway groove to control the break-make of source electrode and drain electrode, thus realizes the reading of data.
The utility model additionally provides a kind of preparation method of nonvolatile three-dimensional semiconductor memory, and as shown in Fig. 3-Figure 12, the preparation process of NAND storage string specifically comprises the steps:
Step one: as described in reference to fig. 3, on the substrate 100 that distributed bottom electrode 201, deposit multilayer membrane stack structure 120,120 forms by control grid electrode 121 is alternate with dielectric 122.Then in the stacked structure formed, carry out deep hole etching, form through hole 80, as shown in Figure 4.
Wherein, control grid electrode 121, dielectric 122 can with any suitable deposition processs, such as sputtering, CVD, molecular beam epitaxy (MBE, MOLECULAR BEAM EPITAXY) etc., are deposited on substrate.Control grid electrode 121, dielectric 122 can be 6 to 100 nanometer thickness.In the present embodiment, control grid electrode 121 can select conductor (such as metal or metal alloy) or semiconductor (such as heavy doping n+, p+ polysilicon), and dielectric 122 can select insulating material (such as silicon nitride, silica etc.).Described heavy doping comprises semi-conducting material Doped n-type or p-type concentration is greater than 10
18cm
-3.201 as bottom electrode, can be the metal material of the low work function of Al, Ta and so on, can adopt the film-forming method preparations such as sputtering, evaporation.
Step 2: as shown in Figure 5, the through hole 80 formed in step one, carries out selective etch control grid electrode 121, forms structure as shown in Figure 5.Wherein, relative to dielectric 122, control grid electrode 121 is optionally etched, and forms the first pit 62 at ground floor control grid electrode 121.Pit 62 can use optionally isotropic wet etching or dry etching, and wherein selective etch refers to that opposing insulation medium 122 etches control grid electrode 121, and isotropic etching refers at all directions etching depth of etching identical.The degree of depth of pit 62 can be 20 to 100 nanometers.
Step 3: successively deposition intercepts dielectric substance and charge storage material successively in through hole 80, as shown in Figure 6 and Figure 7.Then carry out etching and again form through hole 80, and form obstruct dielectric layer 7 and charge storage layer 9 simultaneously, as shown in Figure 8.
7 for intercepting dielectric, can be to form silicon oxide layer by ald (ALD) or chemical meteorology deposition (CVD) method, or other high-k dielectric substance, such as hafnium oxide, and its deposit thickness is 5 to 20nm.9 is charge storage layer, can comprise a charge storage dielectric material (such as silicon nitride discrete charge storage dielectric medium structure).Removably, charge storage material can comprise conductor or semiconductor floating gate material (such as, metal, metal mixture, metal silicide or middle doped polycrystalline silicon floating gate material), any available method may be used to form charge storage material.The thickness of described obstruct dielectric layer 7 is 5nm-20nm; The thickness of described charge storage layer 9 is 15nm-80nm;
Step 4: and Tunneling dielectric material is deposited in through hole 80, as shown in Figure 9.Then form through hole 81 by carrying out etching to Tunneling dielectric material and form tunnel dielectric layer 11, as shown in Figure 10.Then deposited semiconductor region 1 in through hole 81, as shown in figure 11.
Described tunnel dielectric layer 11 thickness is 5nm-20nm; The diameter forming through hole 81 is 15nm-80nm;
Wherein, tunnel dielectric layer 11 can be form silicon oxide layer by ald (ALD) or chemical meteorology deposition (CVD) method.
Wherein, semiconductor regions 1 contains drain region, source region and the channel part of device, formed by commaterial, semiconductor regions 1 can Sb2Te3 material, GeTe material, Bi2Te3 material, SnTe material, Bi2Se3 material, GeSe material, PbTe material, the chalcogenide compound materials such as SnSe material, molecular beam epitaxy (MBE can be adopted, MOLECULAR BEAM EPITAXY), metallo-organic compound chemical gaseous phase deposition (MOCVD, Metal-organic Chemical Vapor Deposition), plasma enhanced chemical vapor deposition method (PECVD, Plasma Enhanced Chemical Vapor Deposition), ald (ALD, Atomic layer deposition) homepitaxy mode deposits, also crystallization is carried out again after the modes such as sputtering can be adopted to deposit.
Step 5: finally carrying out photolitographic deposition top electrode 202, as shown in figure 12.
Wherein, top electrode 202 and bottom electrode 201 are prepared from by same material.Be mainly the metal material that the work functions such as Cu, Ta are close with chalcogenide compound material work functions, easily form ohmic contact.Top electrode 202 can adopt with the preparation of bottom electrode 201 sputter, prepared by the mode such as evaporation.
In order to the preparation method of the nonvolatile three-dimensional semiconductor memory that further description the utility model embodiment provides, now provide specific embodiment, in order to avoid loaded down with trivial details, provide the value of parameters in each specific embodiment in the mode of list, specifically refer to following table:
Following description is made for parameter described in above-described embodiment: the second through hole 81 diameter determines that the canal cross section of device amasss, during devices function, canal cross section is long-pending larger, and source and drain saturation current during its work is larger, and raceway groove needs the threshold voltage required for cut-off larger.The difference of the first through hole 80 diameter and the second through hole 81 diameter is the thickness of tunnel dielectric layer 11, and its thickness is associated with canal cross section diameter, and the increase equal proportion long-pending along with canal cross section increases.The thickness intercepting dielectric layer 7 is associated with canal cross section diameter, and along with the increase of canal cross section diameter, the thickness intercepting dielectric layer needs to make corresponding equal proportion and increases.Thickness and the canal cross section diameter of charge storage layer 9 have relevance, and canal cross section diameter is larger, needs more magnitude of the stored charge, so the thickness of charge storage layer and canal cross section diameter are geometric ratio relations.The degree of depth of pit 62 is by charge storage layer 9 and intercepts dielectric layer 7 sum.Thickness and the above-mentioned parameter of this external insulation layer 122 and control grid electrode 121 do not have proportionate relationship, and insulating barrier 122 and control grid electrode 121 determine the channel length of device, and channel length reduces, and threshold voltage is less.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all do within spirit of the present utility model and principle any amendment, equivalent to replace and improvement etc., all should be included within protection range of the present utility model.
Claims (5)
1. a nonvolatile three-dimensional semiconductor memory, comprises the three dimensional NAND storage string of multiple vertical direction, it is characterized in that, each three dimensional NAND storage string comprises:
Horizontal substrate (100), perpendicular to the cylindrical semiconductive region (1) of described substrate (100), lay respectively on described semiconductor regions (1), under the second electrode (202) and the first electrode (201), wrap up the Tunneling dielectric (11) of described cylindrical semiconductive region (1), around on Tunneling dielectric (11), under distributed multiple discrete charge storage layer (9), wrap up the obstruct dielectric layer (7) of Tunneling dielectric (11) and multiple charge storage layer (9), and the control grid electrode (121) that outermost is mutually stacking with insulating barrier (122),
Described cylindrical semiconductive region (1) comprises the source region of multiple memory cell, drain region and raceway groove; Commaterial is all adopted to fill; Between source region and raceway groove, do not form PN junction, between drain region and raceway groove, do not form PN junction;
Described channel region is cylindrical, and described control grid electrode (121) encloses grid structure around described channel region formation.
2. nonvolatile three-dimensional semiconductor memory as claimed in claim 1, it is characterized in that, the body diameter of described cylindrical semiconductive region (1) is 20nm ~ 100nm.
3. nonvolatile three-dimensional semiconductor memory as claimed in claim 1, is characterized in that, in described cylindrical semiconductive region (1), source region, drain region and raceway groove all adopt chalcogenide compound material to prepare.
4. as nonvolatile three-dimensional semiconductor memory as claimed in claim 3, it is characterized in that, described chalcogenide compound material comprises Sb2Te3 material, GeTe material, Bi2Te3 material, SnTe material, Bi2Se3 material, GeSe material, PbTe material, SnSe material.
5. nonvolatile three-dimensional semiconductor memory as claimed in claim 3, it is characterized in that, the intrinsic carrier concentration of described chalcogenide compound material is 10
18cm
-3-10
20cm
-3.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241294A (en) * | 2014-09-16 | 2014-12-24 | 华中科技大学 | Nonvolatile three-dimensional semiconductor memory and manufacturing method thereof |
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