CN204086904U

CN204086904U - A kind of two AD sampling plate

Info

Publication number: CN204086904U
Application number: CN201420603504.8U
Authority: CN
Inventors: 毛健; 封孝松; 周宽裕; 黄娟梅; 李永年
Original assignee: China Yangtze Power Co Ltd
Current assignee: China Yangtze Power Co Ltd
Priority date: 2014-10-20
Filing date: 2014-10-20
Publication date: 2015-01-07
Anticipated expiration: 2024-10-20

Abstract

A kind of two AD sampling plate, comprises 6 4x2 analog switches, 34 tunnel amplifiers, two panels 6 road A/D chips.Described 6 4x2 analog switches are divided into two groups, each group comprises 4x6 way switch array, totally two groups of 4x6 way switch arrays, 24 road analog input signals deliver to two groups of 4x6 way switch arrays simultaneously, under one-chip computer module controls, have 6 road signals after 3 totally 12 amplifier unit bufferings, be added on the A/D chip of two panels 6 road, described A/D chip connects one-chip computer module at every turn; One-chip computer module connects CPLD module, CPLD model calling STD bus.A kind of two AD sampling plate of the utility model; the signal need sampled for each road all adopts two-way independently to gather respectively in AD loop, when a certain passage appoints element fault, can provide signal in time; and locking relay protection outlet, thus reach the function improving relay protection performance factor.

Description

A kind of two AD sampling plate

Technical field

The utility model relates to a kind of sampling plate, particularly a kind of two AD sampling plate.

Background technology

Protective relaying device be that one can be reacted electrical equipment in electric system and broken down or irregular operating state, and action is in circuit breaker trip or the aut.eq. sending signal.Just generally speaking, a whole set of relay protection is grouped into by measure portion, logical gate and enforcement division.Wherein, measure portion measures the relevant electric parameters from protected object input, and compare with given setting valve, according to the result compared, provides one group of logical signal, thus judge whether protection should start.So the performance of measure portion is the important foundation of whole protective relaying device.The measure portion of traditional generator, Transformer protective relaying device; general all uses single channel modulus acquisition mode; namely the alternating current need sampled to each road, voltage signal passage adopt a road AD circuit to carry out data acquisition, and each road AD circuit component comprises: sampling resistor, multi-way switch, sampling capacitance, AD conversion loop.

But when on this AD loop when component wear or hydraulic performance decline, sampled data will be caused abnormal, the problem that protective relaying maloperation is done may be caused.Although can consider on protection algorism software that the locking of some data exceptions differentiates measure, sampling abnormal data fundamentally can not be eliminated on the impact of relay protection action logic, particularly to ask for something QA protection in 40 milliseconds.In actual motion, when often there is sampling system fault, cannot effectively latch-up protection, cause the phenomenon that protective relaying maloperation is done.

Summary of the invention

For the above-mentioned defect of traditional single channel modulus sampling plate; the utility model provides a kind of two AD sampling plate; the signal need sampled for each road all adopts two-way independently to gather respectively in AD loop; when a certain passage appoints element fault; signal can be provided in time; and locking relay protection outlet, thus reach the function improving relay protection performance factor.

The technical scheme that the utility model is taked is: a kind of two AD sampling plate, comprises 6 4x2 analog switches, 34 tunnel amplifiers, two panels 6 road A/D chips.Described 6 4x2 analog switches are divided into two groups, each group comprises 4x6 way switch array, totally two groups of 4x6 way switch arrays, 24 road analog input signals deliver to two groups of 4x6 way switch arrays simultaneously, under one-chip computer module controls, have 6 road signals after 3 totally 12 amplifier unit bufferings, be added on the A/D chip of two panels 6 road, described A/D chip connects one-chip computer module at every turn; One-chip computer module connects CPLD module, CPLD model calling STD bus.

Described CPLD model calling SRAM module, described A/D chip is AD7656 chip, and described one-chip computer module is 89C52 single-chip microcomputer.

A kind of two AD sampling plate of the utility model, technique effect is as follows:

1), this sampling plate is a block I/O intelligent plate, and self is with CPU, program and data-carrier store.

2), adopt highly reliable two panels AD7656 as A/D chip, it is a kind of high integration, 6 passages, 16 SAR ADC, has the sampling rate of every passage up to 250kSPS, and in sheet, comprise a 2.5V internal source voltage and reference buffer.And this device only has the power consumption of 160mW, input the lower power consumption of ADC 60% than immediate similar bipolarity;

3), adopt 8 group of No. 6 multi-way switch, 2 group of 6 road signal gathers (namely 1 road signal gathers 2 times simultaneously) simultaneously.Switching time is 3 microseconds only, be very suitable for gathering simultaneity and require higher, and acquisition and processing requires also higher electric system protection device;

4), by STD bus definition design interface module, host CPU plate can realize operation by bus to it;

5), all TTL logical circuits put into piece of CPLD, simplify the structure of circuit board.

Accompanying drawing explanation

Fig. 1 is the two AD sampling plate structural representation of the utility model.

Embodiment

As shown in Figure 1, a kind of two AD sampling plate, comprises 6 4x2 analog switches, 34 tunnel amplifiers, two panels 6 road A/D chips.Described 6 4x2 analog switches are divided into two groups, each group comprises 4x6 way switch array, totally two groups of 4x6 way switch arrays, 24 road analog input signals deliver to two groups of 4x6 way switch arrays simultaneously, under one-chip computer module controls, have 6 road signals after 3 totally 12 amplifier unit bufferings, be added on the A/D chip of two panels 6 road, described A/D chip connects one-chip computer module at every turn.One-chip computer module connects CPLD module, CPLD model calling STD bus.Described CPLD model calling SRAM module.Described A/D chip is AD7656.Described one-chip computer module is 89C52 single-chip microcomputer.

A kind of two AD sampling plate of the utility model, principle of work in two sub-sections:

Part I is simulation part: form primarily of 6 4x2 analog switches, 34 tunnel amplifiers and two panels 6 road A/D chip.6 4x2 analog switches are divided into two groups, often group comprises 4x6 way switch array, 24 road analog input signals deliver to two groups of 4x6 way switch arrays simultaneously, under the control of one-chip computer module, there are 6 road signals after 3 totally 12 amplifier unit bufferings at every turn, be added on 26 road A/D chips, control by single-chip microcomputer control module, 26 road A/D chips complete the A/D conversion of 6 road signals simultaneously.One-chip computer module can with interruption or inquiry mode after A/D completes, read the A/D result of 2 groups of each 6 road input signals.

A0, A1 of analog switch are connected respectively to P1.0 and the P1.1 pin of single-chip microcomputer; The conversion of A/D chip starts the P1.3 pin that pin is connected to one-chip computer module simultaneously, the transition of this pin from low level to high level triggers an A/D conversion process, the BUSY signal of A/D chip becomes high level simultaneously, after about 3 microseconds, the A/D of 6 road signals has converted, BUSY signal recuperation low level, therefore, the negative edge triggered interrupts of BUSY can be utilized, or find that it reads A/D data from after high step-down by inquiry.

Part II is numerical portion: be made up of the SRAM module of single-chip microcomputer, M4A5-128/64CPLD and optional 32K.The interface logic of Bus isolation, decoding logic and STD bus required on board is all integrated in CPLD.Because the resolution bits 16 of A/D, hardware setting are the preceding reading manner of high byte, need when therefore single-chip microcomputer reads the A/D data of 6 passages to read 12 times continuously.

Claims

1. a two AD sampling plate, comprise 6 4x2 analog switches, 34 tunnel amplifiers, two panels 6 road A/D chips, it is characterized in that, described 6 4x2 analog switches are divided into two groups, and each group comprises 4x6 way switch array, totally two groups of 4x6 way switch arrays, 24 road analog input signals deliver to two groups of 4x6 way switch arrays simultaneously, under one-chip computer module controls, have 6 road signals after 3 totally 12 amplifier unit bufferings at every turn, be added on the A/D chip of two panels 6 road, described A/D chip connects one-chip computer module; One-chip computer module connects CPLD module, CPLD model calling STD bus.

2. a kind of two AD sampling plate according to claim 1, is characterized in that, CPLD model calling SRAM module.

3. a kind of two AD sampling plate according to claim 1, it is characterized in that, described A/D chip is AD7656 chip.

4. a kind of two AD sampling plate according to claim 1, it is characterized in that, described one-chip computer module is 89C52 single-chip microcomputer.