CN204009879U

CN204009879U - Logic analyser

Info

Publication number: CN204009879U
Application number: CN201420410283.2U
Authority: CN
Inventors: 唐剑
Original assignee: IPGoal Microelectronics Sichuan Co Ltd
Current assignee: IPGoal Microelectronics Sichuan Co Ltd
Priority date: 2014-07-23
Filing date: 2014-07-23
Publication date: 2014-12-10
Anticipated expiration: 2024-07-23

Abstract

The utility model discloses a kind of logic analyser, comprise data acquisition module, clock trigger module, PCIE controller, PCIE interface, described data acquisition module is connected with described clock trigger module and PCIE controller respectively, and described PCIE interface is connected with described PCIE controller and host interface respectively; Described data acquisition module is according to the data of the frequency collection input of the clock of described clock trigger module output, the data packing that described PCIE controller obtains described data collecting module collected, the data after packing transfer to host interface by described PCIE interface.Logic analyser of the present utility model utilizes the high bandwidth of PCIE, omits logic analyser internal data storage unit, simple in structure and provide cost savings and simplified design, has improved the performance of logic analyser.

Description

Logic analyser

Technical field

The utility model relates to integrated circuit fields, relates more specifically to a kind of logic analyser.

Background technology

Logic analyser can be divided into stand alone type (or stand-alone type) logic analyser and the PC-based cassette FVLA based on computer.Stand alone type logic analyser is that all testing softwares, computing managent component are incorporated among an instrument; Logic analyser based on the PC computer that needs to arrange in pairs or groups uses together, and display screen also separates with main frame.The existing logic analyser based on PC generally adopts USB2.0 to connect main frame, and they support plug and play, uses easily.This USB2.0 logic analyser includes data acquisition unit, data storage cell, data retransmission unit etc.Be subject to the restriction of USB2.0 bandwidth, its index is up to 16 passages, the sampling rate of 200mhz, and performance is unoutstanding.

Due to USB2.0 limit bandwidth, the data in logic analyser cannot be real-time transmitted to computing machine, thereby need data storage cell storage data, make data storage cell become the requisite part of all USB2.0 logic analysers.Notoriously, the storage depth of the big or small decision logic analyser of data storage cell.Due to cost restriction, the data storage cell of USB2.0 logic analyser the inside only can provide the storage depth of every passage 2M-4Mbit, is nowhere near for the incompatible theory of checkout area of many complexity.Will increase data storage cell and increase storage depth, and cause cost to rise.And due to this kind of logic analyser image data, transmitting data to main frame can not carry out simultaneously, after triggering, need to wait for that local data moves main frame, cause the response after software triggers very slow, have a strong impact on user and experience and work efficiency.

Therefore, be necessary to provide a kind of improved logic analyser to overcome above-mentioned defect.

Utility model content

The purpose of this utility model is to provide a kind of logic analyser.Logic analyser of the present utility model utilizes the high bandwidth of PCIE, omits logic analyser internal data storage unit, simple in structure and provide cost savings and simplified design, has improved the performance of logic analyser.

For achieving the above object, the utility model provides a kind of logic analyser, comprise data acquisition module, clock trigger module, PCIE controller, PCIE interface, described data acquisition module is connected with described clock trigger module and PCIE controller respectively, and described PCIE interface is connected with described PCIE controller and host interface respectively; Described data acquisition module is according to the data of the frequency collection input of the clock of described clock trigger module output, the data packing that described PCIE controller obtains described data collecting module collected, the data after packing transfer to host interface by described PCIE interface.

Preferably, between described PCIE interface and host interface, be connected by bus.

Preferably, described bus is PCIE x4 cable.

Preferably, described bus is PCIE x1 cable.

Compared with prior art, logic analyser of the present utility model, owing to comprising PCIE controller and PCIE interface, thereby can utilize the high bandwidth of PCIE, omit logic analyser internal data storage unit, directly use the internal memory of main frame as primary data storage cell, its storage depth of data storage cell on the logic analyser of prior art extends to the level of GB rank from MB rank, thereby makes more than the storage depth of logic analyser reaches every path 10 0MB; And the real-time of test greatly improves, can make software show in real time, response rapidly, has improved user's work efficiency greatly.

By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.

Brief description of the drawings

Fig. 1 is the structured flowchart that the utility model logic analyser is connected with host interface.

Embodiment

With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similarly element numbers represents similar element.As mentioned above, the utility model provides a kind of logic analyser, and logic analyser of the present utility model utilizes the high bandwidth of PCIE, omits logic analyser internal data storage unit, simple in structure and provide cost savings and simplified design, improve the performance of logic analyser.

Please refer to Fig. 1, as shown in the figure, logic analyser of the present utility model comprises data acquisition module, clock trigger module, PCIE controller, PCIE interface; Described data acquisition module is connected with described clock trigger module and PCIE controller respectively, described PCIE interface is connected with described PCIE controller and host interface respectively, described data acquisition module is according to the data data0 of the frequency collection input of the clock of described clock trigger module output, described clock trigger module produces clock information, think that described logic analyser and host communication provide communication frequency, the data packing that described PCIE controller obtains described data collecting module collected, the data after packing transfer to host interface by described PCIE interface.

And in preferred implementation of the present utility model, between described PCIE interface and host interface, be connected by bus, wherein, bus can be PCIE x4 cable or PCIE x1 cable.

Below in conjunction with reference to figure 1, principle of work and the course of work of the utility model logic analyser described.Logic analyser of the present utility model is coordinated and is obtained data by data acquisition module and clock trigger module, next give PCIE controller, send host interface to by PCIE interface and PCIE cable, the processor of main frame is data from host interface extracts and be stored to its internal memory, and main frame is delivered to the demonstration of display port (not shown) data simultaneously.

The leading indicator of logic analyser is sampling rate, number of active lanes and storage depth.Because logic analyser of the present utility model does not have local storage unit, the bandwidth of PCIE just determines sampling rate and number of active lanes, and the memory size of main frame determines the storage depth of each passage.

If the number of active lanes of logic analyser of the present utility model is 32 passages, adopt the cable of PCIE x4 to connect main frame, and the PCIE interface of main frame meet PCIE3.0 agreement, the bandwidth of each passage is 8Gbit/s exactly.The total bandwidth of PCIE3.0x4 is 8G x4 so, and PCIE3.0 is the 128/130b coded system adopting, and data transmission rate is exactly 8x4x128/ (130*8) ≈ 32Gbit/s.So in theory, the logic analysis instrument of 32 passages just can provide the sampling rate of each passage 32/32=1Gbit/s.In addition, storage depth is decided by the size of internal memory, conventionally the internal memory of computing machine be all generally 2G to 4G, if with 1G internal memory as between data storage area, if 32 passages, the storage depth of every passage is just 1024*8/32=256Mbit/ch.

Because above-mentioned bandwidth calculation is theoretical value, actual bandwidth is subject to main frame actual conditions discount, in order to ensure that logic analyser of the present utility model can steady operation, in the utility model, in the time of logic analyser software startup, pair logic analyser being connected with host interface carries out velocity test, read the transmitting-receiving buffer area that the inner PCIE controller of logic analyser contains, to obtain the concrete transfer efficiency of current platform.If transfer efficiency only has theoretical value to obtain 80%, the port number that or user arrange just can not reach maximum, or the sampling rate that user arranges just can not be set to maximum.These restrictions all can be informed in advance at the interface of software startup, or be informed in the concrete setting of user.

In addition, the power supply mode of logic analyser of the present utility model can be selected outer power supply or the power supply of PCIE cable; And the bus being connected between PCIE interface and host interface is selected PCIE x1 or PCIE x4 cable according to performance, and software and performance are just the same.

In conjunction with most preferred embodiment, the utility model is described above, but the utility model is not limited to the embodiment of above announcement, and should contains the various amendments of carrying out according to essence of the present utility model, equivalent combinations.

Claims

1. a logic analyser, is characterized in that, comprises data acquisition module, clock trigger module, PCIE controller, PCIE interface; Described data acquisition module is connected with described clock trigger module and PCIE controller respectively, described PCIE interface is connected with described PCIE controller and host interface respectively, described data acquisition module is according to the data of the frequency collection input of the clock of described clock trigger module output, the data packing that described PCIE controller obtains described data collecting module collected, the data after packing transfer to host interface by described PCIE interface.

2. logic analyser as claimed in claim 1, is characterized in that, between described PCIE interface and host interface, is connected by bus.

3. logic analyser as claimed in claim 2, is characterized in that, described bus is PCIE x4 cable.

4. logic analyser as claimed in claim 2, is characterized in that, described bus is PCIE x1 cable.